| T1564 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_fmt_empty.2980270127 |
|
|
Sep 01 07:33:52 AM UTC 24 |
Sep 01 07:34:17 AM UTC 24 |
1569963633 ps |
| T1565 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.3583940168 |
|
|
Sep 01 07:33:56 AM UTC 24 |
Sep 01 07:34:19 AM UTC 24 |
1231955116 ps |
| T1566 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_hrst.3727795611 |
|
|
Sep 01 07:34:16 AM UTC 24 |
Sep 01 07:34:19 AM UTC 24 |
264469365 ps |
| T1567 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2000491329 |
|
|
Sep 01 07:31:26 AM UTC 24 |
Sep 01 07:34:21 AM UTC 24 |
9404145484 ps |
| T1568 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.2115680706 |
|
|
Sep 01 07:34:16 AM UTC 24 |
Sep 01 07:34:23 AM UTC 24 |
3554338944 ps |
| T1569 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_perf.4132882933 |
|
|
Sep 01 07:34:16 AM UTC 24 |
Sep 01 07:34:23 AM UTC 24 |
2205718774 ps |
| T1570 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_tx.3378256264 |
|
|
Sep 01 07:34:21 AM UTC 24 |
Sep 01 07:34:23 AM UTC 24 |
448921166 ps |
| T1571 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.3606033372 |
|
|
Sep 01 07:32:50 AM UTC 24 |
Sep 01 07:34:24 AM UTC 24 |
13610971572 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.2278010643 |
|
|
Sep 01 07:34:20 AM UTC 24 |
Sep 01 07:34:24 AM UTC 24 |
1751710562 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1593697488 |
|
|
Sep 01 07:34:22 AM UTC 24 |
Sep 01 07:34:26 AM UTC 24 |
630759175 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.3677354435 |
|
|
Sep 01 07:34:22 AM UTC 24 |
Sep 01 07:34:26 AM UTC 24 |
102009014 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3146113237 |
|
|
Sep 01 07:34:24 AM UTC 24 |
Sep 01 07:34:27 AM UTC 24 |
660927969 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.565366688 |
|
|
Sep 01 07:32:53 AM UTC 24 |
Sep 01 07:34:27 AM UTC 24 |
2497238993 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_alert_test.4006421225 |
|
|
Sep 01 07:34:25 AM UTC 24 |
Sep 01 07:34:27 AM UTC 24 |
28448152 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_smoke.2181096011 |
|
|
Sep 01 07:33:51 AM UTC 24 |
Sep 01 07:34:28 AM UTC 24 |
1576232416 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_override.3163544487 |
|
|
Sep 01 07:34:26 AM UTC 24 |
Sep 01 07:34:29 AM UTC 24 |
85344153 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.1446908553 |
|
|
Sep 01 07:34:24 AM UTC 24 |
Sep 01 07:34:29 AM UTC 24 |
520824528 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.4272642529 |
|
|
Sep 01 07:34:24 AM UTC 24 |
Sep 01 07:34:29 AM UTC 24 |
1080352399 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.913393668 |
|
|
Sep 01 07:34:17 AM UTC 24 |
Sep 01 07:34:31 AM UTC 24 |
9099184727 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.2562314057 |
|
|
Sep 01 07:34:29 AM UTC 24 |
Sep 01 07:34:31 AM UTC 24 |
219337732 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.2685688693 |
|
|
Sep 01 07:34:29 AM UTC 24 |
Sep 01 07:34:35 AM UTC 24 |
2436434557 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.2853154521 |
|
|
Sep 01 07:33:57 AM UTC 24 |
Sep 01 07:34:37 AM UTC 24 |
2290063438 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2836329636 |
|
|
Sep 01 07:34:29 AM UTC 24 |
Sep 01 07:34:38 AM UTC 24 |
992304234 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.2017836017 |
|
|
Sep 01 07:34:30 AM UTC 24 |
Sep 01 07:34:40 AM UTC 24 |
162579603 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_full.751558338 |
|
|
Sep 01 07:32:10 AM UTC 24 |
Sep 01 07:34:40 AM UTC 24 |
4283835553 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.2601142122 |
|
|
Sep 01 07:25:05 AM UTC 24 |
Sep 01 07:34:41 AM UTC 24 |
25484698252 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.1698865924 |
|
|
Sep 01 07:34:32 AM UTC 24 |
Sep 01 07:34:43 AM UTC 24 |
1322878276 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_full.1068690475 |
|
|
Sep 01 07:30:33 AM UTC 24 |
Sep 01 07:34:44 AM UTC 24 |
17536841253 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.1065656634 |
|
|
Sep 01 07:34:32 AM UTC 24 |
Sep 01 07:34:45 AM UTC 24 |
1025704657 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.4258778847 |
|
|
Sep 01 07:33:54 AM UTC 24 |
Sep 01 07:34:45 AM UTC 24 |
1663888670 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_stretch_timeout.978321708 |
|
|
Sep 01 07:33:54 AM UTC 24 |
Sep 01 07:34:47 AM UTC 24 |
5125749662 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.4067292182 |
|
|
Sep 01 07:34:42 AM UTC 24 |
Sep 01 07:34:48 AM UTC 24 |
1137440944 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.2098691059 |
|
|
Sep 01 07:34:46 AM UTC 24 |
Sep 01 07:34:49 AM UTC 24 |
336422007 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.614720657 |
|
|
Sep 01 07:33:52 AM UTC 24 |
Sep 01 07:34:49 AM UTC 24 |
3122818665 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.2281197965 |
|
|
Sep 01 07:34:46 AM UTC 24 |
Sep 01 07:34:49 AM UTC 24 |
577600223 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.4215007378 |
|
|
Sep 01 07:34:37 AM UTC 24 |
Sep 01 07:34:51 AM UTC 24 |
9639049841 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.2002930103 |
|
|
Sep 01 07:34:42 AM UTC 24 |
Sep 01 07:34:52 AM UTC 24 |
870304977 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/42.i2c_target_stress_wr.2004186464 |
|
|
Sep 01 07:31:35 AM UTC 24 |
Sep 01 07:34:52 AM UTC 24 |
49907782734 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_perf.3179083400 |
|
|
Sep 01 07:34:47 AM UTC 24 |
Sep 01 07:34:53 AM UTC 24 |
2049156380 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_mode_toggle.2394446908 |
|
|
Sep 01 07:34:51 AM UTC 24 |
Sep 01 07:34:53 AM UTC 24 |
178367768 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.1929547892 |
|
|
Sep 01 07:34:36 AM UTC 24 |
Sep 01 07:34:55 AM UTC 24 |
858470503 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.3759517097 |
|
|
Sep 01 07:34:51 AM UTC 24 |
Sep 01 07:34:56 AM UTC 24 |
3677058045 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.1613066391 |
|
|
Sep 01 07:34:53 AM UTC 24 |
Sep 01 07:34:56 AM UTC 24 |
575004364 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.304313632 |
|
|
Sep 01 07:34:52 AM UTC 24 |
Sep 01 07:34:57 AM UTC 24 |
1633584271 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.3394394274 |
|
|
Sep 01 07:34:53 AM UTC 24 |
Sep 01 07:34:57 AM UTC 24 |
87604391 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2212390003 |
|
|
Sep 01 07:34:49 AM UTC 24 |
Sep 01 07:34:57 AM UTC 24 |
1604970094 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.2706683779 |
|
|
Sep 01 07:34:44 AM UTC 24 |
Sep 01 07:34:57 AM UTC 24 |
5380300479 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_alert_test.1215942204 |
|
|
Sep 01 07:34:56 AM UTC 24 |
Sep 01 07:34:58 AM UTC 24 |
22474130 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.3125930661 |
|
|
Sep 01 07:34:54 AM UTC 24 |
Sep 01 07:34:59 AM UTC 24 |
493991455 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2981998417 |
|
|
Sep 01 07:34:55 AM UTC 24 |
Sep 01 07:34:59 AM UTC 24 |
2207758673 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.3340266840 |
|
|
Sep 01 07:34:56 AM UTC 24 |
Sep 01 07:34:59 AM UTC 24 |
123500416 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.2419324055 |
|
|
Sep 01 07:34:54 AM UTC 24 |
Sep 01 07:35:00 AM UTC 24 |
1630993703 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_override.3080357938 |
|
|
Sep 01 07:34:58 AM UTC 24 |
Sep 01 07:35:00 AM UTC 24 |
53643824 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/43.i2c_host_fifo_watermark.3632971067 |
|
|
Sep 01 07:32:09 AM UTC 24 |
Sep 01 07:35:02 AM UTC 24 |
47005970204 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/28.i2c_target_stress_wr.2200501335 |
|
|
Sep 01 07:23:24 AM UTC 24 |
Sep 01 07:35:02 AM UTC 24 |
45183467518 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.3717837978 |
|
|
Sep 01 07:35:00 AM UTC 24 |
Sep 01 07:35:02 AM UTC 24 |
101654507 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/41.i2c_host_fifo_watermark.581314906 |
|
|
Sep 01 07:30:31 AM UTC 24 |
Sep 01 07:35:06 AM UTC 24 |
4523746070 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2500426901 |
|
|
Sep 01 07:35:03 AM UTC 24 |
Sep 01 07:35:06 AM UTC 24 |
347998023 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/36.i2c_host_perf.588460625 |
|
|
Sep 01 07:27:20 AM UTC 24 |
Sep 01 07:35:06 AM UTC 24 |
50012412427 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.122298406 |
|
|
Sep 01 07:35:01 AM UTC 24 |
Sep 01 07:35:08 AM UTC 24 |
220131904 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_stretch.4267240618 |
|
|
Sep 01 07:35:09 AM UTC 24 |
Sep 01 07:35:11 AM UTC 24 |
301265326 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.876557295 |
|
|
Sep 01 07:35:00 AM UTC 24 |
Sep 01 07:35:12 AM UTC 24 |
169638068 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/43.i2c_host_perf.2840386818 |
|
|
Sep 01 07:32:10 AM UTC 24 |
Sep 01 07:35:14 AM UTC 24 |
5885417978 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.3715290841 |
|
|
Sep 01 07:35:00 AM UTC 24 |
Sep 01 07:35:16 AM UTC 24 |
918321723 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.2408992418 |
|
|
Sep 01 07:35:12 AM UTC 24 |
Sep 01 07:35:20 AM UTC 24 |
7278256695 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3344399702 |
|
|
Sep 01 07:35:20 AM UTC 24 |
Sep 01 07:35:23 AM UTC 24 |
184884940 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.2798301606 |
|
|
Sep 01 07:35:21 AM UTC 24 |
Sep 01 07:35:24 AM UTC 24 |
273158700 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.2703709723 |
|
|
Sep 01 07:35:15 AM UTC 24 |
Sep 01 07:35:27 AM UTC 24 |
1329820354 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.4153826314 |
|
|
Sep 01 07:34:42 AM UTC 24 |
Sep 01 07:35:32 AM UTC 24 |
7424127778 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.3093654452 |
|
|
Sep 01 07:35:06 AM UTC 24 |
Sep 01 07:35:32 AM UTC 24 |
775626261 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.590876883 |
|
|
Sep 01 07:34:57 AM UTC 24 |
Sep 01 07:35:34 AM UTC 24 |
1355276745 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_perf.2655036707 |
|
|
Sep 01 07:35:23 AM UTC 24 |
Sep 01 07:35:34 AM UTC 24 |
2186026990 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.2979364377 |
|
|
Sep 01 07:35:27 AM UTC 24 |
Sep 01 07:35:36 AM UTC 24 |
758804276 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.615329956 |
|
|
Sep 01 07:35:33 AM UTC 24 |
Sep 01 07:35:38 AM UTC 24 |
461429703 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.2812194555 |
|
|
Sep 01 07:35:37 AM UTC 24 |
Sep 01 07:35:39 AM UTC 24 |
146188533 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.2973206695 |
|
|
Sep 01 07:35:13 AM UTC 24 |
Sep 01 07:35:40 AM UTC 24 |
8744238394 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.731977755 |
|
|
Sep 01 07:35:36 AM UTC 24 |
Sep 01 07:35:40 AM UTC 24 |
1642726866 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.442388297 |
|
|
Sep 01 07:34:48 AM UTC 24 |
Sep 01 07:35:41 AM UTC 24 |
6854107697 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.2941023219 |
|
|
Sep 01 07:35:38 AM UTC 24 |
Sep 01 07:35:43 AM UTC 24 |
165517718 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.884191974 |
|
|
Sep 01 07:35:39 AM UTC 24 |
Sep 01 07:35:44 AM UTC 24 |
391221477 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.3511826223 |
|
|
Sep 01 07:35:35 AM UTC 24 |
Sep 01 07:35:44 AM UTC 24 |
1334388674 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_alert_test.4001940038 |
|
|
Sep 01 07:35:42 AM UTC 24 |
Sep 01 07:35:44 AM UTC 24 |
32675164 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_nack_txstretch.3418551207 |
|
|
Sep 01 07:35:41 AM UTC 24 |
Sep 01 07:35:44 AM UTC 24 |
276851963 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.371546574 |
|
|
Sep 01 07:35:40 AM UTC 24 |
Sep 01 07:35:45 AM UTC 24 |
1011052355 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/44.i2c_host_perf.144259926 |
|
|
Sep 01 07:32:53 AM UTC 24 |
Sep 01 07:35:45 AM UTC 24 |
6831399041 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_override.2203633473 |
|
|
Sep 01 07:35:44 AM UTC 24 |
Sep 01 07:35:46 AM UTC 24 |
93093747 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.1022650008 |
|
|
Sep 01 07:34:25 AM UTC 24 |
Sep 01 07:35:47 AM UTC 24 |
6402429976 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.3721528402 |
|
|
Sep 01 07:35:41 AM UTC 24 |
Sep 01 07:35:48 AM UTC 24 |
499492765 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.2598236241 |
|
|
Sep 01 07:35:46 AM UTC 24 |
Sep 01 07:35:48 AM UTC 24 |
1142460159 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/20.i2c_target_stress_wr.2000233667 |
|
|
Sep 01 07:18:41 AM UTC 24 |
Sep 01 07:35:49 AM UTC 24 |
53445002443 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.75574565 |
|
|
Sep 01 07:35:49 AM UTC 24 |
Sep 01 07:35:53 AM UTC 24 |
131122564 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.3865845899 |
|
|
Sep 01 07:35:46 AM UTC 24 |
Sep 01 07:35:53 AM UTC 24 |
384684693 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.4189650351 |
|
|
Sep 01 07:35:48 AM UTC 24 |
Sep 01 07:35:54 AM UTC 24 |
84667709 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.3717752446 |
|
|
Sep 01 07:35:03 AM UTC 24 |
Sep 01 07:35:56 AM UTC 24 |
4112701095 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.606184981 |
|
|
Sep 01 07:35:46 AM UTC 24 |
Sep 01 07:35:57 AM UTC 24 |
703401986 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.2654792140 |
|
|
Sep 01 07:34:40 AM UTC 24 |
Sep 01 07:35:59 AM UTC 24 |
3125077661 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.4023774761 |
|
|
Sep 01 07:27:03 AM UTC 24 |
Sep 01 07:36:00 AM UTC 24 |
106795910593 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.2592579265 |
|
|
Sep 01 07:36:00 AM UTC 24 |
Sep 01 07:36:04 AM UTC 24 |
1118168992 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.3514111042 |
|
|
Sep 01 07:35:58 AM UTC 24 |
Sep 01 07:36:08 AM UTC 24 |
860223336 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/28.i2c_host_perf_precise.884419586 |
|
|
Sep 01 07:23:22 AM UTC 24 |
Sep 01 07:36:08 AM UTC 24 |
23267328138 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.3740701250 |
|
|
Sep 01 07:35:58 AM UTC 24 |
Sep 01 07:36:11 AM UTC 24 |
790093439 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.3478414197 |
|
|
Sep 01 07:36:08 AM UTC 24 |
Sep 01 07:36:12 AM UTC 24 |
206920919 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.3553925781 |
|
|
Sep 01 07:36:09 AM UTC 24 |
Sep 01 07:36:13 AM UTC 24 |
356138702 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.2149890361 |
|
|
Sep 01 07:36:01 AM UTC 24 |
Sep 01 07:36:14 AM UTC 24 |
11129418788 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/40.i2c_host_perf.4211090145 |
|
|
Sep 01 07:29:57 AM UTC 24 |
Sep 01 07:36:14 AM UTC 24 |
25586659308 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_perf.3629950105 |
|
|
Sep 01 07:36:09 AM UTC 24 |
Sep 01 07:36:16 AM UTC 24 |
938939016 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3932814227 |
|
|
Sep 01 07:36:13 AM UTC 24 |
Sep 01 07:36:16 AM UTC 24 |
221650363 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3220124445 |
|
|
Sep 01 07:35:55 AM UTC 24 |
Sep 01 07:36:18 AM UTC 24 |
1275059466 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.1311962364 |
|
|
Sep 01 07:36:15 AM UTC 24 |
Sep 01 07:36:21 AM UTC 24 |
496403670 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.901629579 |
|
|
Sep 01 07:36:17 AM UTC 24 |
Sep 01 07:36:21 AM UTC 24 |
559609741 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.2541060356 |
|
|
Sep 01 07:35:53 AM UTC 24 |
Sep 01 07:36:21 AM UTC 24 |
1245635147 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.1190420345 |
|
|
Sep 01 07:35:48 AM UTC 24 |
Sep 01 07:36:22 AM UTC 24 |
570354982 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.220304469 |
|
|
Sep 01 07:36:18 AM UTC 24 |
Sep 01 07:36:22 AM UTC 24 |
696124814 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.103367063 |
|
|
Sep 01 07:35:07 AM UTC 24 |
Sep 01 07:36:22 AM UTC 24 |
5008313145 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_perf.4019186702 |
|
|
Sep 01 07:35:01 AM UTC 24 |
Sep 01 07:36:23 AM UTC 24 |
6566148911 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.1811869170 |
|
|
Sep 01 07:36:11 AM UTC 24 |
Sep 01 07:36:23 AM UTC 24 |
1144162806 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_alert_test.3552262944 |
|
|
Sep 01 07:36:21 AM UTC 24 |
Sep 01 07:36:23 AM UTC 24 |
18051900 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.3250404166 |
|
|
Sep 01 07:36:17 AM UTC 24 |
Sep 01 07:36:24 AM UTC 24 |
197371963 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/4.i2c_target_stress_wr.1005289742 |
|
|
Sep 01 07:12:02 AM UTC 24 |
Sep 01 07:36:58 AM UTC 24 |
62338760827 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1799571658 |
|
|
Sep 01 07:35:01 AM UTC 24 |
Sep 01 07:36:59 AM UTC 24 |
6458503919 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_override.1642427179 |
|
|
Sep 01 07:36:23 AM UTC 24 |
Sep 01 07:36:25 AM UTC 24 |
18785417 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.674896097 |
|
|
Sep 01 07:36:19 AM UTC 24 |
Sep 01 07:36:25 AM UTC 24 |
879871816 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.2965243182 |
|
|
Sep 01 07:36:20 AM UTC 24 |
Sep 01 07:36:25 AM UTC 24 |
393595858 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.1649693035 |
|
|
Sep 01 07:36:15 AM UTC 24 |
Sep 01 07:36:25 AM UTC 24 |
531195451 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.2279647729 |
|
|
Sep 01 07:36:24 AM UTC 24 |
Sep 01 07:36:27 AM UTC 24 |
389744429 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.2778920107 |
|
|
Sep 01 07:34:58 AM UTC 24 |
Sep 01 07:36:27 AM UTC 24 |
12496676790 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_perf.998881064 |
|
|
Sep 01 07:34:30 AM UTC 24 |
Sep 01 07:36:29 AM UTC 24 |
7080063547 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.878648298 |
|
|
Sep 01 07:36:26 AM UTC 24 |
Sep 01 07:36:29 AM UTC 24 |
433355459 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.2152199470 |
|
|
Sep 01 07:36:27 AM UTC 24 |
Sep 01 07:36:29 AM UTC 24 |
73092003 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.2022047721 |
|
|
Sep 01 07:36:24 AM UTC 24 |
Sep 01 07:36:32 AM UTC 24 |
338264678 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_perf.4100462245 |
|
|
Sep 01 07:36:25 AM UTC 24 |
Sep 01 07:36:34 AM UTC 24 |
1366010953 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_stretch.1776284528 |
|
|
Sep 01 07:36:30 AM UTC 24 |
Sep 01 07:36:35 AM UTC 24 |
755925862 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.2073198767 |
|
|
Sep 01 07:34:03 AM UTC 24 |
Sep 01 07:36:37 AM UTC 24 |
26949309909 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.2790717742 |
|
|
Sep 01 07:36:36 AM UTC 24 |
Sep 01 07:36:40 AM UTC 24 |
202230857 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1987548418 |
|
|
Sep 01 07:36:30 AM UTC 24 |
Sep 01 07:36:40 AM UTC 24 |
1912519833 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.93776354 |
|
|
Sep 01 07:36:38 AM UTC 24 |
Sep 01 07:36:41 AM UTC 24 |
358282927 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.2700030085 |
|
|
Sep 01 07:36:24 AM UTC 24 |
Sep 01 07:36:43 AM UTC 24 |
486366229 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.2748359234 |
|
|
Sep 01 07:36:32 AM UTC 24 |
Sep 01 07:36:43 AM UTC 24 |
4345429074 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2142528965 |
|
|
Sep 01 07:36:39 AM UTC 24 |
Sep 01 07:36:45 AM UTC 24 |
487848760 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.2600709764 |
|
|
Sep 01 07:36:43 AM UTC 24 |
Sep 01 07:36:46 AM UTC 24 |
245669617 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.1676067435 |
|
|
Sep 01 07:36:46 AM UTC 24 |
Sep 01 07:36:48 AM UTC 24 |
177439132 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.3537368559 |
|
|
Sep 01 07:36:41 AM UTC 24 |
Sep 01 07:36:50 AM UTC 24 |
1007880570 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.2996344685 |
|
|
Sep 01 07:36:46 AM UTC 24 |
Sep 01 07:36:50 AM UTC 24 |
269320428 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.2222131737 |
|
|
Sep 01 07:36:27 AM UTC 24 |
Sep 01 07:36:53 AM UTC 24 |
3464436026 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.1041107938 |
|
|
Sep 01 07:36:49 AM UTC 24 |
Sep 01 07:36:53 AM UTC 24 |
81954791 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.418809120 |
|
|
Sep 01 07:35:07 AM UTC 24 |
Sep 01 07:36:55 AM UTC 24 |
31948626791 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.869540065 |
|
|
Sep 01 07:36:51 AM UTC 24 |
Sep 01 07:36:56 AM UTC 24 |
886770286 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_nack_txstretch.3973085851 |
|
|
Sep 01 07:36:54 AM UTC 24 |
Sep 01 07:36:56 AM UTC 24 |
1143650126 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.273080923 |
|
|
Sep 01 07:36:51 AM UTC 24 |
Sep 01 07:36:57 AM UTC 24 |
529691171 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_alert_test.3830226414 |
|
|
Sep 01 07:36:56 AM UTC 24 |
Sep 01 07:36:58 AM UTC 24 |
121379384 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1083215681 |
|
|
Sep 01 07:35:24 AM UTC 24 |
Sep 01 07:36:59 AM UTC 24 |
16657526949 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.2212538849 |
|
|
Sep 01 07:36:54 AM UTC 24 |
Sep 01 07:36:59 AM UTC 24 |
940982782 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.2445854026 |
|
|
Sep 01 07:36:44 AM UTC 24 |
Sep 01 07:37:01 AM UTC 24 |
1570602104 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.1725932016 |
|
|
Sep 01 07:31:53 AM UTC 24 |
Sep 01 07:37:01 AM UTC 24 |
41070920249 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2069565220 |
|
|
Sep 01 07:33:57 AM UTC 24 |
Sep 01 07:37:03 AM UTC 24 |
45417260031 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.3040872687 |
|
|
Sep 01 07:35:44 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
13184975862 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.487316733 |
|
|
Sep 01 07:36:26 AM UTC 24 |
Sep 01 07:37:08 AM UTC 24 |
2713282318 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.3491358996 |
|
|
Sep 01 07:36:28 AM UTC 24 |
Sep 01 07:37:08 AM UTC 24 |
23904864645 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.4165744334 |
|
|
Sep 01 07:34:27 AM UTC 24 |
Sep 01 07:37:15 AM UTC 24 |
12605330679 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.2835156901 |
|
|
Sep 01 07:35:46 AM UTC 24 |
Sep 01 07:37:23 AM UTC 24 |
10470756616 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.3328809532 |
|
|
Sep 01 07:36:28 AM UTC 24 |
Sep 01 07:37:25 AM UTC 24 |
2049106406 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.2960119027 |
|
|
Sep 01 07:25:24 AM UTC 24 |
Sep 01 07:37:28 AM UTC 24 |
48205887375 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.2611590784 |
|
|
Sep 01 07:36:23 AM UTC 24 |
Sep 01 07:37:31 AM UTC 24 |
2187181085 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.3862938330 |
|
|
Sep 01 07:34:30 AM UTC 24 |
Sep 01 07:37:32 AM UTC 24 |
16191263441 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.1999747732 |
|
|
Sep 01 07:34:27 AM UTC 24 |
Sep 01 07:37:38 AM UTC 24 |
2648719124 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.2530648997 |
|
|
Sep 01 07:33:40 AM UTC 24 |
Sep 01 07:37:41 AM UTC 24 |
24933575597 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.1383779392 |
|
|
Sep 01 07:26:58 AM UTC 24 |
Sep 01 07:37:42 AM UTC 24 |
31032735567 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.2695676832 |
|
|
Sep 01 07:35:45 AM UTC 24 |
Sep 01 07:37:45 AM UTC 24 |
17641548172 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.2804925702 |
|
|
Sep 01 07:36:25 AM UTC 24 |
Sep 01 07:37:48 AM UTC 24 |
8802136877 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.2934024836 |
|
|
Sep 01 07:36:23 AM UTC 24 |
Sep 01 07:38:03 AM UTC 24 |
1744587570 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.2191312304 |
|
|
Sep 01 07:35:47 AM UTC 24 |
Sep 01 07:38:05 AM UTC 24 |
4161825626 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.1647648407 |
|
|
Sep 01 07:33:52 AM UTC 24 |
Sep 01 07:38:29 AM UTC 24 |
4505017095 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.1856778261 |
|
|
Sep 01 07:36:41 AM UTC 24 |
Sep 01 07:38:36 AM UTC 24 |
24216919099 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_host_perf.3632902351 |
|
|
Sep 01 07:35:47 AM UTC 24 |
Sep 01 07:39:02 AM UTC 24 |
24736767959 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.4229990875 |
|
|
Sep 01 07:34:58 AM UTC 24 |
Sep 01 07:39:09 AM UTC 24 |
16958862312 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.1493755140 |
|
|
Sep 01 07:36:30 AM UTC 24 |
Sep 01 07:40:41 AM UTC 24 |
18657948003 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.3189626401 |
|
|
Sep 01 07:36:11 AM UTC 24 |
Sep 01 07:40:48 AM UTC 24 |
87862039183 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.4225203107 |
|
|
Sep 01 07:36:23 AM UTC 24 |
Sep 01 07:41:13 AM UTC 24 |
7357222393 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.1019128768 |
|
|
Sep 01 07:25:35 AM UTC 24 |
Sep 01 07:41:37 AM UTC 24 |
44958458471 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.3664069344 |
|
|
Sep 01 07:24:55 AM UTC 24 |
Sep 01 07:41:41 AM UTC 24 |
60869586619 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.3467819273 |
|
|
Sep 01 07:32:19 AM UTC 24 |
Sep 01 07:42:45 AM UTC 24 |
40079274718 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.566607318 |
|
|
Sep 01 07:34:16 AM UTC 24 |
Sep 01 07:44:20 AM UTC 24 |
42047408808 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/38.i2c_host_stress_all.2215186302 |
|
|
Sep 01 07:28:51 AM UTC 24 |
Sep 01 07:44:39 AM UTC 24 |
150809054785 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.1078257087 |
|
|
Sep 01 07:35:55 AM UTC 24 |
Sep 01 07:45:08 AM UTC 24 |
43948453737 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.1668463104 |
|
|
Sep 01 07:25:56 AM UTC 24 |
Sep 01 07:45:51 AM UTC 24 |
54537514052 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/13.i2c_host_stress_all.1871260452 |
|
|
Sep 01 07:15:40 AM UTC 24 |
Sep 01 07:47:21 AM UTC 24 |
55570715923 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.1410390324 |
|
|
Sep 01 07:22:51 AM UTC 24 |
Sep 01 07:49:32 AM UTC 24 |
149729196603 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/46.i2c_host_stress_all.750106136 |
|
|
Sep 01 07:34:34 AM UTC 24 |
Sep 01 07:51:29 AM UTC 24 |
137148924135 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/18.i2c_host_perf.1033707166 |
|
|
Sep 01 07:17:44 AM UTC 24 |
Sep 01 07:52:28 AM UTC 24 |
49040696864 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/default/13.i2c_target_stress_wr.2620281965 |
|
|
Sep 01 07:15:42 AM UTC 24 |
Sep 01 07:52:48 AM UTC 24 |
70284884738 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.973870582 |
|
|
Sep 01 07:36:58 AM UTC 24 |
Sep 01 07:37:00 AM UTC 24 |
221002164 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.3386023351 |
|
|
Sep 01 07:36:58 AM UTC 24 |
Sep 01 07:37:00 AM UTC 24 |
23487991 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.3803224561 |
|
|
Sep 01 07:36:58 AM UTC 24 |
Sep 01 07:37:00 AM UTC 24 |
19310915 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.4235611006 |
|
|
Sep 01 07:36:57 AM UTC 24 |
Sep 01 07:37:00 AM UTC 24 |
132540648 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.3204190708 |
|
|
Sep 01 07:36:57 AM UTC 24 |
Sep 01 07:37:01 AM UTC 24 |
96180147 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.1766819916 |
|
|
Sep 01 07:36:59 AM UTC 24 |
Sep 01 07:37:02 AM UTC 24 |
105159393 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.1814815880 |
|
|
Sep 01 07:37:01 AM UTC 24 |
Sep 01 07:37:03 AM UTC 24 |
17008065 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.2745409809 |
|
|
Sep 01 07:36:59 AM UTC 24 |
Sep 01 07:37:03 AM UTC 24 |
87963287 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.107245420 |
|
|
Sep 01 07:37:01 AM UTC 24 |
Sep 01 07:37:03 AM UTC 24 |
36668759 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.3117167568 |
|
|
Sep 01 07:37:01 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
71466326 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.3168005691 |
|
|
Sep 01 07:37:01 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
79176520 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.3426991615 |
|
|
Sep 01 07:37:02 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
20140530 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.1802424356 |
|
|
Sep 01 07:37:02 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
67207034 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.1401982234 |
|
|
Sep 01 07:36:59 AM UTC 24 |
Sep 01 07:37:04 AM UTC 24 |
181578926 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2147284408 |
|
|
Sep 01 07:37:03 AM UTC 24 |
Sep 01 07:37:06 AM UTC 24 |
86765488 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2950412814 |
|
|
Sep 01 07:37:03 AM UTC 24 |
Sep 01 07:37:06 AM UTC 24 |
152975615 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.970878722 |
|
|
Sep 01 07:37:02 AM UTC 24 |
Sep 01 07:37:06 AM UTC 24 |
108096578 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2744218462 |
|
|
Sep 01 07:37:03 AM UTC 24 |
Sep 01 07:37:07 AM UTC 24 |
69743113 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.4130223158 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:07 AM UTC 24 |
16991581 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1555297151 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:07 AM UTC 24 |
20807056 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.247228863 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:07 AM UTC 24 |
19007333 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.939646156 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:07 AM UTC 24 |
90708563 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.494535385 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:08 AM UTC 24 |
98941388 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.4231174451 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:09 AM UTC 24 |
202441441 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.4143542578 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:09 AM UTC 24 |
118988018 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3090101089 |
|
|
Sep 01 07:37:06 AM UTC 24 |
Sep 01 07:37:09 AM UTC 24 |
139067505 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.1371953985 |
|
|
Sep 01 07:37:02 AM UTC 24 |
Sep 01 07:37:09 AM UTC 24 |
647051288 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/10.i2c_intr_test.2524905905 |
|
|
Sep 01 07:37:20 AM UTC 24 |
Sep 01 07:37:22 AM UTC 24 |
29542361 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.2025309837 |
|
|
Sep 01 07:37:08 AM UTC 24 |
Sep 01 07:37:09 AM UTC 24 |
31244574 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.2256307193 |
|
|
Sep 01 07:37:05 AM UTC 24 |
Sep 01 07:37:10 AM UTC 24 |
377122707 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.145937680 |
|
|
Sep 01 07:37:08 AM UTC 24 |
Sep 01 07:37:10 AM UTC 24 |
40872296 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.2111780583 |
|
|
Sep 01 07:37:08 AM UTC 24 |
Sep 01 07:37:10 AM UTC 24 |
55689940 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.1112170601 |
|
|
Sep 01 07:37:08 AM UTC 24 |
Sep 01 07:37:11 AM UTC 24 |
59106417 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.3720758179 |
|
|
Sep 01 07:37:06 AM UTC 24 |
Sep 01 07:37:11 AM UTC 24 |
180974110 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1804817582 |
|
|
Sep 01 07:37:09 AM UTC 24 |
Sep 01 07:37:11 AM UTC 24 |
30520971 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.997875280 |
|
|
Sep 01 07:37:09 AM UTC 24 |
Sep 01 07:37:12 AM UTC 24 |
78987682 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.3674199334 |
|
|
Sep 01 07:37:09 AM UTC 24 |
Sep 01 07:37:12 AM UTC 24 |
446679407 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.1437202060 |
|
|
Sep 01 07:37:11 AM UTC 24 |
Sep 01 07:37:13 AM UTC 24 |
20000341 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.606533409 |
|
|
Sep 01 07:37:10 AM UTC 24 |
Sep 01 07:37:13 AM UTC 24 |
21298178 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.358855079 |
|
|
Sep 01 07:37:08 AM UTC 24 |
Sep 01 07:37:13 AM UTC 24 |
2927835983 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.1112263016 |
|
|
Sep 01 07:37:09 AM UTC 24 |
Sep 01 07:37:13 AM UTC 24 |
123011561 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3261511672 |
|
|
Sep 01 07:37:11 AM UTC 24 |
Sep 01 07:37:13 AM UTC 24 |
207881440 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/9.i2c_tl_errors.3385828586 |
|
|
Sep 01 07:37:18 AM UTC 24 |
Sep 01 07:37:22 AM UTC 24 |
53369535 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.626814107 |
|
|
Sep 01 07:37:09 AM UTC 24 |
Sep 01 07:37:14 AM UTC 24 |
146887833 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.2377670397 |
|
|
Sep 01 07:37:12 AM UTC 24 |
Sep 01 07:37:14 AM UTC 24 |
211373808 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.1382554660 |
|
|
Sep 01 07:37:12 AM UTC 24 |
Sep 01 07:37:14 AM UTC 24 |
39509024 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.1733642409 |
|
|
Sep 01 07:37:11 AM UTC 24 |
Sep 01 07:37:14 AM UTC 24 |
77812512 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.982911061 |
|
|
Sep 01 07:37:11 AM UTC 24 |
Sep 01 07:37:15 AM UTC 24 |
137314206 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3351813214 |
|
|
Sep 01 07:37:14 AM UTC 24 |
Sep 01 07:37:16 AM UTC 24 |
67202223 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.1264063680 |
|
|
Sep 01 07:37:14 AM UTC 24 |
Sep 01 07:37:16 AM UTC 24 |
20723674 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.1537441732 |
|
|
Sep 01 07:37:12 AM UTC 24 |
Sep 01 07:37:16 AM UTC 24 |
185686613 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.3197418594 |
|
|
Sep 01 07:37:13 AM UTC 24 |
Sep 01 07:37:16 AM UTC 24 |
167477706 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.4156772778 |
|
|
Sep 01 07:37:14 AM UTC 24 |
Sep 01 07:37:16 AM UTC 24 |
35224458 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.3348896108 |
|
|
Sep 01 07:37:14 AM UTC 24 |
Sep 01 07:37:17 AM UTC 24 |
262786631 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.2229020137 |
|
|
Sep 01 07:37:15 AM UTC 24 |
Sep 01 07:37:17 AM UTC 24 |
267744344 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.4071207828 |
|
|
Sep 01 07:37:15 AM UTC 24 |
Sep 01 07:37:17 AM UTC 24 |
22815039 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.478976780 |
|
|
Sep 01 07:37:15 AM UTC 24 |
Sep 01 07:37:17 AM UTC 24 |
60967355 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1603190641 |
|
|
Sep 01 07:37:15 AM UTC 24 |
Sep 01 07:37:18 AM UTC 24 |
269776834 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.3148161224 |
|
|
Sep 01 07:37:14 AM UTC 24 |
Sep 01 07:37:18 AM UTC 24 |
575260074 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_08_31/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.4212133001 |
|
|
Sep 01 07:37:11 AM UTC 24 |
Sep 01 07:37:18 AM UTC 24 |
1866292086 ps |