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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
91.09 97.15 89.39 97.22 71.43 94.11 98.44 89.89


Total test records in report: 1848
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html

T1085 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_timeout.2221765197 Sep 09 10:35:32 AM UTC 24 Sep 09 10:35:45 AM UTC 24 1591391595 ps
T1086 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_stress_rd.1786994992 Sep 09 10:35:25 AM UTC 24 Sep 09 10:35:46 AM UTC 24 3811198320 ps
T1087 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_target_bad_addr.830235051 Sep 09 10:41:07 AM UTC 24 Sep 09 10:41:15 AM UTC 24 1191003310 ps
T1088 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_full.4202165685 Sep 09 10:34:42 AM UTC 24 Sep 09 10:35:47 AM UTC 24 2198660147 ps
T1089 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_acq.3432060891 Sep 09 10:35:41 AM UTC 24 Sep 09 10:35:47 AM UTC 24 490233689 ps
T1090 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_fifo_watermarks_tx.3927910570 Sep 09 10:35:43 AM UTC 24 Sep 09 10:35:47 AM UTC 24 672376425 ps
T1091 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_bad_addr.3555101274 Sep 09 10:35:38 AM UTC 24 Sep 09 10:35:48 AM UTC 24 977960939 ps
T1092 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_may_nack.3739026914 Sep 09 10:35:39 AM UTC 24 Sep 09 10:35:49 AM UTC 24 219701204 ps
T1093 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_alert_test.1127744115 Sep 09 10:35:48 AM UTC 24 Sep 09 10:35:50 AM UTC 24 42740198 ps
T1094 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_smbus_maxlen.2589336315 Sep 09 10:35:45 AM UTC 24 Sep 09 10:35:50 AM UTC 24 3135492482 ps
T1095 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_override.562253832 Sep 09 10:35:48 AM UTC 24 Sep 09 10:35:50 AM UTC 24 122201102 ps
T1096 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_nack_txstretch.2111953830 Sep 09 10:35:47 AM UTC 24 Sep 09 10:35:50 AM UTC 24 155686404 ps
T1097 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull.3866860891 Sep 09 10:35:45 AM UTC 24 Sep 09 10:35:51 AM UTC 24 548891541 ps
T1098 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_nack_acqfull_addr.703092218 Sep 09 10:35:47 AM UTC 24 Sep 09 10:35:52 AM UTC 24 855544677 ps
T1099 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_fmt.2505089503 Sep 09 10:35:50 AM UTC 24 Sep 09 10:35:53 AM UTC 24 414709223 ps
T1100 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_stretch_timeout.3160289284 Sep 09 10:35:19 AM UTC 24 Sep 09 10:35:56 AM UTC 24 2613370791 ps
T1101 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_tx_stretch_ctrl.232661525 Sep 09 10:35:44 AM UTC 24 Sep 09 10:35:58 AM UTC 24 515378988 ps
T1102 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_reset_rx.412209074 Sep 09 10:35:51 AM UTC 24 Sep 09 10:36:02 AM UTC 24 463169772 ps
T1103 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_perf_precise.1923041533 Sep 09 10:35:52 AM UTC 24 Sep 09 10:36:02 AM UTC 24 1795902775 ps
T1104 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_fmt_empty.1691619881 Sep 09 10:35:51 AM UTC 24 Sep 09 10:36:02 AM UTC 24 1366217147 ps
T1105 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_host_perf.792995732 Sep 09 10:34:42 AM UTC 24 Sep 09 10:36:02 AM UTC 24 5624471904 ps
T1106 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/26.i2c_host_perf.910567242 Sep 09 10:33:05 AM UTC 24 Sep 09 10:36:04 AM UTC 24 27007748698 ps
T1107 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_stretch_timeout.3053675040 Sep 09 10:35:52 AM UTC 24 Sep 09 10:36:06 AM UTC 24 4891421712 ps
T1108 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_perf.1817366381 Sep 09 10:35:51 AM UTC 24 Sep 09 10:36:08 AM UTC 24 3559958488 ps
T1109 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/27.i2c_target_intr_stress_wr.447088524 Sep 09 10:33:48 AM UTC 24 Sep 09 10:36:09 AM UTC 24 15409402231 ps
T1110 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_stretch.3543769995 Sep 09 10:36:03 AM UTC 24 Sep 09 10:36:11 AM UTC 24 653203117 ps
T1111 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_stress_rd.1030138759 Sep 09 10:36:03 AM UTC 24 Sep 09 10:36:12 AM UTC 24 1230886839 ps
T1112 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_reset_acq.887389651 Sep 09 10:36:09 AM UTC 24 Sep 09 10:36:12 AM UTC 24 289997153 ps
T1113 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_intr_stress_wr.1045573585 Sep 09 10:36:04 AM UTC 24 Sep 09 10:36:12 AM UTC 24 2888524538 ps
T1114 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_error_intr.874979525 Sep 09 10:35:54 AM UTC 24 Sep 09 10:36:13 AM UTC 24 2041759316 ps
T1115 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_timeout.1736730785 Sep 09 10:36:07 AM UTC 24 Sep 09 10:36:16 AM UTC 24 6948083045 ps
T1116 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_tx.467217104 Sep 09 10:36:17 AM UTC 24 Sep 09 10:36:20 AM UTC 24 284596844 ps
T1117 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_bad_addr.4213076843 Sep 09 10:36:13 AM UTC 24 Sep 09 10:36:20 AM UTC 24 5545382459 ps
T1118 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_fifo_watermarks_acq.20473771 Sep 09 10:36:17 AM UTC 24 Sep 09 10:36:21 AM UTC 24 3845432638 ps
T1119 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_perf.3931400723 Sep 09 10:36:11 AM UTC 24 Sep 09 10:36:21 AM UTC 24 3164708690 ps
T1120 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_tx_stretch_ctrl.1693763288 Sep 09 10:36:18 AM UTC 24 Sep 09 10:36:21 AM UTC 24 58456089 ps
T1121 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_smoke.3909715153 Sep 09 10:35:48 AM UTC 24 Sep 09 10:36:22 AM UTC 24 7599619589 ps
T1122 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_may_nack.2866841508 Sep 09 10:36:15 AM UTC 24 Sep 09 10:36:23 AM UTC 24 454348357 ps
T1123 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_smbus_maxlen.95538218 Sep 09 10:36:19 AM UTC 24 Sep 09 10:36:24 AM UTC 24 514844170 ps
T1124 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_alert_test.1851111903 Sep 09 10:36:22 AM UTC 24 Sep 09 10:36:24 AM UTC 24 38855531 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_override.2774939495 Sep 09 10:36:23 AM UTC 24 Sep 09 10:36:25 AM UTC 24 20532339 ps
T1125 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull.1969995661 Sep 09 10:36:20 AM UTC 24 Sep 09 10:36:26 AM UTC 24 519589843 ps
T1126 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_nack_txstretch.823877449 Sep 09 10:36:22 AM UTC 24 Sep 09 10:36:26 AM UTC 24 122922208 ps
T1127 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_nack_acqfull_addr.908784502 Sep 09 10:36:21 AM UTC 24 Sep 09 10:36:27 AM UTC 24 7726803914 ps
T1128 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_fmt.1842188618 Sep 09 10:36:25 AM UTC 24 Sep 09 10:36:28 AM UTC 24 268529651 ps
T1129 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/23.i2c_target_stress_all.1497626982 Sep 09 10:31:37 AM UTC 24 Sep 09 10:39:19 AM UTC 24 62046990246 ps
T1130 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_intr_stress_wr.3626695522 Sep 09 10:35:32 AM UTC 24 Sep 09 10:36:30 AM UTC 24 24266752096 ps
T1131 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_watermark.1755130309 Sep 09 10:35:16 AM UTC 24 Sep 09 10:36:32 AM UTC 24 7362276217 ps
T1132 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_full.3338639488 Sep 09 10:35:18 AM UTC 24 Sep 09 10:36:34 AM UTC 24 10202044057 ps
T1133 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_error_intr.3572661339 Sep 09 10:36:30 AM UTC 24 Sep 09 10:36:34 AM UTC 24 400247494 ps
T1134 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_overflow.2790913194 Sep 09 10:34:41 AM UTC 24 Sep 09 10:36:35 AM UTC 24 1872293126 ps
T1135 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_reset_rx.636715040 Sep 09 10:36:27 AM UTC 24 Sep 09 10:36:36 AM UTC 24 826774431 ps
T1136 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_fmt_empty.3743048989 Sep 09 10:36:26 AM UTC 24 Sep 09 10:36:40 AM UTC 24 750106623 ps
T1137 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_perf_precise.3541031594 Sep 09 10:36:28 AM UTC 24 Sep 09 10:36:40 AM UTC 24 189374274 ps
T1138 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_stretch.2552602654 Sep 09 10:36:37 AM UTC 24 Sep 09 10:36:43 AM UTC 24 1990747459 ps
T1139 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_stress_rd.315770351 Sep 09 10:36:37 AM UTC 24 Sep 09 10:36:43 AM UTC 24 276587113 ps
T1140 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_stretch_timeout.2430838159 Sep 09 10:36:30 AM UTC 24 Sep 09 10:36:46 AM UTC 24 4631474613 ps
T1141 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_stress_all.2421040555 Sep 09 10:35:37 AM UTC 24 Sep 09 10:41:14 AM UTC 24 21505951814 ps
T1142 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_smoke.1984545289 Sep 09 10:35:15 AM UTC 24 Sep 09 10:36:47 AM UTC 24 1576880224 ps
T1143 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_host_fifo_overflow.2371367110 Sep 09 10:35:16 AM UTC 24 Sep 09 10:36:47 AM UTC 24 6271700611 ps
T1144 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_smoke.2190863569 Sep 09 10:36:35 AM UTC 24 Sep 09 10:36:49 AM UTC 24 3131160125 ps
T1145 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_tx.2552158446 Sep 09 10:36:47 AM UTC 24 Sep 09 10:36:49 AM UTC 24 413416572 ps
T1146 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_reset_acq.2609581133 Sep 09 10:36:46 AM UTC 24 Sep 09 10:36:50 AM UTC 24 734656835 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_intr_stress_wr.3045082455 Sep 09 10:36:41 AM UTC 24 Sep 09 10:36:52 AM UTC 24 19384032152 ps
T1147 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_intr_smoke.2177569697 Sep 09 10:36:41 AM UTC 24 Sep 09 10:36:53 AM UTC 24 1213759527 ps
T1148 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_perf.2540214102 Sep 09 10:36:47 AM UTC 24 Sep 09 10:36:54 AM UTC 24 1285696704 ps
T1149 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/30.i2c_target_stretch.1531071955 Sep 09 10:35:27 AM UTC 24 Sep 09 10:36:54 AM UTC 24 2998577265 ps
T1150 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_hrst.2349690781 Sep 09 10:36:51 AM UTC 24 Sep 09 10:36:55 AM UTC 24 301866924 ps
T1151 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_full.4157559475 Sep 09 10:35:51 AM UTC 24 Sep 09 10:36:55 AM UTC 24 4157523275 ps
T1152 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_timeout.507082988 Sep 09 10:36:44 AM UTC 24 Sep 09 10:36:55 AM UTC 24 1249067303 ps
T1153 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_mode_toggle.2442261720 Sep 09 10:36:51 AM UTC 24 Sep 09 10:36:56 AM UTC 24 172691435 ps
T1154 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_tx.4235305636 Sep 09 10:36:55 AM UTC 24 Sep 09 10:36:58 AM UTC 24 604939375 ps
T1155 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_bad_addr.2540265564 Sep 09 10:36:49 AM UTC 24 Sep 09 10:36:58 AM UTC 24 2441975699 ps
T1156 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_fifo_watermarks_acq.440014777 Sep 09 10:36:54 AM UTC 24 Sep 09 10:36:58 AM UTC 24 3087259673 ps
T1157 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_nack_txstretch.181820180 Sep 09 10:36:56 AM UTC 24 Sep 09 10:36:59 AM UTC 24 562556945 ps
T1158 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_tx_stretch_ctrl.1954977101 Sep 09 10:36:55 AM UTC 24 Sep 09 10:37:00 AM UTC 24 293398102 ps
T1159 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_smbus_maxlen.2722965951 Sep 09 10:36:56 AM UTC 24 Sep 09 10:37:01 AM UTC 24 2385909121 ps
T1160 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_alert_test.2609726947 Sep 09 10:36:58 AM UTC 24 Sep 09 10:37:01 AM UTC 24 41045836 ps
T1161 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull_addr.144676944 Sep 09 10:36:56 AM UTC 24 Sep 09 10:37:01 AM UTC 24 1041768012 ps
T1162 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_nack_acqfull.4165896037 Sep 09 10:36:56 AM UTC 24 Sep 09 10:37:01 AM UTC 24 2187471130 ps
T1163 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_override.7590624 Sep 09 10:36:59 AM UTC 24 Sep 09 10:37:02 AM UTC 24 17520468 ps
T1164 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_stress_all.4180144046 Sep 09 10:36:13 AM UTC 24 Sep 09 10:37:03 AM UTC 24 36099385457 ps
T1165 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_fmt.306417372 Sep 09 10:37:02 AM UTC 24 Sep 09 10:37:04 AM UTC 24 257211881 ps
T1166 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_smoke.434373196 Sep 09 10:36:23 AM UTC 24 Sep 09 10:37:05 AM UTC 24 6345851120 ps
T1167 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_perf_precise.1269339026 Sep 09 10:37:04 AM UTC 24 Sep 09 10:37:07 AM UTC 24 313834831 ps
T1168 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_overflow.2266109182 Sep 09 10:35:49 AM UTC 24 Sep 09 10:37:07 AM UTC 24 2462191253 ps
T1169 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_reset_rx.351541342 Sep 09 10:37:02 AM UTC 24 Sep 09 10:37:08 AM UTC 24 1069468060 ps
T1170 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_error_intr.1224462068 Sep 09 10:37:05 AM UTC 24 Sep 09 10:37:09 AM UTC 24 354207586 ps
T1171 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_full.655481621 Sep 09 10:36:27 AM UTC 24 Sep 09 10:37:10 AM UTC 24 18951208089 ps
T1172 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_stretch.2108578489 Sep 09 10:37:11 AM UTC 24 Sep 09 10:37:13 AM UTC 24 429057934 ps
T1173 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_may_nack.2192378798 Sep 09 10:36:53 AM UTC 24 Sep 09 10:37:14 AM UTC 24 1569526739 ps
T1174 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/27.i2c_host_fifo_watermark.1464678134 Sep 09 10:33:38 AM UTC 24 Sep 09 10:37:16 AM UTC 24 16721887987 ps
T1175 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_fmt_empty.853511257 Sep 09 10:37:02 AM UTC 24 Sep 09 10:37:18 AM UTC 24 2854427409 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_intr_smoke.1073829515 Sep 09 10:37:13 AM UTC 24 Sep 09 10:37:23 AM UTC 24 3625896865 ps
T1176 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/24.i2c_target_stress_all.3452903030 Sep 09 10:32:13 AM UTC 24 Sep 09 10:37:23 AM UTC 24 27452785836 ps
T1177 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_acq.2105596943 Sep 09 10:37:19 AM UTC 24 Sep 09 10:37:23 AM UTC 24 329820610 ps
T1178 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_reset_tx.2250283897 Sep 09 10:37:21 AM UTC 24 Sep 09 10:37:24 AM UTC 24 161081327 ps
T1179 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_timeout.1014849290 Sep 09 10:37:15 AM UTC 24 Sep 09 10:37:28 AM UTC 24 1268395527 ps
T1180 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_smoke.3677217229 Sep 09 10:36:58 AM UTC 24 Sep 09 10:37:28 AM UTC 24 1850659058 ps
T1181 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_bad_addr.1923561623 Sep 09 10:37:24 AM UTC 24 Sep 09 10:37:31 AM UTC 24 2530253399 ps
T1182 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_mode_toggle.3099255974 Sep 09 10:37:28 AM UTC 24 Sep 09 10:37:32 AM UTC 24 473687333 ps
T1183 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_stress_wr.2924567772 Sep 09 10:37:09 AM UTC 24 Sep 09 10:37:33 AM UTC 24 50163669302 ps
T1184 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_may_nack.515485042 Sep 09 10:37:28 AM UTC 24 Sep 09 10:37:35 AM UTC 24 627400461 ps
T1185 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_host_fifo_watermark.214700259 Sep 09 10:34:41 AM UTC 24 Sep 09 10:37:35 AM UTC 24 3245439320 ps
T1186 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_tx.2875079827 Sep 09 10:37:34 AM UTC 24 Sep 09 10:37:37 AM UTC 24 343715024 ps
T1187 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_perf.3492594687 Sep 09 10:37:24 AM UTC 24 Sep 09 10:37:37 AM UTC 24 1920098098 ps
T1188 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_fifo_watermarks_acq.421996127 Sep 09 10:37:32 AM UTC 24 Sep 09 10:37:37 AM UTC 24 964807757 ps
T1189 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_smoke.750057617 Sep 09 10:37:08 AM UTC 24 Sep 09 10:37:38 AM UTC 24 913781248 ps
T1190 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_tx_stretch_ctrl.2818654285 Sep 09 10:37:34 AM UTC 24 Sep 09 10:37:38 AM UTC 24 88754025 ps
T1191 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_stretch_timeout.77605875 Sep 09 10:37:05 AM UTC 24 Sep 09 10:37:38 AM UTC 24 5583151466 ps
T1192 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_alert_test.3680997842 Sep 09 10:37:38 AM UTC 24 Sep 09 10:37:40 AM UTC 24 15679416 ps
T1193 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_smbus_maxlen.2898486938 Sep 09 10:37:36 AM UTC 24 Sep 09 10:37:40 AM UTC 24 638974644 ps
T1194 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_nack_txstretch.1594644776 Sep 09 10:37:38 AM UTC 24 Sep 09 10:37:41 AM UTC 24 129521528 ps
T1195 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_override.1460616138 Sep 09 10:37:39 AM UTC 24 Sep 09 10:37:41 AM UTC 24 36987651 ps
T1196 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull.3825584544 Sep 09 10:37:36 AM UTC 24 Sep 09 10:37:42 AM UTC 24 3650204619 ps
T1197 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_nack_acqfull_addr.2487491703 Sep 09 10:37:38 AM UTC 24 Sep 09 10:37:42 AM UTC 24 1987944949 ps
T1198 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_fmt.1361469571 Sep 09 10:37:41 AM UTC 24 Sep 09 10:37:44 AM UTC 24 123432849 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/27.i2c_host_stress_all.33161887 Sep 09 10:33:43 AM UTC 24 Sep 09 10:37:46 AM UTC 24 27951847525 ps
T1199 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_perf_precise.1460559276 Sep 09 10:37:45 AM UTC 24 Sep 09 10:37:47 AM UTC 24 100944118 ps
T1200 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_reset_rx.2349526135 Sep 09 10:37:43 AM UTC 24 Sep 09 10:37:50 AM UTC 24 256339460 ps
T1201 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_error_intr.2134010512 Sep 09 10:37:48 AM UTC 24 Sep 09 10:37:54 AM UTC 24 492315216 ps
T1202 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_fmt_empty.1637973115 Sep 09 10:37:42 AM UTC 24 Sep 09 10:37:58 AM UTC 24 3369459030 ps
T1203 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_fifo_watermark.4068089303 Sep 09 10:35:48 AM UTC 24 Sep 09 10:37:59 AM UTC 24 5429597762 ps
T1204 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_overflow.2962003344 Sep 09 10:36:25 AM UTC 24 Sep 09 10:38:06 AM UTC 24 2918235691 ps
T1205 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_perf.3406961503 Sep 09 10:37:03 AM UTC 24 Sep 09 10:38:09 AM UTC 24 3143868453 ps
T1206 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_smoke.3646469318 Sep 09 10:37:54 AM UTC 24 Sep 09 10:38:13 AM UTC 24 1106006682 ps
T1207 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_stretch.3329238788 Sep 09 10:38:04 AM UTC 24 Sep 09 10:38:15 AM UTC 24 3945357395 ps
T1208 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_stretch_timeout.2116483732 Sep 09 10:37:47 AM UTC 24 Sep 09 10:38:15 AM UTC 24 2252309238 ps
T1209 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/9.i2c_target_stress_wr.851798834 Sep 09 10:24:13 AM UTC 24 Sep 09 10:38:16 AM UTC 24 75428096627 ps
T1210 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_intr_smoke.44781810 Sep 09 10:38:06 AM UTC 24 Sep 09 10:38:16 AM UTC 24 2167172560 ps
T1211 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_intr_stress_wr.333540498 Sep 09 10:37:15 AM UTC 24 Sep 09 10:38:17 AM UTC 24 21128162108 ps
T1212 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_stress_all.131785116 Sep 09 10:36:47 AM UTC 24 Sep 09 10:38:18 AM UTC 24 8377490379 ps
T1213 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_acq.1176383816 Sep 09 10:38:17 AM UTC 24 Sep 09 10:38:19 AM UTC 24 177154045 ps
T1214 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_reset_tx.2952089377 Sep 09 10:38:17 AM UTC 24 Sep 09 10:38:19 AM UTC 24 246539303 ps
T1215 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_error_intr.1931189372 Sep 09 10:39:10 AM UTC 24 Sep 09 10:39:16 AM UTC 24 515932605 ps
T1216 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_overflow.3282896830 Sep 09 10:37:40 AM UTC 24 Sep 09 10:38:20 AM UTC 24 2845859288 ps
T1217 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_smoke.2287567631 Sep 09 10:38:28 AM UTC 24 Sep 09 10:39:11 AM UTC 24 1772004726 ps
T1218 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_hrst.3370226350 Sep 09 10:38:18 AM UTC 24 Sep 09 10:38:23 AM UTC 24 2233781768 ps
T1219 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_tx.3994246065 Sep 09 10:38:21 AM UTC 24 Sep 09 10:38:24 AM UTC 24 144093810 ps
T1220 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_fifo_watermarks_acq.3972952581 Sep 09 10:38:20 AM UTC 24 Sep 09 10:38:26 AM UTC 24 1072144083 ps
T1221 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_bad_addr.3320733231 Sep 09 10:38:18 AM UTC 24 Sep 09 10:38:27 AM UTC 24 1750247549 ps
T1222 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_timeout.3252510242 Sep 09 10:38:14 AM UTC 24 Sep 09 10:38:27 AM UTC 24 1291121977 ps
T1223 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_target_stress_rd.2194044825 Sep 09 10:37:09 AM UTC 24 Sep 09 10:38:27 AM UTC 24 1616040294 ps
T1224 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_perf.3331133810 Sep 09 10:38:17 AM UTC 24 Sep 09 10:38:28 AM UTC 24 2751610167 ps
T1225 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_fifo_watermark.952625627 Sep 09 10:36:24 AM UTC 24 Sep 09 10:38:28 AM UTC 24 5195850655 ps
T1226 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull.2353768239 Sep 09 10:38:24 AM UTC 24 Sep 09 10:38:28 AM UTC 24 545263876 ps
T1227 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_smbus_maxlen.3602422943 Sep 09 10:38:24 AM UTC 24 Sep 09 10:38:29 AM UTC 24 409999974 ps
T1228 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_tx_stretch_ctrl.3954887050 Sep 09 10:38:22 AM UTC 24 Sep 09 10:38:29 AM UTC 24 354963686 ps
T1229 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_intr_stress_wr.3839500011 Sep 09 10:38:10 AM UTC 24 Sep 09 10:38:29 AM UTC 24 24114025251 ps
T1230 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_nack_acqfull_addr.1529626162 Sep 09 10:38:25 AM UTC 24 Sep 09 10:38:30 AM UTC 24 2124711216 ps
T1231 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_full.3101415309 Sep 09 10:37:03 AM UTC 24 Sep 09 10:38:30 AM UTC 24 12031164919 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_override.3357221274 Sep 09 10:38:28 AM UTC 24 Sep 09 10:38:30 AM UTC 24 387535105 ps
T1232 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_alert_test.1662400349 Sep 09 10:38:28 AM UTC 24 Sep 09 10:38:30 AM UTC 24 26399212 ps
T1233 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_nack_txstretch.1672516422 Sep 09 10:38:27 AM UTC 24 Sep 09 10:38:31 AM UTC 24 555580730 ps
T1234 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_may_nack.2699429619 Sep 09 10:38:20 AM UTC 24 Sep 09 10:38:31 AM UTC 24 5231398066 ps
T1235 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_may_nack.3073017790 Sep 09 10:38:51 AM UTC 24 Sep 09 10:39:12 AM UTC 24 2442445058 ps
T1236 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_fmt.1823616166 Sep 09 10:38:29 AM UTC 24 Sep 09 10:38:32 AM UTC 24 442628297 ps
T1237 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_reset_rx.1730761673 Sep 09 10:38:29 AM UTC 24 Sep 09 10:38:34 AM UTC 24 145861215 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/25.i2c_host_stress_all.733828560 Sep 09 10:32:36 AM UTC 24 Sep 09 10:38:36 AM UTC 24 15146599334 ps
T1238 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_fmt_empty.841272683 Sep 09 10:38:29 AM UTC 24 Sep 09 10:38:38 AM UTC 24 1078169867 ps
T1239 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/27.i2c_target_stress_wr.362583808 Sep 09 10:33:44 AM UTC 24 Sep 09 10:38:42 AM UTC 24 49454210701 ps
T1240 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_stress_rd.3553305629 Sep 09 10:38:35 AM UTC 24 Sep 09 10:38:42 AM UTC 24 371356891 ps
T1241 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_overflow.1585404423 Sep 09 10:37:01 AM UTC 24 Sep 09 10:38:45 AM UTC 24 1755557767 ps
T1242 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_perf_precise.96088070 Sep 09 10:38:31 AM UTC 24 Sep 09 10:38:46 AM UTC 24 255769489 ps
T1243 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_stress_rd.1179721167 Sep 09 10:37:59 AM UTC 24 Sep 09 10:38:47 AM UTC 24 896349565 ps
T1244 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_error_intr.961038615 Sep 09 10:38:32 AM UTC 24 Sep 09 10:38:48 AM UTC 24 432612938 ps
T1245 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_acq.3432719014 Sep 09 10:38:45 AM UTC 24 Sep 09 10:38:48 AM UTC 24 309095367 ps
T1246 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_smoke.333923822 Sep 09 10:37:39 AM UTC 24 Sep 09 10:38:48 AM UTC 24 5953163323 ps
T1247 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_reset_tx.3936433267 Sep 09 10:38:46 AM UTC 24 Sep 09 10:38:49 AM UTC 24 417194130 ps
T1248 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_intr_smoke.643611545 Sep 09 10:38:38 AM UTC 24 Sep 09 10:38:50 AM UTC 24 3573993805 ps
T1249 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_smoke.3298723259 Sep 09 10:38:32 AM UTC 24 Sep 09 10:38:50 AM UTC 24 1025990220 ps
T1250 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_perf.3277318438 Sep 09 10:38:46 AM UTC 24 Sep 09 10:38:52 AM UTC 24 525672037 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_stretch_timeout.3177653574 Sep 09 10:38:32 AM UTC 24 Sep 09 10:38:52 AM UTC 24 855752568 ps
T1251 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_timeout.2901268676 Sep 09 10:38:43 AM UTC 24 Sep 09 10:38:52 AM UTC 24 6497037244 ps
T1252 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_rx.3698815632 Sep 09 10:39:01 AM UTC 24 Sep 09 10:39:14 AM UTC 24 153353740 ps
T1253 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_tx.3547747462 Sep 09 10:38:51 AM UTC 24 Sep 09 10:38:54 AM UTC 24 158637823 ps
T1254 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_fifo_watermarks_acq.536511275 Sep 09 10:38:51 AM UTC 24 Sep 09 10:38:54 AM UTC 24 750825980 ps
T1255 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_alert_test.917910963 Sep 09 10:38:55 AM UTC 24 Sep 09 10:38:57 AM UTC 24 35995128 ps
T1256 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_perf.4164816639 Sep 09 10:37:43 AM UTC 24 Sep 09 10:38:58 AM UTC 24 7127386986 ps
T1257 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull.489358746 Sep 09 10:38:53 AM UTC 24 Sep 09 10:38:58 AM UTC 24 1167310925 ps
T1258 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_smbus_maxlen.3037176837 Sep 09 10:38:53 AM UTC 24 Sep 09 10:38:58 AM UTC 24 493889774 ps
T1259 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_nack_txstretch.1305303879 Sep 09 10:38:55 AM UTC 24 Sep 09 10:38:59 AM UTC 24 148162049 ps
T1260 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_bad_addr.3017876732 Sep 09 10:38:49 AM UTC 24 Sep 09 10:38:59 AM UTC 24 12668595097 ps
T1261 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_override.52887249 Sep 09 10:38:59 AM UTC 24 Sep 09 10:39:00 AM UTC 24 30952316 ps
T1262 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_nack_acqfull_addr.3943705563 Sep 09 10:38:55 AM UTC 24 Sep 09 10:39:01 AM UTC 24 886295239 ps
T1263 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_tx_stretch_ctrl.733792832 Sep 09 10:38:52 AM UTC 24 Sep 09 10:39:02 AM UTC 24 353775489 ps
T1264 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_reset_fmt.1421319135 Sep 09 10:39:00 AM UTC 24 Sep 09 10:39:03 AM UTC 24 1178178392 ps
T1265 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_perf_precise.324174788 Sep 09 10:39:03 AM UTC 24 Sep 09 10:39:07 AM UTC 24 670471850 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_target_stress_all.2445769098 Sep 09 10:38:18 AM UTC 24 Sep 09 10:39:09 AM UTC 24 17246641545 ps
T1267 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_fmt_empty.1679088955 Sep 09 10:39:00 AM UTC 24 Sep 09 10:39:23 AM UTC 24 827575725 ps
T1268 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_fifo_watermark.1607969397 Sep 09 10:36:59 AM UTC 24 Sep 09 10:39:24 AM UTC 24 59033106325 ps
T1269 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_stretch_timeout.17063048 Sep 09 10:39:08 AM UTC 24 Sep 09 10:39:25 AM UTC 24 710465647 ps
T1270 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_stretch.2203990006 Sep 09 10:38:37 AM UTC 24 Sep 09 10:39:26 AM UTC 24 3777878041 ps
T1271 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_target_intr_smoke.466032475 Sep 09 10:41:00 AM UTC 24 Sep 09 10:41:10 AM UTC 24 1637620173 ps
T1272 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_overflow.4089785262 Sep 09 10:38:29 AM UTC 24 Sep 09 10:39:27 AM UTC 24 3829910974 ps
T1273 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_target_perf.3303857370 Sep 09 10:41:05 AM UTC 24 Sep 09 10:41:12 AM UTC 24 515572521 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/23.i2c_host_stress_all.3532088251 Sep 09 10:31:30 AM UTC 24 Sep 09 10:39:30 AM UTC 24 166133586902 ps
T1274 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_acq.3454030977 Sep 09 10:39:28 AM UTC 24 Sep 09 10:39:31 AM UTC 24 138614121 ps
T1275 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_reset_tx.3851835802 Sep 09 10:39:28 AM UTC 24 Sep 09 10:39:31 AM UTC 24 456449674 ps
T1276 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_intr_smoke.194671149 Sep 09 10:39:24 AM UTC 24 Sep 09 10:39:34 AM UTC 24 1928150486 ps
T1277 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_smoke.3670394909 Sep 09 10:39:13 AM UTC 24 Sep 09 10:39:35 AM UTC 24 3868154865 ps
T1278 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_hrst.3909695375 Sep 09 10:39:32 AM UTC 24 Sep 09 10:39:36 AM UTC 24 1214204884 ps
T1279 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_target_timeout.1956263344 Sep 09 10:41:01 AM UTC 24 Sep 09 10:41:13 AM UTC 24 1393240190 ps
T1280 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_timeout.1550388536 Sep 09 10:39:26 AM UTC 24 Sep 09 10:39:39 AM UTC 24 1100363847 ps
T1281 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_stress_all.3534291389 Sep 09 10:38:48 AM UTC 24 Sep 09 10:39:39 AM UTC 24 20357713016 ps
T1282 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_perf.3683072773 Sep 09 10:39:31 AM UTC 24 Sep 09 10:39:41 AM UTC 24 8672080027 ps
T1283 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_target_intr_stress_wr.2964217699 Sep 09 10:38:39 AM UTC 24 Sep 09 10:39:41 AM UTC 24 21069321410 ps
T1284 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_acq.1559802180 Sep 09 10:39:37 AM UTC 24 Sep 09 10:39:42 AM UTC 24 6841800536 ps
T1285 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_stress_wr.3016590123 Sep 09 10:39:15 AM UTC 24 Sep 09 10:39:42 AM UTC 24 10267046206 ps
T1286 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_smoke.1073677009 Sep 09 10:38:59 AM UTC 24 Sep 09 10:39:42 AM UTC 24 2106245778 ps
T1287 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_fifo_watermarks_tx.4232152485 Sep 09 10:39:39 AM UTC 24 Sep 09 10:39:42 AM UTC 24 126445337 ps
T1288 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_bad_addr.2704607744 Sep 09 10:39:31 AM UTC 24 Sep 09 10:39:43 AM UTC 24 4644409879 ps
T1289 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_may_nack.3421115013 Sep 09 10:39:36 AM UTC 24 Sep 09 10:39:44 AM UTC 24 705823934 ps
T1290 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_smbus_maxlen.2546478158 Sep 09 10:39:40 AM UTC 24 Sep 09 10:39:44 AM UTC 24 412095263 ps
T1291 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_override.2987278409 Sep 09 10:39:42 AM UTC 24 Sep 09 10:39:45 AM UTC 24 30158702 ps
T1292 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_alert_test.3825292726 Sep 09 10:39:42 AM UTC 24 Sep 09 10:39:45 AM UTC 24 19121363 ps
T1293 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull_addr.4117995568 Sep 09 10:39:41 AM UTC 24 Sep 09 10:39:46 AM UTC 24 429456973 ps
T1294 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_nack_txstretch.4178503208 Sep 09 10:39:42 AM UTC 24 Sep 09 10:39:46 AM UTC 24 509641438 ps
T1295 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_nack_acqfull.1171339716 Sep 09 10:39:40 AM UTC 24 Sep 09 10:39:46 AM UTC 24 2457390570 ps
T1296 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_fmt.1352475131 Sep 09 10:39:45 AM UTC 24 Sep 09 10:39:48 AM UTC 24 176423210 ps
T1297 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_tx_stretch_ctrl.2236728642 Sep 09 10:39:40 AM UTC 24 Sep 09 10:39:50 AM UTC 24 412770057 ps
T1298 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_stress_rd.857628324 Sep 09 10:39:18 AM UTC 24 Sep 09 10:39:51 AM UTC 24 8979730667 ps
T1299 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_error_intr.967651615 Sep 09 10:39:48 AM UTC 24 Sep 09 10:39:52 AM UTC 24 200219264 ps
T1300 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_fmt_empty.2442004269 Sep 09 10:39:46 AM UTC 24 Sep 09 10:39:53 AM UTC 24 4067817928 ps
T1301 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_fifo_overflow.3074577626 Sep 09 10:39:00 AM UTC 24 Sep 09 10:39:57 AM UTC 24 2165164559 ps
T1302 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_fifo_reset_rx.3410435412 Sep 09 10:39:46 AM UTC 24 Sep 09 10:39:57 AM UTC 24 183404244 ps
T1303 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_perf_precise.1349894101 Sep 09 10:39:47 AM UTC 24 Sep 09 10:39:58 AM UTC 24 233333712 ps
T1304 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/34.i2c_host_fifo_full.2373341176 Sep 09 10:37:43 AM UTC 24 Sep 09 10:40:04 AM UTC 24 2210880160 ps
T1305 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_intr_smoke.1957377370 Sep 09 10:39:59 AM UTC 24 Sep 09 10:40:05 AM UTC 24 3115595628 ps
T1306 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_smoke.3909556527 Sep 09 10:39:52 AM UTC 24 Sep 09 10:40:10 AM UTC 24 1049769749 ps
T1307 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_target_intr_stress_wr.4202842542 Sep 09 10:34:55 AM UTC 24 Sep 09 10:40:10 AM UTC 24 19978270633 ps
T1308 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_fifo_full.3043732306 Sep 09 10:38:30 AM UTC 24 Sep 09 10:40:12 AM UTC 24 12620278758 ps
T1309 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_acq.193599084 Sep 09 10:40:10 AM UTC 24 Sep 09 10:40:13 AM UTC 24 221536959 ps
T1310 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_reset_tx.1187190225 Sep 09 10:40:11 AM UTC 24 Sep 09 10:40:14 AM UTC 24 402781840 ps
T1311 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_timeout.838718547 Sep 09 10:40:05 AM UTC 24 Sep 09 10:40:16 AM UTC 24 4548348867 ps
T1312 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_perf.3708312178 Sep 09 10:40:11 AM UTC 24 Sep 09 10:40:20 AM UTC 24 3914294303 ps
T1313 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_stretch_timeout.3054271161 Sep 09 10:39:47 AM UTC 24 Sep 09 10:40:22 AM UTC 24 613596769 ps
T1314 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_bad_addr.4034066153 Sep 09 10:40:13 AM UTC 24 Sep 09 10:40:23 AM UTC 24 4780031969 ps
T1315 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_host_perf.688041358 Sep 09 10:39:47 AM UTC 24 Sep 09 10:40:23 AM UTC 24 4980365097 ps
T1316 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_stress_rd.1665359294 Sep 09 10:39:55 AM UTC 24 Sep 09 10:40:24 AM UTC 24 1293107312 ps
T1317 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_tx.3641677429 Sep 09 10:40:24 AM UTC 24 Sep 09 10:40:27 AM UTC 24 362084405 ps
T1318 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_fifo_watermarks_acq.4035266858 Sep 09 10:40:23 AM UTC 24 Sep 09 10:40:29 AM UTC 24 1938193390 ps
T1319 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_smbus_maxlen.2176115159 Sep 09 10:40:25 AM UTC 24 Sep 09 10:40:31 AM UTC 24 453233823 ps
T1320 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull_addr.4222971307 Sep 09 10:40:28 AM UTC 24 Sep 09 10:40:32 AM UTC 24 505621110 ps
T1321 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_nack_acqfull.3561652361 Sep 09 10:40:27 AM UTC 24 Sep 09 10:40:33 AM UTC 24 825940796 ps
T1322 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_target_tx_stretch_ctrl.3877809523 Sep 09 10:40:24 AM UTC 24 Sep 09 10:40:33 AM UTC 24 248222871 ps
T1323 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/37.i2c_alert_test.574102428 Sep 09 10:40:31 AM UTC 24 Sep 09 10:40:33 AM UTC 24 25484829 ps
T1324 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_host_override.2710268459 Sep 09 10:40:33 AM UTC 24 Sep 09 10:40:36 AM UTC 24 43538729 ps
T1325 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/38.i2c_host_fifo_reset_fmt.788612057 Sep 09 10:40:35 AM UTC 24 Sep 09 10:40:37 AM UTC 24 88214519 ps
T1326 /workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_target_stress_all.3103198740 Sep 09 10:39:31 AM UTC 24 Sep 09 10:40:37 AM UTC 24 42969288845 ps
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