| T1571 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_mode_toggle.4145665278 |
|
|
Sep 09 10:45:33 AM UTC 24 |
Sep 09 10:45:37 AM UTC 24 |
2380185193 ps |
| T1572 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_intr_stress_wr.3958447258 |
|
|
Sep 09 10:45:22 AM UTC 24 |
Sep 09 10:45:38 AM UTC 24 |
5906254202 ps |
| T1573 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_bad_addr.2364313417 |
|
|
Sep 09 10:45:32 AM UTC 24 |
Sep 09 10:45:39 AM UTC 24 |
3265530320 ps |
| T1574 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_fifo_watermarks_acq.138207218 |
|
|
Sep 09 10:45:37 AM UTC 24 |
Sep 09 10:45:43 AM UTC 24 |
398088916 ps |
| T1575 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_smbus_maxlen.1428407052 |
|
|
Sep 09 10:45:39 AM UTC 24 |
Sep 09 10:45:44 AM UTC 24 |
1733462613 ps |
| T1576 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull.2189217890 |
|
|
Sep 09 10:45:39 AM UTC 24 |
Sep 09 10:45:44 AM UTC 24 |
540150936 ps |
| T1577 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_txstretch.3669837203 |
|
|
Sep 09 10:45:42 AM UTC 24 |
Sep 09 10:45:44 AM UTC 24 |
164498299 ps |
| T1578 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_alert_test.3129944699 |
|
|
Sep 09 10:45:44 AM UTC 24 |
Sep 09 10:45:46 AM UTC 24 |
18277391 ps |
| T1579 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_nack_acqfull_addr.4072278257 |
|
|
Sep 09 10:45:40 AM UTC 24 |
Sep 09 10:45:46 AM UTC 24 |
1044793593 ps |
| T1580 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_override.715790016 |
|
|
Sep 09 10:45:45 AM UTC 24 |
Sep 09 10:45:47 AM UTC 24 |
181269798 ps |
| T1581 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_smoke.1660266124 |
|
|
Sep 09 10:45:17 AM UTC 24 |
Sep 09 10:45:48 AM UTC 24 |
808577648 ps |
| T1582 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_tx_stretch_ctrl.2050863544 |
|
|
Sep 09 10:45:38 AM UTC 24 |
Sep 09 10:45:49 AM UTC 24 |
446785148 ps |
| T1583 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_fmt.690813062 |
|
|
Sep 09 10:45:47 AM UTC 24 |
Sep 09 10:45:50 AM UTC 24 |
177163622 ps |
| T1584 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/40.i2c_host_fifo_watermark.1832220792 |
|
|
Sep 09 10:41:53 AM UTC 24 |
Sep 09 10:45:51 AM UTC 24 |
4376419356 ps |
| T1585 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_may_nack.1721006412 |
|
|
Sep 09 10:45:35 AM UTC 24 |
Sep 09 10:45:52 AM UTC 24 |
1518462330 ps |
| T1586 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_target_intr_stress_wr.694720023 |
|
|
Sep 09 10:44:44 AM UTC 24 |
Sep 09 10:45:53 AM UTC 24 |
17351386707 ps |
| T1587 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_target_stress_all.2718830781 |
|
|
Sep 09 10:44:55 AM UTC 24 |
Sep 09 10:45:53 AM UTC 24 |
44762298911 ps |
| T1588 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_reset_rx.3720858691 |
|
|
Sep 09 10:45:49 AM UTC 24 |
Sep 09 10:45:56 AM UTC 24 |
150826451 ps |
| T1589 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_error_intr.46346726 |
|
|
Sep 09 10:45:54 AM UTC 24 |
Sep 09 10:45:58 AM UTC 24 |
183192149 ps |
| T1590 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_rd.1202339748 |
|
|
Sep 09 10:45:18 AM UTC 24 |
Sep 09 10:46:00 AM UTC 24 |
1541019880 ps |
| T1591 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_target_stress_wr.1634587443 |
|
|
Sep 09 10:34:49 AM UTC 24 |
Sep 09 10:46:01 AM UTC 24 |
70695344053 ps |
| T1592 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_perf_precise.348472702 |
|
|
Sep 09 10:45:52 AM UTC 24 |
Sep 09 10:46:04 AM UTC 24 |
224025648 ps |
| T1593 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_stretch_timeout.3807547522 |
|
|
Sep 09 10:45:52 AM UTC 24 |
Sep 09 10:46:05 AM UTC 24 |
10385472304 ps |
| T1594 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_rd.1957795121 |
|
|
Sep 09 10:45:59 AM UTC 24 |
Sep 09 10:46:07 AM UTC 24 |
651138224 ps |
| T1595 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_stretch.3513608100 |
|
|
Sep 09 10:46:01 AM UTC 24 |
Sep 09 10:46:11 AM UTC 24 |
2011411699 ps |
| T1596 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_perf.977917575 |
|
|
Sep 09 10:45:51 AM UTC 24 |
Sep 09 10:46:12 AM UTC 24 |
9034817146 ps |
| T1597 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_acq.2290842553 |
|
|
Sep 09 10:46:08 AM UTC 24 |
Sep 09 10:46:12 AM UTC 24 |
234122384 ps |
| T1598 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_intr_smoke.1481745014 |
|
|
Sep 09 10:46:02 AM UTC 24 |
Sep 09 10:46:13 AM UTC 24 |
1863276599 ps |
| T1599 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_smoke.1361536607 |
|
|
Sep 09 10:45:54 AM UTC 24 |
Sep 09 10:46:14 AM UTC 24 |
12708979137 ps |
| T1600 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_reset_tx.4276445225 |
|
|
Sep 09 10:46:12 AM UTC 24 |
Sep 09 10:46:15 AM UTC 24 |
355872773 ps |
| T1601 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_fmt_empty.2990042525 |
|
|
Sep 09 10:45:47 AM UTC 24 |
Sep 09 10:46:15 AM UTC 24 |
406508849 ps |
| T1602 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_overflow.554540648 |
|
|
Sep 09 10:45:07 AM UTC 24 |
Sep 09 10:46:15 AM UTC 24 |
9272135999 ps |
| T1603 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/43.i2c_host_perf.440283662 |
|
|
Sep 09 10:43:57 AM UTC 24 |
Sep 09 10:46:16 AM UTC 24 |
2567177265 ps |
| T1604 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_timeout.2234953710 |
|
|
Sep 09 10:46:06 AM UTC 24 |
Sep 09 10:46:17 AM UTC 24 |
5143905323 ps |
| T1605 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/42.i2c_target_stress_all.572807428 |
|
|
Sep 09 10:43:42 AM UTC 24 |
Sep 09 10:46:18 AM UTC 24 |
18249219760 ps |
| T1606 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_tx.1956831219 |
|
|
Sep 09 10:46:16 AM UTC 24 |
Sep 09 10:46:18 AM UTC 24 |
92262837 ps |
| T1607 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_perf.2934634773 |
|
|
Sep 09 10:46:13 AM UTC 24 |
Sep 09 10:46:19 AM UTC 24 |
2708347461 ps |
| T1608 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_fifo_watermarks_acq.580682966 |
|
|
Sep 09 10:46:16 AM UTC 24 |
Sep 09 10:46:20 AM UTC 24 |
481625785 ps |
| T1609 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_bad_addr.2975156411 |
|
|
Sep 09 10:46:14 AM UTC 24 |
Sep 09 10:46:20 AM UTC 24 |
547008342 ps |
| T1610 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_txstretch.480708972 |
|
|
Sep 09 10:46:20 AM UTC 24 |
Sep 09 10:46:22 AM UTC 24 |
279903293 ps |
| T1611 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_alert_test.2861002057 |
|
|
Sep 09 10:46:21 AM UTC 24 |
Sep 09 10:46:23 AM UTC 24 |
47345695 ps |
| T1612 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_smbus_maxlen.707581272 |
|
|
Sep 09 10:46:17 AM UTC 24 |
Sep 09 10:46:23 AM UTC 24 |
4347626357 ps |
| T1613 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_tx_stretch_ctrl.2221219665 |
|
|
Sep 09 10:46:17 AM UTC 24 |
Sep 09 10:46:23 AM UTC 24 |
143180463 ps |
| T1614 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_override.2443403198 |
|
|
Sep 09 10:46:22 AM UTC 24 |
Sep 09 10:46:24 AM UTC 24 |
142570160 ps |
| T1615 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_all.1246826292 |
|
|
Sep 09 10:45:31 AM UTC 24 |
Sep 09 10:46:24 AM UTC 24 |
7672873607 ps |
| T1616 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull.3113537984 |
|
|
Sep 09 10:46:18 AM UTC 24 |
Sep 09 10:46:25 AM UTC 24 |
641773757 ps |
| T1617 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_nack_acqfull_addr.2095484989 |
|
|
Sep 09 10:46:20 AM UTC 24 |
Sep 09 10:46:26 AM UTC 24 |
581668686 ps |
| T1618 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_may_nack.478326967 |
|
|
Sep 09 10:46:16 AM UTC 24 |
Sep 09 10:46:26 AM UTC 24 |
5863919887 ps |
| T1619 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_fmt.2983831386 |
|
|
Sep 09 10:46:24 AM UTC 24 |
Sep 09 10:46:27 AM UTC 24 |
233714004 ps |
| T1620 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_perf_precise.2568433035 |
|
|
Sep 09 10:46:26 AM UTC 24 |
Sep 09 10:46:30 AM UTC 24 |
288761657 ps |
| T1621 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_reset_rx.3143765655 |
|
|
Sep 09 10:46:25 AM UTC 24 |
Sep 09 10:46:30 AM UTC 24 |
120021162 ps |
| T1622 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_error_intr.2759658068 |
|
|
Sep 09 10:46:28 AM UTC 24 |
Sep 09 10:46:31 AM UTC 24 |
97889948 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/33.i2c_host_stress_all.2589164078 |
|
|
Sep 09 10:37:07 AM UTC 24 |
Sep 09 10:46:32 AM UTC 24 |
41292637942 ps |
| T1623 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_intr_stress_wr.225295103 |
|
|
Sep 09 10:46:05 AM UTC 24 |
Sep 09 10:46:33 AM UTC 24 |
11263646195 ps |
| T1624 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_target_stretch.253666355 |
|
|
Sep 09 10:44:42 AM UTC 24 |
Sep 09 10:46:39 AM UTC 24 |
2770716588 ps |
| T1625 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_stretch_timeout.4291998716 |
|
|
Sep 09 10:46:28 AM UTC 24 |
Sep 09 10:46:40 AM UTC 24 |
8158828683 ps |
| T1626 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_fmt_empty.2093572423 |
|
|
Sep 09 10:46:24 AM UTC 24 |
Sep 09 10:46:42 AM UTC 24 |
403878886 ps |
| T1627 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/41.i2c_target_stress_wr.2968514145 |
|
|
Sep 09 10:42:50 AM UTC 24 |
Sep 09 10:46:44 AM UTC 24 |
33049879546 ps |
| T1628 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_intr_smoke.5942218 |
|
|
Sep 09 10:46:34 AM UTC 24 |
Sep 09 10:46:46 AM UTC 24 |
2012433001 ps |
| T1629 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_acq.3649160671 |
|
|
Sep 09 10:46:43 AM UTC 24 |
Sep 09 10:46:47 AM UTC 24 |
269930806 ps |
| T1630 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_reset_tx.3371945649 |
|
|
Sep 09 10:46:44 AM UTC 24 |
Sep 09 10:46:47 AM UTC 24 |
136832497 ps |
| T1631 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_smoke.251831337 |
|
|
Sep 09 10:45:45 AM UTC 24 |
Sep 09 10:46:49 AM UTC 24 |
24959874374 ps |
| T1632 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_timeout.251994913 |
|
|
Sep 09 10:46:40 AM UTC 24 |
Sep 09 10:46:50 AM UTC 24 |
1314798073 ps |
| T1633 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_perf.2979969687 |
|
|
Sep 09 10:46:26 AM UTC 24 |
Sep 09 10:46:52 AM UTC 24 |
5805703596 ps |
| T1634 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_hrst.545501917 |
|
|
Sep 09 10:46:49 AM UTC 24 |
Sep 09 10:46:53 AM UTC 24 |
711855419 ps |
| T1635 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_intr_stress_wr.4182430550 |
|
|
Sep 09 10:46:40 AM UTC 24 |
Sep 09 10:46:55 AM UTC 24 |
16032948469 ps |
| T1636 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_perf.3060643014 |
|
|
Sep 09 10:46:46 AM UTC 24 |
Sep 09 10:46:56 AM UTC 24 |
13123035001 ps |
| T1637 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_tx.2569571646 |
|
|
Sep 09 10:46:53 AM UTC 24 |
Sep 09 10:46:57 AM UTC 24 |
293228610 ps |
| T1638 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_bad_addr.170321955 |
|
|
Sep 09 10:46:48 AM UTC 24 |
Sep 09 10:46:58 AM UTC 24 |
1800574581 ps |
| T1639 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_smoke.2349730336 |
|
|
Sep 09 10:46:31 AM UTC 24 |
Sep 09 10:46:58 AM UTC 24 |
2494046433 ps |
| T1640 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_fifo_watermarks_acq.3179631801 |
|
|
Sep 09 10:46:52 AM UTC 24 |
Sep 09 10:46:59 AM UTC 24 |
583531304 ps |
| T1641 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_may_nack.2505676150 |
|
|
Sep 09 10:46:51 AM UTC 24 |
Sep 09 10:46:59 AM UTC 24 |
2886236709 ps |
| T1642 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_smbus_maxlen.2570595978 |
|
|
Sep 09 10:46:55 AM UTC 24 |
Sep 09 10:47:00 AM UTC 24 |
471043906 ps |
| T1643 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_overflow.2287363748 |
|
|
Sep 09 10:44:33 AM UTC 24 |
Sep 09 10:47:01 AM UTC 24 |
11152875252 ps |
| T1644 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_alert_test.85599 |
|
|
Sep 09 10:46:59 AM UTC 24 |
Sep 09 10:47:01 AM UTC 24 |
28282872 ps |
| T1645 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull.2968793846 |
|
|
Sep 09 10:46:57 AM UTC 24 |
Sep 09 10:47:03 AM UTC 24 |
1213408843 ps |
| T1646 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_override.3164595648 |
|
|
Sep 09 10:47:00 AM UTC 24 |
Sep 09 10:47:02 AM UTC 24 |
19063898 ps |
| T1647 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_tx_stretch_ctrl.976164643 |
|
|
Sep 09 10:46:54 AM UTC 24 |
Sep 09 10:47:02 AM UTC 24 |
167501670 ps |
| T1648 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_nack_acqfull_addr.2479213816 |
|
|
Sep 09 10:46:57 AM UTC 24 |
Sep 09 10:47:03 AM UTC 24 |
506188514 ps |
| T1649 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_overflow.2966563152 |
|
|
Sep 09 10:45:46 AM UTC 24 |
Sep 09 10:47:04 AM UTC 24 |
17116774168 ps |
| T1650 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_fmt.3991326299 |
|
|
Sep 09 10:47:02 AM UTC 24 |
Sep 09 10:47:05 AM UTC 24 |
588991234 ps |
| T1651 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_perf_precise.1009731832 |
|
|
Sep 09 10:47:04 AM UTC 24 |
Sep 09 10:47:07 AM UTC 24 |
76763951 ps |
| T1652 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_error_intr.3923700667 |
|
|
Sep 09 10:47:06 AM UTC 24 |
Sep 09 10:47:09 AM UTC 24 |
121948751 ps |
| T1653 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_fmt_empty.908101204 |
|
|
Sep 09 10:47:03 AM UTC 24 |
Sep 09 10:47:10 AM UTC 24 |
452280969 ps |
| T1654 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/41.i2c_target_stress_all.3055919617 |
|
|
Sep 09 10:43:07 AM UTC 24 |
Sep 09 10:47:14 AM UTC 24 |
20937473789 ps |
| T1655 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_rd.3410977983 |
|
|
Sep 09 10:46:32 AM UTC 24 |
Sep 09 10:47:14 AM UTC 24 |
3180120934 ps |
| T1656 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_watermark.783454606 |
|
|
Sep 09 10:44:33 AM UTC 24 |
Sep 09 10:49:23 AM UTC 24 |
9865260460 ps |
| T1657 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_reset_rx.2223782718 |
|
|
Sep 09 10:47:03 AM UTC 24 |
Sep 09 10:47:17 AM UTC 24 |
610637897 ps |
| T1658 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_host_perf.3234953973 |
|
|
Sep 09 10:36:28 AM UTC 24 |
Sep 09 10:47:19 AM UTC 24 |
48858305594 ps |
| T1659 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_stretch_timeout.4165660792 |
|
|
Sep 09 10:47:06 AM UTC 24 |
Sep 09 10:47:22 AM UTC 24 |
820724436 ps |
| T1660 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_wr.2692051504 |
|
|
Sep 09 10:47:11 AM UTC 24 |
Sep 09 10:47:22 AM UTC 24 |
8508752977 ps |
| T1661 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_smoke.1890169485 |
|
|
Sep 09 10:46:21 AM UTC 24 |
Sep 09 10:47:23 AM UTC 24 |
2157660286 ps |
| T1662 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/42.i2c_host_fifo_watermark.2207628079 |
|
|
Sep 09 10:43:21 AM UTC 24 |
Sep 09 10:47:24 AM UTC 24 |
34469743145 ps |
| T1663 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_acq.978960210 |
|
|
Sep 09 10:47:23 AM UTC 24 |
Sep 09 10:47:26 AM UTC 24 |
334729874 ps |
| T1664 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_reset_tx.4244062581 |
|
|
Sep 09 10:47:24 AM UTC 24 |
Sep 09 10:47:27 AM UTC 24 |
163460264 ps |
| T1665 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_overflow.1544051668 |
|
|
Sep 09 10:46:23 AM UTC 24 |
Sep 09 10:47:28 AM UTC 24 |
2550876230 ps |
| T1666 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_full.1820634022 |
|
|
Sep 09 10:45:09 AM UTC 24 |
Sep 09 10:47:29 AM UTC 24 |
2216767318 ps |
| T1667 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_intr_smoke.3002823928 |
|
|
Sep 09 10:47:17 AM UTC 24 |
Sep 09 10:47:29 AM UTC 24 |
3928794414 ps |
| T1668 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_timeout.3035616117 |
|
|
Sep 09 10:47:20 AM UTC 24 |
Sep 09 10:47:31 AM UTC 24 |
1147350905 ps |
| T1669 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_smoke.3673414247 |
|
|
Sep 09 10:47:10 AM UTC 24 |
Sep 09 10:47:32 AM UTC 24 |
1198418169 ps |
| T1670 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_mode_toggle.3459012338 |
|
|
Sep 09 10:47:29 AM UTC 24 |
Sep 09 10:47:33 AM UTC 24 |
134727074 ps |
| T1671 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_hrst.3906680598 |
|
|
Sep 09 10:47:29 AM UTC 24 |
Sep 09 10:47:34 AM UTC 24 |
372073632 ps |
| T1672 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_rd.3657053228 |
|
|
Sep 09 10:47:15 AM UTC 24 |
Sep 09 10:47:35 AM UTC 24 |
5015723173 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/16.i2c_host_stress_all.518943049 |
|
|
Sep 09 10:27:57 AM UTC 24 |
Sep 09 10:47:35 AM UTC 24 |
41211394784 ps |
| T1673 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_acq.2298510343 |
|
|
Sep 09 10:47:30 AM UTC 24 |
Sep 09 10:47:35 AM UTC 24 |
563516647 ps |
| T1674 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_fifo_watermarks_tx.408904111 |
|
|
Sep 09 10:47:32 AM UTC 24 |
Sep 09 10:47:36 AM UTC 24 |
148202059 ps |
| T1675 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_bad_addr.655640375 |
|
|
Sep 09 10:47:28 AM UTC 24 |
Sep 09 10:47:36 AM UTC 24 |
3019056720 ps |
| T1676 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_perf.2372818800 |
|
|
Sep 09 10:47:26 AM UTC 24 |
Sep 09 10:47:36 AM UTC 24 |
3140443166 ps |
| T1677 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_smoke.1674778393 |
|
|
Sep 09 10:47:00 AM UTC 24 |
Sep 09 10:47:36 AM UTC 24 |
1593441571 ps |
| T1678 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_tx_stretch_ctrl.2462502308 |
|
|
Sep 09 10:47:33 AM UTC 24 |
Sep 09 10:47:37 AM UTC 24 |
103248293 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_may_nack.163076887 |
|
|
Sep 09 10:47:30 AM UTC 24 |
Sep 09 10:47:38 AM UTC 24 |
1910839776 ps |
| T1679 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_smbus_maxlen.1480048861 |
|
|
Sep 09 10:47:33 AM UTC 24 |
Sep 09 10:47:38 AM UTC 24 |
751610157 ps |
| T1680 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/44.i2c_host_fifo_full.840374189 |
|
|
Sep 09 10:44:36 AM UTC 24 |
Sep 09 10:47:38 AM UTC 24 |
13404098931 ps |
| T1681 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_alert_test.528746088 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:47:39 AM UTC 24 |
64100576 ps |
| T1682 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_override.3506383699 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:47:39 AM UTC 24 |
31557012 ps |
| T1683 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull_addr.3518532628 |
|
|
Sep 09 10:47:35 AM UTC 24 |
Sep 09 10:47:39 AM UTC 24 |
515986363 ps |
| T1684 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_nack_txstretch.2671613794 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:47:40 AM UTC 24 |
1103501888 ps |
| T1685 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_nack_acqfull.172854889 |
|
|
Sep 09 10:47:35 AM UTC 24 |
Sep 09 10:47:40 AM UTC 24 |
2099986184 ps |
| T1686 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_all.1197503469 |
|
|
Sep 09 10:46:47 AM UTC 24 |
Sep 09 10:47:41 AM UTC 24 |
17395066358 ps |
| T1687 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_fmt.889348974 |
|
|
Sep 09 10:47:38 AM UTC 24 |
Sep 09 10:47:41 AM UTC 24 |
435675604 ps |
| T1688 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_perf_precise.3008065619 |
|
|
Sep 09 10:47:39 AM UTC 24 |
Sep 09 10:47:42 AM UTC 24 |
76393464 ps |
| T1689 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_stretch.67382545 |
|
|
Sep 09 10:47:15 AM UTC 24 |
Sep 09 10:47:43 AM UTC 24 |
4972763384 ps |
| T1690 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_full.4045471619 |
|
|
Sep 09 10:45:50 AM UTC 24 |
Sep 09 10:47:44 AM UTC 24 |
6349095997 ps |
| T1691 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_reset_rx.3478190145 |
|
|
Sep 09 10:47:39 AM UTC 24 |
Sep 09 10:47:45 AM UTC 24 |
431248582 ps |
| T1692 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_error_intr.1029056609 |
|
|
Sep 09 10:47:40 AM UTC 24 |
Sep 09 10:47:47 AM UTC 24 |
3798332226 ps |
| T1693 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_fifo_watermark.433552351 |
|
|
Sep 09 10:45:06 AM UTC 24 |
Sep 09 10:47:47 AM UTC 24 |
18241430908 ps |
| T1694 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_fmt_empty.3344682216 |
|
|
Sep 09 10:47:39 AM UTC 24 |
Sep 09 10:47:48 AM UTC 24 |
253081295 ps |
| T1695 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_acq.870816790 |
|
|
Sep 09 10:47:49 AM UTC 24 |
Sep 09 10:47:52 AM UTC 24 |
305758361 ps |
| T1696 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_reset_tx.3051884925 |
|
|
Sep 09 10:47:51 AM UTC 24 |
Sep 09 10:47:55 AM UTC 24 |
264945033 ps |
| T1697 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_intr_smoke.1561886837 |
|
|
Sep 09 10:47:45 AM UTC 24 |
Sep 09 10:47:57 AM UTC 24 |
993889189 ps |
| T1698 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/43.i2c_target_stress_all.3783918748 |
|
|
Sep 09 10:44:21 AM UTC 24 |
Sep 09 10:47:57 AM UTC 24 |
76491374170 ps |
| T1699 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_timeout.3989410375 |
|
|
Sep 09 10:47:47 AM UTC 24 |
Sep 09 10:47:59 AM UTC 24 |
4169586406 ps |
| T1700 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_hrst.2988528052 |
|
|
Sep 09 10:47:58 AM UTC 24 |
Sep 09 10:48:02 AM UTC 24 |
266759573 ps |
| T1701 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_stretch_timeout.1956880934 |
|
|
Sep 09 10:47:40 AM UTC 24 |
Sep 09 10:48:03 AM UTC 24 |
2584006836 ps |
| T1702 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_mode_toggle.3562285061 |
|
|
Sep 09 10:47:58 AM UTC 24 |
Sep 09 10:48:03 AM UTC 24 |
90680791 ps |
| T1703 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_perf.2198365745 |
|
|
Sep 09 10:47:52 AM UTC 24 |
Sep 09 10:48:04 AM UTC 24 |
805367404 ps |
| T1704 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_smoke.3691402940 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:48:06 AM UTC 24 |
1800518538 ps |
| T1705 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_bad_addr.3293343914 |
|
|
Sep 09 10:47:55 AM UTC 24 |
Sep 09 10:48:06 AM UTC 24 |
1116983937 ps |
| T1706 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_tx.3850508367 |
|
|
Sep 09 10:48:04 AM UTC 24 |
Sep 09 10:48:07 AM UTC 24 |
852685434 ps |
| T1707 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_fifo_watermarks_acq.3230195409 |
|
|
Sep 09 10:48:03 AM UTC 24 |
Sep 09 10:48:08 AM UTC 24 |
5169684047 ps |
| T1708 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_tx_stretch_ctrl.4036053983 |
|
|
Sep 09 10:48:04 AM UTC 24 |
Sep 09 10:48:09 AM UTC 24 |
177765308 ps |
| T1709 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_alert_test.9033857 |
|
|
Sep 09 10:48:07 AM UTC 24 |
Sep 09 10:48:09 AM UTC 24 |
16012178 ps |
| T1710 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_smbus_maxlen.756586563 |
|
|
Sep 09 10:48:05 AM UTC 24 |
Sep 09 10:48:10 AM UTC 24 |
2570963950 ps |
| T1711 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_smoke.4222947096 |
|
|
Sep 09 10:47:42 AM UTC 24 |
Sep 09 10:48:12 AM UTC 24 |
2124195568 ps |
| T1712 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_rd.2510413242 |
|
|
Sep 09 10:47:43 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
1357485593 ps |
| T1713 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull.1084743769 |
|
|
Sep 09 10:48:07 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
7144515129 ps |
| T1714 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_nack_acqfull_addr.1905017224 |
|
|
Sep 09 10:48:07 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
1821369634 ps |
| T1715 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_may_nack.3552975179 |
|
|
Sep 09 10:48:00 AM UTC 24 |
Sep 09 10:48:14 AM UTC 24 |
734516447 ps |
| T1716 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_overflow.3222928836 |
|
|
Sep 09 10:47:02 AM UTC 24 |
Sep 09 10:48:14 AM UTC 24 |
2434497564 ps |
| T1717 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_watermark.3987059966 |
|
|
Sep 09 10:47:01 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
8000522189 ps |
| T1718 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_wr.4165096965 |
|
|
Sep 09 10:47:42 AM UTC 24 |
Sep 09 10:48:24 AM UTC 24 |
12628623561 ps |
| T1719 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_perf.3584925527 |
|
|
Sep 09 10:47:04 AM UTC 24 |
Sep 09 10:48:39 AM UTC 24 |
12831132176 ps |
| T1720 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_perf.1879296692 |
|
|
Sep 09 10:47:39 AM UTC 24 |
Sep 09 10:48:39 AM UTC 24 |
5639165166 ps |
| T1721 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_host_perf.1342540512 |
|
|
Sep 09 10:45:11 AM UTC 24 |
Sep 09 10:48:40 AM UTC 24 |
25563528144 ps |
| T1722 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_full.1095175225 |
|
|
Sep 09 10:46:25 AM UTC 24 |
Sep 09 10:48:51 AM UTC 24 |
11373977212 ps |
| T1723 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_full.1522275387 |
|
|
Sep 09 10:47:39 AM UTC 24 |
Sep 09 10:49:04 AM UTC 24 |
2669130640 ps |
| T1724 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_intr_stress_wr.1025264898 |
|
|
Sep 09 10:47:18 AM UTC 24 |
Sep 09 10:49:04 AM UTC 24 |
13373601584 ps |
| T1725 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_overflow.1198880515 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:49:12 AM UTC 24 |
3095882148 ps |
| T1726 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_fifo_watermark.1430279524 |
|
|
Sep 09 10:47:37 AM UTC 24 |
Sep 09 10:49:28 AM UTC 24 |
56424218408 ps |
| T1727 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_host_fifo_full.593634833 |
|
|
Sep 09 10:47:03 AM UTC 24 |
Sep 09 10:49:50 AM UTC 24 |
13903681749 ps |
| T1728 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/12.i2c_target_stress_all.1267990009 |
|
|
Sep 09 10:26:04 AM UTC 24 |
Sep 09 10:49:55 AM UTC 24 |
71278940333 ps |
| T1729 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_all.3133230269 |
|
|
Sep 09 10:46:13 AM UTC 24 |
Sep 09 10:49:58 AM UTC 24 |
27720009484 ps |
| T1730 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_intr_stress_wr.2317261600 |
|
|
Sep 09 10:47:46 AM UTC 24 |
Sep 09 10:50:02 AM UTC 24 |
16775383049 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/29.i2c_host_stress_all.2667624104 |
|
|
Sep 09 10:34:45 AM UTC 24 |
Sep 09 10:50:12 AM UTC 24 |
13009186250 ps |
| T1731 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_host_fifo_watermark.1101013889 |
|
|
Sep 09 10:45:45 AM UTC 24 |
Sep 09 10:50:19 AM UTC 24 |
6698056201 ps |
| T1732 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_target_stress_wr.367432498 |
|
|
Sep 09 10:46:31 AM UTC 24 |
Sep 09 10:50:28 AM UTC 24 |
45050692153 ps |
| T1733 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/46.i2c_target_stress_wr.932895638 |
|
|
Sep 09 10:45:57 AM UTC 24 |
Sep 09 10:50:35 AM UTC 24 |
48546937345 ps |
| T1734 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/48.i2c_target_stress_all.1716099989 |
|
|
Sep 09 10:47:27 AM UTC 24 |
Sep 09 10:50:38 AM UTC 24 |
33505622799 ps |
| T1735 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/47.i2c_host_fifo_watermark.960633668 |
|
|
Sep 09 10:46:23 AM UTC 24 |
Sep 09 10:51:21 AM UTC 24 |
35524474308 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/11.i2c_host_stress_all.3413164454 |
|
|
Sep 09 10:25:17 AM UTC 24 |
Sep 09 10:52:19 AM UTC 24 |
19152755254 ps |
| T1736 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_target_stress_wr.2528727990 |
|
|
Sep 09 10:36:03 AM UTC 24 |
Sep 09 10:53:27 AM UTC 24 |
56886503692 ps |
| T1737 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/36.i2c_host_perf.3405667992 |
|
|
Sep 09 10:39:02 AM UTC 24 |
Sep 09 10:55:31 AM UTC 24 |
26764829668 ps |
| T1738 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/20.i2c_host_perf.2962458823 |
|
|
Sep 09 10:30:04 AM UTC 24 |
Sep 09 10:58:12 AM UTC 24 |
50247658179 ps |
| T1739 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/32.i2c_target_stress_wr.1454446861 |
|
|
Sep 09 10:36:35 AM UTC 24 |
Sep 09 11:01:18 AM UTC 24 |
68615412369 ps |
| T1740 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_target_stress_all.548470160 |
|
|
Sep 09 10:47:53 AM UTC 24 |
Sep 09 11:01:19 AM UTC 24 |
44247613357 ps |
| T1741 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/43.i2c_target_stress_wr.927290023 |
|
|
Sep 09 10:44:03 AM UTC 24 |
Sep 09 11:01:55 AM UTC 24 |
60840207616 ps |
| T1742 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/45.i2c_target_stress_wr.2293801889 |
|
|
Sep 09 10:45:17 AM UTC 24 |
Sep 09 11:06:27 AM UTC 24 |
67569886069 ps |
| T1743 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/31.i2c_host_stress_all.162506585 |
|
|
Sep 09 10:35:58 AM UTC 24 |
Sep 09 11:08:18 AM UTC 24 |
19595312144 ps |
| T1744 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/35.i2c_host_perf.3056982693 |
|
|
Sep 09 10:38:30 AM UTC 24 |
Sep 09 11:10:41 AM UTC 24 |
49551854581 ps |
| T1745 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/18.i2c_host_stress_all.4120668959 |
|
|
Sep 09 10:29:00 AM UTC 24 |
Sep 09 11:11:33 AM UTC 24 |
45501629930 ps |
| T1746 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/15.i2c_host_perf.1525522785 |
|
|
Sep 09 10:27:24 AM UTC 24 |
Sep 09 11:18:40 AM UTC 24 |
72065746793 ps |
| T1747 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/24.i2c_host_perf.3260932301 |
|
|
Sep 09 10:31:51 AM UTC 24 |
Sep 09 11:22:06 AM UTC 24 |
73739844578 ps |
| T1748 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/default/49.i2c_host_stress_all.415913398 |
|
|
Sep 09 10:47:41 AM UTC 24 |
Sep 09 11:30:03 AM UTC 24 |
124848671458 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_errors.1282761368 |
|
|
Sep 09 10:48:09 AM UTC 24 |
Sep 09 10:48:12 AM UTC 24 |
197256985 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_tl_intg_err.771601173 |
|
|
Sep 09 10:48:10 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
266591164 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_hw_reset.2334278498 |
|
|
Sep 09 10:48:11 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
48256904 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_intr_test.168904441 |
|
|
Sep 09 10:48:11 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
20444227 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_rw.1612955442 |
|
|
Sep 09 10:48:11 AM UTC 24 |
Sep 09 10:48:13 AM UTC 24 |
32292221 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_intr_test.4009429214 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:16 AM UTC 24 |
189794284 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_rw.145624709 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
43435019 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_same_csr_outstanding.4174888782 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
78427018 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_hw_reset.157193106 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
100591631 ps |
| T1749 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_aliasing.1500328995 |
|
|
Sep 09 10:48:13 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
1428909987 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_errors.4178003842 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:17 AM UTC 24 |
94603874 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.97425916 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:18 AM UTC 24 |
53284085 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_tl_intg_err.1487700250 |
|
|
Sep 09 10:48:14 AM UTC 24 |
Sep 09 10:48:18 AM UTC 24 |
548199966 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/0.i2c_csr_bit_bash.2367293371 |
|
|
Sep 09 10:48:13 AM UTC 24 |
Sep 09 10:48:18 AM UTC 24 |
247911798 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_aliasing.1616288444 |
|
|
Sep 09 10:48:16 AM UTC 24 |
Sep 09 10:48:18 AM UTC 24 |
100415237 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2598210775 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:20 AM UTC 24 |
40841979 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.2259663361 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:20 AM UTC 24 |
17265287 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_intr_test.1414509520 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:20 AM UTC 24 |
18370671 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_rw.1283637549 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:20 AM UTC 24 |
72820952 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_hw_reset.1885904766 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:20 AM UTC 24 |
61703067 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_intg_err.642855468 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:21 AM UTC 24 |
78150051 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.931840844 |
|
|
Sep 09 10:48:19 AM UTC 24 |
Sep 09 10:48:22 AM UTC 24 |
238782514 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_tl_errors.2766976325 |
|
|
Sep 09 10:48:18 AM UTC 24 |
Sep 09 10:48:22 AM UTC 24 |
94918256 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_same_csr_outstanding.228176326 |
|
|
Sep 09 10:48:19 AM UTC 24 |
Sep 09 10:48:22 AM UTC 24 |
283789467 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_hw_reset.1962566150 |
|
|
Sep 09 10:48:21 AM UTC 24 |
Sep 09 10:48:23 AM UTC 24 |
28628475 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_intr_test.3520578527 |
|
|
Sep 09 10:48:21 AM UTC 24 |
Sep 09 10:48:23 AM UTC 24 |
111643099 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_aliasing.774129164 |
|
|
Sep 09 10:48:19 AM UTC 24 |
Sep 09 10:48:23 AM UTC 24 |
650876138 ps |
| T1750 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/1.i2c_csr_bit_bash.4276606844 |
|
|
Sep 09 10:48:16 AM UTC 24 |
Sep 09 10:48:24 AM UTC 24 |
362600200 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_rw.489358116 |
|
|
Sep 09 10:48:22 AM UTC 24 |
Sep 09 10:48:24 AM UTC 24 |
52731695 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/2.i2c_csr_bit_bash.3580298017 |
|
|
Sep 09 10:48:19 AM UTC 24 |
Sep 09 10:48:24 AM UTC 24 |
288585714 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_intg_err.3770591596 |
|
|
Sep 09 10:48:21 AM UTC 24 |
Sep 09 10:48:24 AM UTC 24 |
81238410 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_tl_errors.1921070560 |
|
|
Sep 09 10:48:21 AM UTC 24 |
Sep 09 10:48:25 AM UTC 24 |
166977349 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_same_csr_outstanding.486318864 |
|
|
Sep 09 10:48:23 AM UTC 24 |
Sep 09 10:48:26 AM UTC 24 |
174184229 ps |
| T1751 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_aliasing.1360069181 |
|
|
Sep 09 10:48:23 AM UTC 24 |
Sep 09 10:48:26 AM UTC 24 |
166172667 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.2174566794 |
|
|
Sep 09 10:48:23 AM UTC 24 |
Sep 09 10:48:26 AM UTC 24 |
39874824 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_hw_reset.771657722 |
|
|
Sep 09 10:48:25 AM UTC 24 |
Sep 09 10:48:27 AM UTC 24 |
27213399 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_intr_test.1714677860 |
|
|
Sep 09 10:48:25 AM UTC 24 |
Sep 09 10:48:27 AM UTC 24 |
32496931 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_errors.3155072062 |
|
|
Sep 09 10:48:23 AM UTC 24 |
Sep 09 10:48:28 AM UTC 24 |
91629478 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_tl_intg_err.1621665742 |
|
|
Sep 09 10:48:25 AM UTC 24 |
Sep 09 10:48:28 AM UTC 24 |
71236534 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_rw.2477087725 |
|
|
Sep 09 10:48:26 AM UTC 24 |
Sep 09 10:48:28 AM UTC 24 |
49825107 ps |
| T1752 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.2483924835 |
|
|
Sep 09 10:48:26 AM UTC 24 |
Sep 09 10:48:28 AM UTC 24 |
62690438 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_same_csr_outstanding.1320831758 |
|
|
Sep 09 10:48:26 AM UTC 24 |
Sep 09 10:48:29 AM UTC 24 |
26091899 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/3.i2c_csr_bit_bash.1370360402 |
|
|
Sep 09 10:48:22 AM UTC 24 |
Sep 09 10:48:30 AM UTC 24 |
112447116 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_intr_test.1724171879 |
|
|
Sep 09 10:48:28 AM UTC 24 |
Sep 09 10:48:30 AM UTC 24 |
60488759 ps |
| T1753 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_aliasing.3145542622 |
|
|
Sep 09 10:48:26 AM UTC 24 |
Sep 09 10:48:30 AM UTC 24 |
1396511448 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_rw.1235339320 |
|
|
Sep 09 10:48:28 AM UTC 24 |
Sep 09 10:48:30 AM UTC 24 |
27256057 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_same_csr_outstanding.4209160698 |
|
|
Sep 09 10:48:28 AM UTC 24 |
Sep 09 10:48:30 AM UTC 24 |
239484294 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_intg_err.1690104085 |
|
|
Sep 09 10:48:27 AM UTC 24 |
Sep 09 10:48:31 AM UTC 24 |
83614075 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_tl_errors.1545063260 |
|
|
Sep 09 10:48:27 AM UTC 24 |
Sep 09 10:48:31 AM UTC 24 |
42907464 ps |
| T1754 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/5.i2c_csr_mem_rw_with_rand_reset.1880484399 |
|
|
Sep 09 10:48:29 AM UTC 24 |
Sep 09 10:48:31 AM UTC 24 |
20506512 ps |
| T1755 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_errors.997884461 |
|
|
Sep 09 10:48:29 AM UTC 24 |
Sep 09 10:48:32 AM UTC 24 |
48551306 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_intr_test.760562837 |
|
|
Sep 09 10:48:30 AM UTC 24 |
Sep 09 10:48:33 AM UTC 24 |
41986681 ps |
| T1756 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_rw.3031758120 |
|
|
Sep 09 10:48:30 AM UTC 24 |
Sep 09 10:48:33 AM UTC 24 |
198362738 ps |
| T1757 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_same_csr_outstanding.1398007526 |
|
|
Sep 09 10:48:30 AM UTC 24 |
Sep 09 10:48:33 AM UTC 24 |
279672169 ps |
| T1758 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_csr_mem_rw_with_rand_reset.679969389 |
|
|
Sep 09 10:48:30 AM UTC 24 |
Sep 09 10:48:33 AM UTC 24 |
79260064 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/6.i2c_tl_intg_err.537356561 |
|
|
Sep 09 10:48:29 AM UTC 24 |
Sep 09 10:48:34 AM UTC 24 |
501414773 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_intr_test.5771891 |
|
|
Sep 09 10:48:32 AM UTC 24 |
Sep 09 10:48:34 AM UTC 24 |
17408337 ps |
| T1759 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_rw.2307266158 |
|
|
Sep 09 10:48:32 AM UTC 24 |
Sep 09 10:48:34 AM UTC 24 |
36983409 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/4.i2c_csr_bit_bash.451095698 |
|
|
Sep 09 10:48:26 AM UTC 24 |
Sep 09 10:48:34 AM UTC 24 |
374181699 ps |
| T1760 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_same_csr_outstanding.1128959050 |
|
|
Sep 09 10:48:32 AM UTC 24 |
Sep 09 10:48:35 AM UTC 24 |
48268904 ps |
| T1761 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/12.i2c_tl_errors.1346846344 |
|
|
Sep 09 10:48:40 AM UTC 24 |
Sep 09 10:48:43 AM UTC 24 |
156381337 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_intg_err.3231236901 |
|
|
Sep 09 10:48:32 AM UTC 24 |
Sep 09 10:48:35 AM UTC 24 |
71824317 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_intr_test.2367404091 |
|
|
Sep 09 10:48:33 AM UTC 24 |
Sep 09 10:48:36 AM UTC 24 |
89856888 ps |
| T1762 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_csr_rw.3222848071 |
|
|
Sep 09 10:48:33 AM UTC 24 |
Sep 09 10:48:36 AM UTC 24 |
41239542 ps |
| T1763 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_tl_errors.3512177615 |
|
|
Sep 09 10:48:32 AM UTC 24 |
Sep 09 10:48:36 AM UTC 24 |
75034783 ps |
| T1764 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/7.i2c_csr_mem_rw_with_rand_reset.1348277945 |
|
|
Sep 09 10:48:33 AM UTC 24 |
Sep 09 10:48:36 AM UTC 24 |
66037411 ps |
| T1765 |
/workspaces/repo/scratch/os_regression_2024_09_08/i2c-sim-vcs/coverage/cover_reg_top/8.i2c_same_csr_outstanding.4229632377 |
|
|
Sep 09 10:48:33 AM UTC 24 |
Sep 09 10:48:36 AM UTC 24 |
82507305 ps |