KEYMGR Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: 26b0ee226

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 1.181m 4.805ms 50 50 100.00
V1 random keymgr_random 49.000s 4.679ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.400s 120.418us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.510s 30.905us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 12.380s 909.842us 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 6.850s 129.709us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.860s 42.680us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.510s 30.905us 20 20 100.00
keymgr_csr_aliasing 6.850s 129.709us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 1.587m 7.443ms 50 50 100.00
V2 sideload keymgr_sideload 35.520s 3.646ms 50 50 100.00
keymgr_sideload_kmac 49.540s 2.092ms 49 50 98.00
keymgr_sideload_aes 49.260s 13.401ms 50 50 100.00
keymgr_sideload_otbn 1.456m 8.975ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 19.720s 8.399ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 35.800s 805.216us 49 50 98.00
V2 kmac_error_response keymgr_kmac_rsp_err 58.320s 5.905ms 40 50 80.00
V2 invalid_sw_input keymgr_sw_invalid_input 56.070s 15.761ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 58.350s 2.171ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 37.860s 4.639ms 50 50 100.00
V2 stress_all keymgr_stress_all 17.103m 110.109ms 50 50 100.00
V2 intr_test keymgr_intr_test 0.920s 21.147us 50 50 100.00
V2 alert_test keymgr_alert_test 0.990s 21.296us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.680s 133.971us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.680s 133.971us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.400s 120.418us 5 5 100.00
keymgr_csr_rw 1.510s 30.905us 20 20 100.00
keymgr_csr_aliasing 6.850s 129.709us 5 5 100.00
keymgr_same_csr_outstanding 4.190s 319.194us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.400s 120.418us 5 5 100.00
keymgr_csr_rw 1.510s 30.905us 20 20 100.00
keymgr_csr_aliasing 6.850s 129.709us 5 5 100.00
keymgr_same_csr_outstanding 4.190s 319.194us 20 20 100.00
V2 TOTAL 728 740 98.38
V2S sec_cm_additional_check keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
keymgr_tl_intg_err 23.400s 4.068ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 22.840s 13.218ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 22.840s 13.218ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 22.840s 13.218ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 22.840s 13.218ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 17.300s 1.042ms 20 20 100.00
V2S prim_count_check keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 23.400s 4.068ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 22.840s 13.218ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 1.587m 7.443ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 49.000s 4.679ms 50 50 100.00
keymgr_csr_rw 1.510s 30.905us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 49.000s 4.679ms 50 50 100.00
keymgr_csr_rw 1.510s 30.905us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 49.000s 4.679ms 50 50 100.00
keymgr_csr_rw 1.510s 30.905us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 35.800s 805.216us 49 50 98.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 58.350s 2.171ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 58.350s 2.171ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 49.000s 4.679ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 23.640s 2.407ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 1.116m 7.123ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 35.800s 805.216us 49 50 98.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 1.116m 7.123ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 1.116m 7.123ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 1.116m 7.123ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 2.130m 14.696ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 1.116m 7.123ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 15.240s 421.049us 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 1092 1110 98.38

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 13 81.25
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.78 99.09 98.13 98.03 100.00 99.08 98.38 91.78

Failure Buckets

Past Results