KEYMGR Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: 94eb0df12

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke keymgr_smoke 38.310s 3.746ms 50 50 100.00
V1 random keymgr_random 1.552m 9.559ms 50 50 100.00
V1 csr_hw_reset keymgr_csr_hw_reset 1.360s 54.341us 5 5 100.00
V1 csr_rw keymgr_csr_rw 1.630s 125.962us 20 20 100.00
V1 csr_bit_bash keymgr_csr_bit_bash 25.610s 5.118ms 5 5 100.00
V1 csr_aliasing keymgr_csr_aliasing 8.620s 253.383us 5 5 100.00
V1 csr_mem_rw_with_rand_reset keymgr_csr_mem_rw_with_rand_reset 1.670s 172.065us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr keymgr_csr_rw 1.630s 125.962us 20 20 100.00
keymgr_csr_aliasing 8.620s 253.383us 5 5 100.00
V1 TOTAL 155 155 100.00
V2 cfgen_during_op keymgr_cfg_regwen 2.031m 2.272ms 50 50 100.00
V2 sideload keymgr_sideload 26.100s 1.657ms 50 50 100.00
keymgr_sideload_kmac 45.040s 3.348ms 50 50 100.00
keymgr_sideload_aes 1.318m 32.266ms 50 50 100.00
keymgr_sideload_otbn 45.160s 1.950ms 50 50 100.00
V2 direct_to_disabled_state keymgr_direct_to_disabled 43.180s 5.079ms 50 50 100.00
V2 lc_disable keymgr_lc_disable 26.130s 575.579us 50 50 100.00
V2 kmac_error_response keymgr_kmac_rsp_err 1.267m 24.373ms 42 50 84.00
V2 invalid_sw_input keymgr_sw_invalid_input 1.228m 14.420ms 50 50 100.00
V2 invalid_hw_input keymgr_hwsw_invalid_input 28.980s 5.502ms 50 50 100.00
V2 sync_async_fault_cross keymgr_sync_async_fault_cross 19.700s 956.071us 49 50 98.00
V2 stress_all keymgr_stress_all 7.024m 21.403ms 49 50 98.00
V2 intr_test keymgr_intr_test 0.930s 14.353us 50 50 100.00
V2 alert_test keymgr_alert_test 1.010s 13.045us 50 50 100.00
V2 tl_d_oob_addr_access keymgr_tl_errors 4.880s 188.997us 20 20 100.00
V2 tl_d_illegal_access keymgr_tl_errors 4.880s 188.997us 20 20 100.00
V2 tl_d_outstanding_access keymgr_csr_hw_reset 1.360s 54.341us 5 5 100.00
keymgr_csr_rw 1.630s 125.962us 20 20 100.00
keymgr_csr_aliasing 8.620s 253.383us 5 5 100.00
keymgr_same_csr_outstanding 4.370s 445.837us 20 20 100.00
V2 tl_d_partial_access keymgr_csr_hw_reset 1.360s 54.341us 5 5 100.00
keymgr_csr_rw 1.630s 125.962us 20 20 100.00
keymgr_csr_aliasing 8.620s 253.383us 5 5 100.00
keymgr_same_csr_outstanding 4.370s 445.837us 20 20 100.00
V2 TOTAL 730 740 98.65
V2S sec_cm_additional_check keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S tl_intg_err keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
keymgr_tl_intg_err 58.310s 1.993ms 20 20 100.00
V2S shadow_reg_update_error keymgr_shadow_reg_errors 12.090s 2.441ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value keymgr_shadow_reg_errors 12.090s 2.441ms 20 20 100.00
V2S shadow_reg_storage_error keymgr_shadow_reg_errors 12.090s 2.441ms 20 20 100.00
V2S shadowed_reset_glitch keymgr_shadow_reg_errors 12.090s 2.441ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw keymgr_shadow_reg_errors_with_csr_rw 17.400s 951.560us 20 20 100.00
V2S prim_count_check keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S prim_fsm_check keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_bus_integrity keymgr_tl_intg_err 58.310s 1.993ms 20 20 100.00
V2S sec_cm_config_shadow keymgr_shadow_reg_errors 12.090s 2.441ms 20 20 100.00
V2S sec_cm_op_config_regwen keymgr_cfg_regwen 2.031m 2.272ms 50 50 100.00
V2S sec_cm_reseed_config_regwen keymgr_random 1.552m 9.559ms 50 50 100.00
keymgr_csr_rw 1.630s 125.962us 20 20 100.00
V2S sec_cm_sw_binding_config_regwen keymgr_random 1.552m 9.559ms 50 50 100.00
keymgr_csr_rw 1.630s 125.962us 20 20 100.00
V2S sec_cm_max_key_ver_config_regwen keymgr_random 1.552m 9.559ms 50 50 100.00
keymgr_csr_rw 1.630s 125.962us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi keymgr_lc_disable 26.130s 575.579us 50 50 100.00
V2S sec_cm_constants_consistency keymgr_hwsw_invalid_input 28.980s 5.502ms 50 50 100.00
V2S sec_cm_intersig_consistency keymgr_hwsw_invalid_input 28.980s 5.502ms 50 50 100.00
V2S sec_cm_hw_key_sw_noaccess keymgr_random 1.552m 9.559ms 50 50 100.00
V2S sec_cm_output_keys_ctrl_redun keymgr_sideload_protect 32.050s 5.307ms 50 50 100.00
V2S sec_cm_ctrl_fsm_sparse keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_data_fsm_sparse keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_ctrl_fsm_local_esc keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_ctrl_fsm_consistency keymgr_custom_cm 37.190s 2.296ms 50 50 100.00
V2S sec_cm_ctrl_fsm_global_esc keymgr_lc_disable 26.130s 575.579us 50 50 100.00
V2S sec_cm_ctrl_ctr_redun keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_kmac_if_fsm_sparse keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_kmac_if_ctr_redun keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_kmac_if_cmd_ctrl_consistency keymgr_custom_cm 37.190s 2.296ms 50 50 100.00
V2S sec_cm_kmac_if_done_ctrl_consistency keymgr_custom_cm 37.190s 2.296ms 50 50 100.00
V2S sec_cm_reseed_ctr_redun keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_side_load_sel_ctrl_consistency keymgr_custom_cm 37.190s 2.296ms 50 50 100.00
V2S sec_cm_sideload_ctrl_fsm_sparse keymgr_sec_cm 2.770m 12.000ms 5 5 100.00
V2S sec_cm_ctrl_key_integrity keymgr_custom_cm 37.190s 2.296ms 50 50 100.00
V2S TOTAL 165 165 100.00
V3 stress_all_with_rand_reset keymgr_stress_all_with_rand_reset 12.770s 364.741us 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 1094 1110 98.56

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 16 16 13 81.25
V2S 6 6 6 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.87 99.09 98.17 98.70 100.00 99.17 98.38 91.58

Failure Buckets

Past Results