KEYMGR Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	43.870s	1.986ms	50	50	100.00
V1	random	keymgr_random	1.710m	10.741ms	49	50	98.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.430s	206.984us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.400s	91.032us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	25.980s	3.912ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	13.160s	744.083us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	6.910s	850.954us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.400s	91.032us	20	20	100.00
		keymgr_csr_aliasing	13.160s	744.083us	5	5	100.00
V1		TOTAL			153	155	98.71
V2	cfgen_during_op	keymgr_cfg_regwen	1.895m	7.948ms	50	50	100.00
V2	sideload	keymgr_sideload	56.590s	15.362ms	50	50	100.00
		keymgr_sideload_kmac	57.630s	34.623ms	50	50	100.00
		keymgr_sideload_aes	1.333m	3.967ms	50	50	100.00
		keymgr_sideload_otbn	45.870s	4.384ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	24.110s	893.297us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	22.150s	2.454ms	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	38.730s	17.581ms	47	50	94.00
V2	invalid_sw_input	keymgr_sw_invalid_input	57.580s	22.442ms	49	50	98.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.033m	13.764ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	32.140s	5.080ms	50	50	100.00
V2	stress_all	keymgr_stress_all	11.943m	24.784ms	49	50	98.00
V2	intr_test	keymgr_intr_test	1.040s	24.919us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.070s	221.229us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.660s	340.658us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.660s	340.658us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.430s	206.984us	5	5	100.00
		keymgr_csr_rw	1.400s	91.032us	20	20	100.00
		keymgr_csr_aliasing	13.160s	744.083us	5	5	100.00
		keymgr_same_csr_outstanding	4.070s	120.427us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.430s	206.984us	5	5	100.00
		keymgr_csr_rw	1.400s	91.032us	20	20	100.00
		keymgr_csr_aliasing	13.160s	744.083us	5	5	100.00
		keymgr_same_csr_outstanding	4.070s	120.427us	20	20	100.00
V2		TOTAL			735	740	99.32
V2S	sec_cm_additional_check	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
		keymgr_tl_intg_err	25.400s	10.346ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	17.710s	1.665ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	17.710s	1.665ms	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	17.710s	1.665ms	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	17.710s	1.665ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.900s	489.095us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	25.400s	10.346ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	17.710s	1.665ms	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.895m	7.948ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.710m	10.741ms	49	50	98.00
		keymgr_csr_rw	1.400s	91.032us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.710m	10.741ms	49	50	98.00
		keymgr_csr_rw	1.400s	91.032us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.710m	10.741ms	49	50	98.00
		keymgr_csr_rw	1.400s	91.032us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	22.150s	2.454ms	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.033m	13.764ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.033m	13.764ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.710m	10.741ms	49	50	98.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	23.680s	744.289us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	1.267m	4.501ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	22.150s	2.454ms	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	1.267m	4.501ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	1.267m	4.501ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	1.267m	4.501ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	59.720s	3.928ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	1.267m	4.501ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	29.390s	675.169us	7	50	14.00
V3		TOTAL			7	50	14.00
		TOTAL			1060	1110	95.50

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.82	99.07	98.14	98.44	100.00	99.11	98.41	91.56

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:756) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 26 failures:
- Test keymgr_stress_all_with_rand_reset has 25 failures.
  - 3.keymgr_stress_all_with_rand_reset.100731357741803187040716923721559544599497129448815093749399072453138103945058
    Line 1164, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1513614637 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 1513614637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.keymgr_stress_all_with_rand_reset.104681199021660172981795862312099211291171999723493422381228094348338391605484
    Line 424, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2435498825 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 2435498825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 23 more failures.
- Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.keymgr_csr_mem_rw_with_rand_reset.21781212488206446878971248268500549035376406406597849715487541031773358211316
    Line 259, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 865869368 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 865869368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:714) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 12 failures:
- Test keymgr_stress_all_with_rand_reset has 12 failures.
  - 0.keymgr_stress_all_with_rand_reset.6835080534444307702733532498995589862872366519755395385425764207703681296608
    Line 690, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 314357541 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 314357541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.keymgr_stress_all_with_rand_reset.57361559524512499776237402374492732725785317071766870209891090440057674617444
    Line 1337, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 774802088 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 774802088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

Test keymgr_kmac_rsp_err has 2 failures.

0.keymgr_kmac_rsp_err.91006065450928866965641108789909677490337971781982139667846149657826515206716
Line 327, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @   4059154 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   4059154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.keymgr_kmac_rsp_err.82369624943578397475441396971662673171466377544619547420915253433344729212703
Line 680, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 495139285 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 495139285 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_random has 1 failures.

9.keymgr_random.82645859648756246639218112601039054212382946732021778262743986708086976791819
Line 262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_random/latest/run.log

  UVM_ERROR @   5219747 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   5219747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test keymgr_sw_invalid_input has 1 failures.

36.keymgr_sw_invalid_input.55792688282142077315468455174887096065573511488614123024292979437278905280009
Line 356, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest/run.log

  UVM_ERROR @  18901120 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  18901120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:1011) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation has 3 failures:

Test keymgr_stress_all_with_rand_reset has 3 failures.

10.keymgr_stress_all_with_rand_reset.59230705534344855261445944010089208304672163421870619134222057623444273276153
Line 1553, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 883384637 ps: (keymgr_scoreboard.sv:1011) [uvm_test_top.env.scoreboard] Check failed act == exp (11267637390845699660378274582263380748707426593314761719354226075724326621306093799207645445389674389533750663425609483388731371173861299916652126686782872410041478416816505916369567522195231173070877548462882126153023844825461944191348411440263554321368423857920887111711999790073948748354091320672183850229050722432465037899337195918303539415496634213824118998675733796840578183981944 [0x8a92ab140000000000000000000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 9504437157466433465467245968296009867988307632722005588751025032658358574246695227227855712897859288508935479006744318678043211977232150660234114478307738393944296166491449306187296588743098964811593745655484712186840018698094873898098746925822169173961645099436928742912741822033339905647519211028685326022114051951241264156384442552401162781081144635029278402856289020550126591667064 [0x74e3771700000000cbb94bb6000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

14.keymgr_stress_all_with_rand_reset.24066113263743441756383585093221616692435784577053175736871066413020562777605
Line 776, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/14.keymgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 128619902 ps: (keymgr_scoreboard.sv:1011) [uvm_test_top.env.scoreboard] Check failed act == exp (130304229852036302105583530939269486606806240259318656239208631127423345041228108291143161120751595427467920074164467011625299072318174907735077042325301219419289132151791311979000027556833483950120592410199138746972441632336824477501039388836262337055540148455973292520505462818496989152970658525902080327301673333561890295497208086185150276347490191769993312461049514868200144710945749082463255296085507 [0x56df763500000000000000000000000021a18eb9000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9bd2c5c3a4c3a9a71504c6b67fce1caeafb27e7f384b9de25ab3cfc2046ac217999b23e4e3cc00b4b7d5bfd7e6f54a8fcdb97025132ed9898c192e760cb376a2c0212a3458b7860d2449213494438ba43b5c2fbeb1e6b716164136e1a107cc0b3ddcb7ae2113b71ce657385c961260e03] vs 245763463011866391524462442337348787991868181347174442708832616701792011510763386073287375629736363988426731158321627775091398821730131785302812770642566202195387754317553016363707205417977941408906391121303787289001719660607271829529120378315542747913587524314074115554173993311722393737490829933067855009681811850391660954601881042198214628275412839732074688941571 [0x37c13d0b000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9bd2c5c3a4c3a9a71504c6b67fce1caeafb27e7f384b9de25ab3cfc2046ac217999b23e4e3cc00b4b7d5bfd7e6f54a8fcdb97025132ed9898c192e760cb376a2c0212a3458b7860d2449213494438ba43b5c2fbeb1e6b716164136e1a107cc0b3ddcb7ae2113b71ce657385c961260e03]) cdi_type: Attestation
  
   DiversificationKey act: 0xb5c2fbeb1e6b716164136e1a107cc0b3ddcb7ae2113b71ce657385c961260e03, exp: 0xb5c2fbeb1e6b716164136e1a107cc0b3ddcb7ae2113b71ce657385c961260e03
   RomDigest act: 0xdb97025132ed9898c192e760cb376a2c0212a3458b7860d2449213494438ba43, exp: 0xdb97025132ed9898c192e760cb376a2c0212a3458b7860d2449213494438ba43
   HealthMeasurement act: 0x99b23e4e3cc00b4b7d5bfd7e6f54a8fc, exp: 0x99b23e4e3cc00b4b7d5bfd7e6f54a8fc

... and 1 more failures.

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 2 failures:
- Test keymgr_stress_all_with_rand_reset has 2 failures.
  - 15.keymgr_stress_all_with_rand_reset.1785095006133555779793414135100912693283323273196250490460032650695457853720
    Line 592, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 569791090 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1846324445 [0x6e0cacdd] vs 1846324445 [0x6e0cacdd])
  UVM_INFO @ 569791090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.keymgr_stress_all_with_rand_reset.60227986253849102713884533218268209645711288686054027367406510142083335734060
    Line 693, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 106419355 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1752577221 [0x687634c5] vs 1752577221 [0x687634c5])
  UVM_INFO @ 106419355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 3.keymgr_stress_all.49517496686153794566655055246003507284176835228480181610408974630753210710470
    Line 1482, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 481958544 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (2280508966 [0x87edce26] vs 3791558401 [0xe1fe9701]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @ 481958544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:674) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 20.keymgr_stress_all_with_rand_reset.341534842028529787897355426484655799099034117721749575957250181946658561732
    Line 892, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 719022132 ps: (keymgr_scoreboard.sv:674) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 719022132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 1 failures:

Test keymgr_kmac_rsp_err has 1 failures.

26.keymgr_kmac_rsp_err.30391434492154558563482567497088439261892195587635945204186659728094585508190
Line 411, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  88988538 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (68716882848428863595364098325150073109908731835825260168961015401563872381118497081173046097803590293038729289282771931394897211173636252129775928556912982143537677103780324112014277059864321972781523418870894786412733568632663877727671691859307299166887516348650150083333485846383620763251680219850675844971230512739312132450774543843071207612267265562528911788866573295720854591419751059629538 [0xc4c3fc4d97ae8b4e000000006326562e000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d163929dd2776d32c97f442f3b51dc197832ecc5c04247caa685f79ed1851ad587c3b33ec91d6d318f37043182a0155ed246a79562fddf70fd8b0c0b2ff1662a1d2ed6c4b4d3899c82890940ca4df5503b392ad28419fa894948643f3ba33a610abccad07ee428c97c3c324027a725e2] vs 68716882848428863595364098325150073109908731835825260168961015401563872381118497081173046097803590293038729289282771931394897211173636252129775928556912982143537677103780324112014277059864321972781523418870894786412733568632663877727671691859307299166887516348650150083333485846383620763251680219850675844971230512739312132450774543843071207612267265562528911788866573295720854591419751059629538 [0xc4c3fc4d97ae8b4e000000006326562e000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9d163929dd2776d32c97f442f3b51dc197832ecc5c04247caa685f79ed1851ad587c3b33ec91d6d318f37043182a0155ed246a79562fddf70fd8b0c0b2ff1662a1d2ed6c4b4d3899c82890940ca4df5503b392ad28419fa894948643f3ba33a610abccad07ee428c97c3c324027a725e2]) cdi_type: Attestation
  
   DiversificationKey act: 0x3b392ad28419fa894948643f3ba33a610abccad07ee428c97c3c324027a725e2, exp: 0x3b392ad28419fa894948643f3ba33a610abccad07ee428c97c3c324027a725e2
   RomDigest act: 0xd246a79562fddf70fd8b0c0b2ff1662a1d2ed6c4b4d3899c82890940ca4df550, exp: 0xd246a79562fddf70fd8b0c0b2ff1662a1d2ed6c4b4d3899c82890940ca4df550
   HealthMeasurement act: 0x87c3b33ec91d6d318f37043182a0155e, exp: 0x87c3b33ec91d6d318f37043182a0155e