KEYMGR Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	40.080s	1.848ms	50	50	100.00
V1	random	keymgr_random	54.960s	2.746ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.140s	41.823us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.460s	45.485us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	17.630s	669.719us	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	14.180s	2.395ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.810s	154.907us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.460s	45.485us	20	20	100.00
		keymgr_csr_aliasing	14.180s	2.395ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	2.033m	4.627ms	50	50	100.00
V2	sideload	keymgr_sideload	1.175m	3.608ms	50	50	100.00
		keymgr_sideload_kmac	1.004m	6.069ms	50	50	100.00
		keymgr_sideload_aes	1.648m	15.435ms	50	50	100.00
		keymgr_sideload_otbn	36.820s	1.585ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	29.090s	5.090ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	51.670s	1.684ms	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	1.226m	2.586ms	45	50	90.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.549m	11.151ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	56.050s	6.660ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	33.210s	3.837ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.179m	18.949ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.920s	60.003us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.060s	86.278us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.280s	128.929us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.280s	128.929us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.140s	41.823us	5	5	100.00
		keymgr_csr_rw	1.460s	45.485us	20	20	100.00
		keymgr_csr_aliasing	14.180s	2.395ms	5	5	100.00
		keymgr_same_csr_outstanding	3.970s	124.263us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.140s	41.823us	5	5	100.00
		keymgr_csr_rw	1.460s	45.485us	20	20	100.00
		keymgr_csr_aliasing	14.180s	2.395ms	5	5	100.00
		keymgr_same_csr_outstanding	3.970s	124.263us	20	20	100.00
V2		TOTAL			732	740	98.92
V2S	sec_cm_additional_check	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
		keymgr_tl_intg_err	47.920s	1.920ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	12.040s	892.834us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	12.040s	892.834us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	12.040s	892.834us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	12.040s	892.834us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.710s	456.564us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	47.920s	1.920ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	12.040s	892.834us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	2.033m	4.627ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	54.960s	2.746ms	50	50	100.00
		keymgr_csr_rw	1.460s	45.485us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	54.960s	2.746ms	50	50	100.00
		keymgr_csr_rw	1.460s	45.485us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	54.960s	2.746ms	50	50	100.00
		keymgr_csr_rw	1.460s	45.485us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	51.670s	1.684ms	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	56.050s	6.660ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	56.050s	6.660ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	54.960s	2.746ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	45.460s	1.663ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	53.550s	2.444ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	51.670s	1.684ms	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	53.550s	2.444ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	53.550s	2.444ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	53.550s	2.444ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	5.596m	32.792ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	53.550s	2.444ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	35.360s	3.100ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1074	1110	96.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.84	99.07	98.06	98.57	100.00	99.11	98.41	91.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 0.keymgr_stress_all_with_rand_reset.29612135711242920698547323620640214997143015448221684318540668483630183413100
    Line 379, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 433979489 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 433979489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.keymgr_stress_all_with_rand_reset.114828204766401247670573169618641542706735670987181395982408842401091764186496
    Line 761, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 564541772 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 564541772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.

UVM_ERROR (keymgr_scoreboard.sv:1013) [scoreboard] Check failed act != exp (* [*] vs * [*]) cdi_type: Attestation has 5 failures:

Test keymgr_kmac_rsp_err has 5 failures.

3.keymgr_kmac_rsp_err.95748343163645743741812749090887353233065703604904819658829805988650563678386
Line 345, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @ 171722749 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (2153346374136851125046387189344560674998558181447906081806625189798177488324770271448604866626440391127839379420335258614205740128210117772834728267603737126109767773701554680168703033206722355939642014343551601085588041372865924269606698294936837803755953236142883339957953210580469260724154394039434388359112533312315062329948786395869012222983841771765081991738467041465953086880472549495106246524669523707940485209910136 [0x4dd33d00000000000000000000000000000000000000000000000000d206662d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 2153346374136851125046387189344560674998558181447906081806625189798177488324770271448604866626440391127839379420335258614205740128210117772834728267603737126109767773701554680168703033206722355939642014343551601085588041372865924269606698294936837803755953236142883339957953210580469260724154394039434388359112533312315062329948786395869012222983841771765081991738467041465953086880472549495106246524669523707940485209910136 [0x4dd33d00000000000000000000000000000000000000000000000000d206662d3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

12.keymgr_kmac_rsp_err.18030540986575215385630900228022425300257311740247732168162734994517524942213
Line 335, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest/run.log

  UVM_ERROR @  89121171 ps: (keymgr_scoreboard.sv:1013) [uvm_test_top.env.scoreboard] Check failed act != exp (20417067398094464743405749527074008632209398504893570398975873898765370804171870951801184882539431679474703258763781794984456774509663627648250492945665290810006169695819962810222145548085991328216083533812612568795007387571399292519262540522863533663177593716103768438669629094184950160665298935487208936962635748666129696006206953192623163629154813812988022340490389997529572210946234186853240 [0x3a7674cffdb35b58e71311b3ab3b42f4000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78] vs 20417067398094464743405749527074008632209398504893570398975873898765370804171870951801184882539431679474703258763781794984456774509663627648250492945665290810006169695819962810222145548085991328216083533812612568795007387571399292519262540522863533663177593716103768438669629094184950160665298935487208936962635748666129696006206953192623163629154813812988022340490389997529572210946234186853240 [0x3a7674cffdb35b58e71311b3ab3b42f4000000003a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f9000000000000000000000000000000000000000000000000000000000000f0f000000000000000005cfbd765ce33f34ea20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507fa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78]) cdi_type: Attestation
  
   DiversificationKey act: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78, exp: 0xfa365df52da48cd752fb3a026a8e608f0098cfe5fa9810494829d0cd9479eb78
   RomDigest act: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507, exp: 0xa20a046cf42e6eac560a3f82bfa76285b5c1d4aea7c915e49a32d1c89be0f507
   HealthMeasurement act: 0x5cfbd765ce33f34e, exp: 0x5cfbd765ce33f34e

... and 3 more failures.

UVM_ERROR (keymgr_scoreboard.sv:736) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * [])` has 3 failures:
- Test keymgr_stress_all_with_rand_reset has 3 failures.
  - 18.keymgr_stress_all_with_rand_reset.46897622283950673883218998680602576797907771312744532444552320492177422257478
    Line 1473, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 183499426 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (4219459959 [0xfb7fd977] vs 4219459959 [0xfb7fd977])
  UVM_INFO @ 183499426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.keymgr_stress_all_with_rand_reset.115552415156304455821476968126642499348326852760643483635776073863972010721266
    Line 2717, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/31.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 280988778 ps: (keymgr_scoreboard.sv:736) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (1329710437 [0x4f41c565] vs 1329710437 [0x4f41c565])
  UVM_INFO @ 280988778 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_stress_all has 2 failures.
  - 30.keymgr_stress_all.114569451489582835700948190401449295172870364442881921027925869674239696623877
    Line 2282, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/30.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 4633031902 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 4633031902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.keymgr_stress_all.90305843706186648469176931869894245854370398394319880172909692427970455858286
    Line 273, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/38.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @   9122890 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   9122890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:750) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 15.keymgr_lc_disable.85195403230122734628058778226273399957056427342806260796921440680299261299936
    Line 354, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/15.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  59392184 ps: (keymgr_scoreboard.sv:750) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (3924706522 [0xe9ee44da] vs 3816741441 [0xe37eda41]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @  59392184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:753) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 42.keymgr_stress_all_with_rand_reset.86700097361439407992577565445461728431865357719233406028821507827162350773790
    Line 491, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 124287442 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 124287442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```