18c8953cf1
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | keymgr_smoke | 42.830s | 36.046ms | 50 | 50 | 100.00 |
V1 | random | keymgr_random | 1.714m | 9.795ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | keymgr_csr_hw_reset | 1.530s | 40.060us | 5 | 5 | 100.00 |
V1 | csr_rw | keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | keymgr_csr_bit_bash | 18.960s | 5.338ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | keymgr_csr_aliasing | 9.660s | 730.464us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | keymgr_csr_mem_rw_with_rand_reset | 2.690s | 85.772us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 |
keymgr_csr_aliasing | 9.660s | 730.464us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | cfgen_during_op | keymgr_cfg_regwen | 1.850m | 2.217ms | 50 | 50 | 100.00 |
V2 | sideload | keymgr_sideload | 51.090s | 10.283ms | 50 | 50 | 100.00 |
keymgr_sideload_kmac | 46.750s | 7.196ms | 49 | 50 | 98.00 | ||
keymgr_sideload_aes | 59.010s | 6.265ms | 50 | 50 | 100.00 | ||
keymgr_sideload_otbn | 1.244m | 10.187ms | 50 | 50 | 100.00 | ||
V2 | direct_to_disabled_state | keymgr_direct_to_disabled | 18.910s | 1.263ms | 50 | 50 | 100.00 |
V2 | lc_disable | keymgr_lc_disable | 8.690s | 343.602us | 49 | 50 | 98.00 |
V2 | kmac_error_response | keymgr_kmac_rsp_err | 6.190s | 138.752us | 50 | 50 | 100.00 |
V2 | invalid_sw_input | keymgr_sw_invalid_input | 50.500s | 2.028ms | 50 | 50 | 100.00 |
V2 | invalid_hw_input | keymgr_hwsw_invalid_input | 29.220s | 1.721ms | 49 | 50 | 98.00 |
V2 | sync_async_fault_cross | keymgr_sync_async_fault_cross | 19.310s | 1.285ms | 50 | 50 | 100.00 |
V2 | stress_all | keymgr_stress_all | 6.062m | 13.380ms | 48 | 50 | 96.00 |
V2 | intr_test | keymgr_intr_test | 0.970s | 22.546us | 50 | 50 | 100.00 |
V2 | alert_test | keymgr_alert_test | 1.030s | 134.763us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | keymgr_tl_errors | 4.330s | 649.165us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | keymgr_tl_errors | 4.330s | 649.165us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | keymgr_csr_hw_reset | 1.530s | 40.060us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.660s | 730.464us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 5.460s | 1.664ms | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | keymgr_csr_hw_reset | 1.530s | 40.060us | 5 | 5 | 100.00 |
keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 | ||
keymgr_csr_aliasing | 9.660s | 730.464us | 5 | 5 | 100.00 | ||
keymgr_same_csr_outstanding | 5.460s | 1.664ms | 20 | 20 | 100.00 | ||
V2 | TOTAL | 735 | 740 | 99.32 | |||
V2S | sec_cm_additional_check | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | tl_intg_err | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
keymgr_tl_intg_err | 12.940s | 584.365us | 20 | 20 | 100.00 | ||
V2S | shadow_reg_update_error | keymgr_shadow_reg_errors | 5.320s | 726.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | keymgr_shadow_reg_errors | 5.320s | 726.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | keymgr_shadow_reg_errors | 5.320s | 726.799us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | keymgr_shadow_reg_errors | 5.320s | 726.799us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | keymgr_shadow_reg_errors_with_csr_rw | 14.850s | 1.651ms | 20 | 20 | 100.00 |
V2S | prim_count_check | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | prim_fsm_check | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_bus_integrity | keymgr_tl_intg_err | 12.940s | 584.365us | 20 | 20 | 100.00 |
V2S | sec_cm_config_shadow | keymgr_shadow_reg_errors | 5.320s | 726.799us | 20 | 20 | 100.00 |
V2S | sec_cm_op_config_regwen | keymgr_cfg_regwen | 1.850m | 2.217ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_config_regwen | keymgr_random | 1.714m | 9.795ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 | ||
V2S | sec_cm_sw_binding_config_regwen | keymgr_random | 1.714m | 9.795ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 | ||
V2S | sec_cm_max_key_ver_config_regwen | keymgr_random | 1.714m | 9.795ms | 50 | 50 | 100.00 |
keymgr_csr_rw | 1.540s | 26.720us | 20 | 20 | 100.00 | ||
V2S | sec_cm_lc_ctrl_intersig_mubi | keymgr_lc_disable | 8.690s | 343.602us | 49 | 50 | 98.00 |
V2S | sec_cm_constants_consistency | keymgr_hwsw_invalid_input | 29.220s | 1.721ms | 49 | 50 | 98.00 |
V2S | sec_cm_intersig_consistency | keymgr_hwsw_invalid_input | 29.220s | 1.721ms | 49 | 50 | 98.00 |
V2S | sec_cm_hw_key_sw_noaccess | keymgr_random | 1.714m | 9.795ms | 50 | 50 | 100.00 |
V2S | sec_cm_output_keys_ctrl_redun | keymgr_sideload_protect | 15.220s | 2.275ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_sparse | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_data_fsm_sparse | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_local_esc | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_fsm_consistency | keymgr_custom_cm | 36.520s | 6.742ms | 50 | 50 | 100.00 |
V2S | sec_cm_ctrl_fsm_global_esc | keymgr_lc_disable | 8.690s | 343.602us | 49 | 50 | 98.00 |
V2S | sec_cm_ctrl_ctr_redun | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_fsm_sparse | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_ctr_redun | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_kmac_if_cmd_ctrl_consistency | keymgr_custom_cm | 36.520s | 6.742ms | 50 | 50 | 100.00 |
V2S | sec_cm_kmac_if_done_ctrl_consistency | keymgr_custom_cm | 36.520s | 6.742ms | 50 | 50 | 100.00 |
V2S | sec_cm_reseed_ctr_redun | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_side_load_sel_ctrl_consistency | keymgr_custom_cm | 36.520s | 6.742ms | 50 | 50 | 100.00 |
V2S | sec_cm_sideload_ctrl_fsm_sparse | keymgr_sec_cm | 13.990s | 1.018ms | 5 | 5 | 100.00 |
V2S | sec_cm_ctrl_key_integrity | keymgr_custom_cm | 36.520s | 6.742ms | 50 | 50 | 100.00 |
V2S | TOTAL | 165 | 165 | 100.00 | |||
V3 | stress_all_with_rand_reset | keymgr_stress_all_with_rand_reset | 26.960s | 1.709ms | 30 | 50 | 60.00 |
V3 | TOTAL | 30 | 50 | 60.00 | |||
TOTAL | 1085 | 1110 | 97.75 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 16 | 16 | 12 | 75.00 |
V2S | 6 | 6 | 6 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
97.71 | 99.03 | 98.07 | 98.28 | 100.00 | 99.02 | 98.41 | 91.14 |
UVM_ERROR (cip_base_vseq.sv:829) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 19 failures:
4.keymgr_stress_all_with_rand_reset.60274390064445113128248842512111236954166030745846554135587919566014416751024
Line 349, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 921697709 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 921697709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.keymgr_stress_all_with_rand_reset.81390408886977836455611815147146408816084247822747172219370463864176582345561
Line 745, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 921608804 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 921608804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
has 1 failures:
7.keymgr_sideload_kmac.47218550592973530186718035759717279115293918352600601924371235922409200289006
Line 386, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest/run.log
UVM_ERROR @ 19990377 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
UVM_INFO @ 19990377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:1066) [scoreboard] Check failed act == exp (* [*] vs * [*]) cdi_type: Attestation
has 1 failures:
10.keymgr_stress_all_with_rand_reset.71915158864031809137266993048742123806232245678452301929343589715081833760488
Line 1092, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/10.keymgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 242604072 ps: (keymgr_scoreboard.sv:1066) [uvm_test_top.env.scoreboard] Check failed act == exp (2351665575270764317028289832379499132715860323932351663261752090144377249348447619722735977029351127359220348155062265440494475684647276771544775782690237539306994790476943038280334026017637505088495794888848152019165197700009709555856965768465506966555392244785022806644528039335196744847828650818747510239150348953287096185856196532433956633498057093297951224322165658594079977236377250120377443245774312249888074042345084 [0x54fe21ab36c856232edbcd3e9e119c0e018d9a3c4e738829983bf370a33324ca3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f94012b33f3d3fa1276288490ae811ec156dc2230ff164311a9245f463e332e095c6e2b7c844d34569e3e635214cbeef68cfa7e3eab2cee0b1f4b5f4f12db03eb15f2c66a0f5246cf61f3aace935027fc78308449855fda2dc5b32cf53eed3c819a7b94c4003b18d06089e72ad0586867c] vs 2998863261224040857588995359570255250044155534096933817240656872097749331520990287276629888778934979404624745192666125615729192328477062591275834641857474498308574890443776679159678635892158554864104509380189456803805669002526229800226574828512121844759545518852978185062777417720649256675982518826873845807919943731616759440598377847414490665639060289254948811025073533172087331148972699286669534679375444161597312910919292 [0x6c6225e769764b09751735b9fea28d7eaadea34ee74780b7b3cb6a2e957a71af3a0a6d73cd50897de4d744bd65ebdb3837ea77087d878651c517c18a5742b2f94012b33f3d3fa1276288490ae811ec156dc2230ff164311a9245f463e332e095c6e2b7c844d34569e3e635214cbeef68cfa7e3eab2cee0b1f4b5f4f12db03eb15f2c66a0f5246cf61f3aace935027fc78308449855fda2dc5b32cf53eed3c819a7b94c4003b18d06089e72ad0586867c]) cdi_type: Attestation
DiversificationKey act: 0x8308449855fda2dc5b32cf53eed3c819a7b94c4003b18d06089e72ad0586867c, exp: 0x8308449855fda2dc5b32cf53eed3c819a7b94c4003b18d06089e72ad0586867c
RomDigest act: 0xcfa7e3eab2cee0b1f4b5f4f12db03eb15f2c66a0f5246cf61f3aace935027fc7, exp: 0xcfa7e3eab2cee0b1f4b5f4f12db03eb15f2c66a0f5246cf61f3aace935027fc7
HealthMeasurement act: 0xc6e2b7c844d34569e3e635214cbeef68, exp: 0xc6e2b7c844d34569e3e635214cbeef68
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly
has 1 failures:
12.keymgr_hwsw_invalid_input.97049843485113903698318352299114366429611230276703608174057628184186986841154
Line 808, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest/run.log
UVM_ERROR @ 24150063 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
UVM_INFO @ 24150063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:651) [scoreboard] Check failed act_state == addr_phase_working_state (* [*] vs * [*])
has 1 failures:
32.keymgr_stress_all.90066500998909505351686388818504626208324970261747836198501582613502671245919
Line 1406, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_stress_all/latest/run.log
UVM_ERROR @ 1240662470 ps: (keymgr_scoreboard.sv:651) [uvm_test_top.env.scoreboard] Check failed act_state == addr_phase_working_state (2 [0x2] vs 6 [0x6])
UVM_INFO @ 1240662470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Sealing Aes
has 1 failures:
48.keymgr_lc_disable.54172540225317697681042213386777450960620754068374023450675895071597528045493
Line 620, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_lc_disable/latest/run.log
UVM_ERROR @ 66018010 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (8918865452972167706880369995495150965852626216465257056452849475836438504475691187038218375329014030563606265900778651279246610002035229092267700654825798 [0xaa4a819841dea4ae519eee0a133c68c929be7dc25700b79ceb013f205ba9a0bdf06249e6c1d8a7e10e1823b2a6c3f2aadb479fac038a8634701d8e69e019e146] vs 8918865452972167706880369995495150965852626216465257056452849475836438504475691187038218375329014030563606265900778651279246610002035229092267700654825798 [0xaa4a819841dea4ae519eee0a133c68c929be7dc25700b79ceb013f205ba9a0bdf06249e6c1d8a7e10e1823b2a6c3f2aadb479fac038a8634701d8e69e019e146]) AES key at state StOwnerKey for Sealing Aes
UVM_INFO @ 66018010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=
gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
48.keymgr_stress_all.109561372505701162061221610291388958614845131410796630845073224162668637110370
Line 935, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/48.keymgr_stress_all/latest/run.log
UVM_ERROR @ 423071029 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_6
UVM_INFO @ 423071029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---