KEYMGR Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	37.320s	2.485ms	50	50	100.00
V1	random	keymgr_random	34.470s	1.066ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.170s	14.679us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.650s	28.974us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	14.600s	1.003ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.500s	1.011ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.490s	69.197us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.650s	28.974us	20	20	100.00
		keymgr_csr_aliasing	15.500s	1.011ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.076m	4.972ms	50	50	100.00
V2	sideload	keymgr_sideload	1.102m	3.366ms	50	50	100.00
		keymgr_sideload_kmac	40.270s	12.035ms	50	50	100.00
		keymgr_sideload_aes	53.920s	1.667ms	50	50	100.00
		keymgr_sideload_otbn	59.030s	3.468ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	13.940s	1.777ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	32.160s	670.606us	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	10.940s	2.692ms	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	45.660s	24.411ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	53.940s	19.655ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.360s	637.231us	48	50	96.00
V2	stress_all	keymgr_stress_all	8.137m	53.970ms	47	50	94.00
V2	intr_test	keymgr_intr_test	0.910s	21.840us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.010s	18.293us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	6.040s	1.440ms	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	6.040s	1.440ms	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.170s	14.679us	5	5	100.00
		keymgr_csr_rw	1.650s	28.974us	20	20	100.00
		keymgr_csr_aliasing	15.500s	1.011ms	5	5	100.00
		keymgr_same_csr_outstanding	3.680s	108.240us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.170s	14.679us	5	5	100.00
		keymgr_csr_rw	1.650s	28.974us	20	20	100.00
		keymgr_csr_aliasing	15.500s	1.011ms	5	5	100.00
		keymgr_same_csr_outstanding	3.680s	108.240us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
		keymgr_tl_intg_err	9.480s	322.944us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.210s	208.944us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.210s	208.944us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.210s	208.944us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.210s	208.944us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	17.020s	548.656us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	9.480s	322.944us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.210s	208.944us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.076m	4.972ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	34.470s	1.066ms	50	50	100.00
		keymgr_csr_rw	1.650s	28.974us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	34.470s	1.066ms	50	50	100.00
		keymgr_csr_rw	1.650s	28.974us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	34.470s	1.066ms	50	50	100.00
		keymgr_csr_rw	1.650s	28.974us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	32.160s	670.606us	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	53.940s	19.655ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	53.940s	19.655ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	34.470s	1.066ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	29.100s	1.973ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	36.060s	4.494ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	32.160s	670.606us	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	36.060s	4.494ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	36.060s	4.494ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	36.060s	4.494ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	15.350s	518.866us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	36.060s	4.494ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	23.280s	664.743us	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.71	99.04	98.11	98.32	100.00	99.02	98.41	91.09

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:
- Test keymgr_stress_all_with_rand_reset has 17 failures.
  - 1.keymgr_stress_all_with_rand_reset.23893566323265346191212342066452566226838755144724520114027465194724647763705
    Line 620, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 150957089 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 150957089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.keymgr_stress_all_with_rand_reset.42280504226935748559422094919601205638125366263532441683217759335929297677140
    Line 493, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 137396203 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 137396203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 2 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 0.keymgr_sync_async_fault_cross.51109308965644591493279096030737761595115543995398561933761127508591772796821
    Line 274, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @   3970354 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   3970354 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all has 1 failures.
  - 9.keymgr_stress_all.5921520875681998595622243336979009394565569389557304423895731669251439939062
    Line 274, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @  13959924 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  13959924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 11.keymgr_stress_all.23410623148942868799760986414980299106556321001434815298287818896093619235290
    Line 2451, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 3978328623 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_5
  UVM_INFO @ 3978328623 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_sync_async_fault_cross_vseq.sv:38) [keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] || act_fault_status[keymgr_pkg::FaultKmacOut] == * (* [*] vs * [*]) has 1 failures:
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 13.keymgr_sync_async_fault_cross.23497389141435033160700298825263914716318706769453716873905212107522009582918
    Line 288, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  77121859 ps: (keymgr_sync_async_fault_cross_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.keymgr_sync_async_fault_cross_vseq] Check failed act_fault_status[keymgr_pkg::FaultKmacOp] ||                 act_fault_status[keymgr_pkg::FaultKmacOut] == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  77121859 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:755) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 13.keymgr_stress_all_with_rand_reset.16789439919039573678116528829464638639045702383592415675135871024233382733877
    Line 275, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/13.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 119184773 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 119184773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 19.keymgr_lc_disable.101856984855965756978089317675937010015712992126986081005313878454365464762601
    Line 319, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @ 114377000 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2243270431 [0x85b5971f] vs 2243270431 [0x85b5971f]) reg name: keymgr_reg_block.sw_share0_output_7
  UVM_INFO @ 114377000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 22.keymgr_stress_all_with_rand_reset.79919028392048269950780032483584309321729914024847652976075112998396990669475
    Line 494, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 518437688 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 2 [0x2])
  UVM_INFO @ 518437688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StDisabled for Attestation Kmac has 1 failures:

Test keymgr_stress_all has 1 failures.

37.keymgr_stress_all.28794863999318734244416878885745764686274866013192292854161696739867617501242
Line 1168, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/37.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 307271546 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9873929450477303225235431701946631779139690215077460459188753068764573251376673922168655990362422435774530385589553665443947869893305996988938099469196733 [0xbc86c305bba5178728324d4f0b03a36ed26b25c6f142e506dad77fa61aa16379721a45514bc9c73b119bf2f56d9a0f5c7363306c43b13968d50f503e9e661dbd] vs 9873929450477303225235431701946631779139690215077460459188753068764573251376673922168655990362422435774530385589553665443947869893305996988938099469196733 [0xbc86c305bba5178728324d4f0b03a36ed26b25c6f142e506dad77fa61aa16379721a45514bc9c73b119bf2f56d9a0f5c7363306c43b13968d50f503e9e661dbd]) KMAC key at state StDisabled for Attestation Kmac
  UVM_INFO @ 307271546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

49.keymgr_lc_disable.7097684196166292318494522342077160684338875729070469737656281395153398524228
Line 445, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/49.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  60541668 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (9262210974610757644620712421393636092320007872248716792582868187958423366595258134862505504395468890103198937715104634986150945246139701847049903065219611 [0xb0d8be829b23c673feb634e25c588dda557f3377f76cc37dc2f1dc92fe730310e31a55017b0651f7f7a559a3e4dc76eb10fd19ce6f0486a4a011ce59feef421b] vs 9262210974610757644620712421393636092320007872248716792582868187958423366595258134862505504395468890103198937715104634986150945246139701847049903065219611 [0xb0d8be829b23c673feb634e25c588dda557f3377f76cc37dc2f1dc92fe730310e31a55017b0651f7f7a559a3e4dc76eb10fd19ce6f0486a4a011ce59feef421b]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @  60541668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---