KEYMGR Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	19.730s	1.301ms	50	50	100.00
V1	random	keymgr_random	1.090m	7.714ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.150s	34.541us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.640s	57.710us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	24.880s	3.424ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	18.260s	987.157us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.650s	73.711us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.640s	57.710us	20	20	100.00
		keymgr_csr_aliasing	18.260s	987.157us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.976m	9.140ms	50	50	100.00
V2	sideload	keymgr_sideload	46.210s	1.437ms	50	50	100.00
		keymgr_sideload_kmac	14.420s	491.264us	50	50	100.00
		keymgr_sideload_aes	39.930s	3.393ms	50	50	100.00
		keymgr_sideload_otbn	40.700s	6.431ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	18.500s	928.966us	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.620s	202.609us	49	50	98.00
V2	kmac_error_response	keymgr_kmac_rsp_err	6.370s	667.129us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	50.690s	7.832ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	45.840s	4.838ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	11.560s	747.448us	50	50	100.00
V2	stress_all	keymgr_stress_all	6.261m	35.640ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.930s	25.849us	50	50	100.00
V2	alert_test	keymgr_alert_test	0.960s	20.117us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.910s	217.745us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.910s	217.745us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.150s	34.541us	5	5	100.00
		keymgr_csr_rw	1.640s	57.710us	20	20	100.00
		keymgr_csr_aliasing	18.260s	987.157us	5	5	100.00
		keymgr_same_csr_outstanding	4.180s	124.904us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.150s	34.541us	5	5	100.00
		keymgr_csr_rw	1.640s	57.710us	20	20	100.00
		keymgr_csr_aliasing	18.260s	987.157us	5	5	100.00
		keymgr_same_csr_outstanding	4.180s	124.904us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
		keymgr_tl_intg_err	10.670s	1.080ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.710s	216.420us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.710s	216.420us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.710s	216.420us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.710s	216.420us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	11.950s	1.309ms	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.670s	1.080ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.710s	216.420us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.976m	9.140ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.090m	7.714ms	50	50	100.00
		keymgr_csr_rw	1.640s	57.710us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.090m	7.714ms	50	50	100.00
		keymgr_csr_rw	1.640s	57.710us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.090m	7.714ms	50	50	100.00
		keymgr_csr_rw	1.640s	57.710us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.620s	202.609us	49	50	98.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	45.840s	4.838ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	45.840s	4.838ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.090m	7.714ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	20.720s	1.149ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	7.760s	638.819us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.620s	202.609us	49	50	98.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	7.760s	638.819us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	7.760s	638.819us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	7.760s	638.819us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	19.600s	856.826us	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	7.760s	638.819us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	25.440s	5.521ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1081	1110	97.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.43	99.00	98.11	98.69	97.67	98.93	98.41	91.19

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test keymgr_stress_all_with_rand_reset has 24 failures.
  - 0.keymgr_stress_all_with_rand_reset.6613434325553017173793102611443416853063418319210066354917550370055988623714
    Line 443, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 128604788 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10002 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 128604788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.keymgr_stress_all_with_rand_reset.78363560538219932158283427953834627136850100586641535383108327075690041522742
    Line 576, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 257033497 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 257033497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 9.keymgr_stress_all_with_rand_reset.63852089692716514815339247735880504506265608638293189552177827162769009478967
    Line 688, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/9.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 249007808 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (0 [0x0] vs 0 [0x0]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @ 249007808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StCreatorRootKey for Attestation Aes has 1 failures:

Test keymgr_stress_all has 1 failures.

17.keymgr_stress_all.80668808824325840722586806753026063164223357885564947232198597191305743334754
Line 1538, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/17.keymgr_stress_all/latest/run.log

  UVM_ERROR @ 1549705847 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (373763141133573151876724966290540675253485310666505463507053672100814538085680464832634793231217967423330807553248256026574580199573310161830229320941883 [0x722ea8aa2732d79ffd94be9099fb1ded2cc4734a3d70bee74feae046d4bd18f6fc1189158311d232f44edefe33aacf05cf30e34a8b21ef9bc3b6a21bad0413b] vs 373763141133573151876724966290540675253485310666505463507053672100814538085680464832634793231217967423330807553248256026574580199573310161830229320941883 [0x722ea8aa2732d79ffd94be9099fb1ded2cc4734a3d70bee74feae046d4bd18f6fc1189158311d232f44edefe33aacf05cf30e34a8b21ef9bc3b6a21bad0413b]) AES key at state StCreatorRootKey for Attestation Aes
  UVM_INFO @ 1549705847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share0_output_*` has 1 failures:
- Test keymgr_stress_all has 1 failures.
  - 19.keymgr_stress_all.44328235047360934877949881443480158748392358174224376847733423719815215716730
    Line 1326, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/19.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 554899193 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (2340366998 [0x8b7f2a96] vs 2340366998 [0x8b7f2a96]) reg name: keymgr_reg_block.sw_share0_output_2
  UVM_INFO @ 554899193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerIntKey for Sealing Aes has 1 failures:

Test keymgr_lc_disable has 1 failures.

32.keymgr_lc_disable.112433472602013671316733816753997784897138865680609710702285358000190182483714
Line 614, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/32.keymgr_lc_disable/latest/run.log

  UVM_ERROR @ 452290738 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (11053114454425160546524630877591478808247340895875759487752513472808473135818105602530332306846366057564072043802908982238189162911735385392683326805614075 [0xd30a7f7fbb8a12aae7cf01c71f9e522623ee944e914893f1230d67ea636529ccc86a1f8d8ed605954e758b60bf0b45018ba6a82726fc06f6c9fa9578a53b9dfb] vs 11053114454425160546524630877591478808247340895875759487752513472808473135818105602530332306846366057564072043802908982238189162911735385392683326805614075 [0xd30a7f7fbb8a12aae7cf01c71f9e522623ee944e914893f1230d67ea636529ccc86a1f8d8ed605954e758b60bf0b45018ba6a82726fc06f6c9fa9578a53b9dfb]) AES key at state StOwnerIntKey for Sealing Aes
  UVM_INFO @ 452290738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 46.keymgr_kmac_rsp_err.50682634181008720244824935294523642959759232516966977585250583467490907278760
    Line 391, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  30370967 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  30370967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```