KEYMGR Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	34.100s	2.667ms	50	50	100.00
V1	random	keymgr_random	41.350s	2.566ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.390s	105.308us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.450s	24.893us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.950s	2.668ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	12.080s	3.080ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.470s	206.180us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.450s	24.893us	20	20	100.00
		keymgr_csr_aliasing	12.080s	3.080ms	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.582m	7.050ms	49	50	98.00
V2	sideload	keymgr_sideload	1.187m	3.769ms	50	50	100.00
		keymgr_sideload_kmac	47.350s	4.561ms	50	50	100.00
		keymgr_sideload_aes	54.730s	1.606ms	50	50	100.00
		keymgr_sideload_otbn	40.910s	1.579ms	49	50	98.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	34.760s	1.427ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	7.310s	1.093ms	48	50	96.00
V2	kmac_error_response	keymgr_kmac_rsp_err	8.700s	192.250us	49	50	98.00
V2	invalid_sw_input	keymgr_sw_invalid_input	51.360s	3.821ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	1.252m	2.144ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.840s	1.247ms	49	50	98.00
V2	stress_all	keymgr_stress_all	7.782m	28.994ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.920s	74.007us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.080s	21.508us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.730s	125.528us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.730s	125.528us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.390s	105.308us	5	5	100.00
		keymgr_csr_rw	1.450s	24.893us	20	20	100.00
		keymgr_csr_aliasing	12.080s	3.080ms	5	5	100.00
		keymgr_same_csr_outstanding	3.640s	415.828us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.390s	105.308us	5	5	100.00
		keymgr_csr_rw	1.450s	24.893us	20	20	100.00
		keymgr_csr_aliasing	12.080s	3.080ms	5	5	100.00
		keymgr_same_csr_outstanding	3.640s	415.828us	20	20	100.00
V2		TOTAL			733	740	99.05
V2S	sec_cm_additional_check	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
		keymgr_tl_intg_err	10.800s	3.239ms	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.620s	214.179us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.620s	214.179us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.620s	214.179us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.620s	214.179us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	16.450s	912.375us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.800s	3.239ms	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.620s	214.179us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.582m	7.050ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	41.350s	2.566ms	50	50	100.00
		keymgr_csr_rw	1.450s	24.893us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	41.350s	2.566ms	50	50	100.00
		keymgr_csr_rw	1.450s	24.893us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	41.350s	2.566ms	50	50	100.00
		keymgr_csr_rw	1.450s	24.893us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	7.310s	1.093ms	48	50	96.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	1.252m	2.144ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	1.252m	2.144ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	41.350s	2.566ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	39.320s	1.437ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	13.760s	551.980us	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	7.310s	1.093ms	48	50	96.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	13.760s	551.980us	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	13.760s	551.980us	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	13.760s	551.980us	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	16.910s	1.200ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	13.760s	551.980us	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.400s	723.538us	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1090	1110	98.20

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	10	62.50
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.75	99.04	98.11	98.44	100.00	99.02	98.41	91.24

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 12 failures:
- Test keymgr_stress_all_with_rand_reset has 12 failures.
  - 5.keymgr_stress_all_with_rand_reset.75973151760568055909998755227006414390589400226401483607961841718279101895399
    Line 312, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 405617771 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 405617771 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.keymgr_stress_all_with_rand_reset.10418368508729754282544699199976802368254633396641123852946798176035628242005
    Line 322, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 458247420 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 458247420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 5 failures:
- Test keymgr_stress_all has 1 failures.
  - 8.keymgr_stress_all.59928381603040918849090949360179201517129579786175096147018379486240462531299
    Line 829, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/8.keymgr_stress_all/latest/run.log
```
  UVM_ERROR @ 142077107 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 142077107 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sideload_otbn has 1 failures.
  - 11.keymgr_sideload_otbn.72128363229414678811395451893107911347530713546774723706437041753757668099207
    Line 369, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest/run.log
```
  UVM_ERROR @ 333087796 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @ 333087796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_stress_all_with_rand_reset has 1 failures.
  - 11.keymgr_stress_all_with_rand_reset.85287134139427225587023955974279136893777192187409763386320391274298121984937
    Line 262, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/11.keymgr_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  55952008 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:2000
  UVM_INFO @  55952008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_cfg_regwen has 1 failures.
  - 22.keymgr_cfg_regwen.61863303443491472357252208593157904447521500711550628486930761524611123581763
    Line 324, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest/run.log
```
  UVM_ERROR @   4008649 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @   4008649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test keymgr_sync_async_fault_cross has 1 failures.
  - 36.keymgr_sync_async_fault_cross.91961578143502597988625836959738191880051559030676115277503264098251482584083
    Line 288, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest/run.log
```
  UVM_ERROR @  12237821 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
  UVM_INFO @  12237821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:
- Test keymgr_kmac_rsp_err has 1 failures.
  - 25.keymgr_kmac_rsp_err.1225420340688877797550334248531780752078923660479624297784987101896451957308
    Line 674, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest/run.log
```
  UVM_ERROR @  75220989 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
  UVM_INFO @  75220989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StCreatorRootKey for Attestation Kmac has 1 failures:

Test keymgr_lc_disable has 1 failures.

36.keymgr_lc_disable.49285565974221278905172888790474137628382741725116885073127704182788425281196
Line 361, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/36.keymgr_lc_disable/latest/run.log

  UVM_ERROR @  47589498 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (4230353783760223971000308642548964784633104525463824646850214605808834878545352254650878898416067064425430029299799480487627486280179626905857351008194219 [0x50c589df89a25f6c42d42bd628ccd67fc63ffa595af6128ef1198cce60d058979a63fec7945bad06be8d70e512a472af148f1e15206010b48922a4e95c6d0eab] vs 4230353783760223971000308642548964784633104525463824646850214605808834878545352254650878898416067064425430029299799480487627486280179626905857351008194219 [0x50c589df89a25f6c42d42bd628ccd67fc63ffa595af6128ef1198cce60d058979a63fec7945bad06be8d70e512a472af148f1e15206010b48922a4e95c6d0eab]) KMAC key at state StCreatorRootKey for Attestation Kmac
  UVM_INFO @  47589498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (keymgr_scoreboard.sv:766) [scoreboard] Check failed item.d_data !=gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.sw_share1_output_*` has 1 failures:
- Test keymgr_lc_disable has 1 failures.
  - 45.keymgr_lc_disable.93798823745771264617555557788322039048365513863601151894509950447680355835567
    Line 607, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/45.keymgr_lc_disable/latest/run.log
```
  UVM_ERROR @  27604991 ps: (keymgr_scoreboard.sv:766) [uvm_test_top.env.scoreboard] Check failed item.d_data != `gmv(csr) (3628416443 [0xd8453dbb] vs 3628416443 [0xd8453dbb]) reg name: keymgr_reg_block.sw_share1_output_2
  UVM_INFO @  27604991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```