KEYMGR Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: eca25c0ff8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	32.190s	3.707ms	49	50	98.00
V1	random	keymgr_random	51.340s	8.975ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.310s	18.603us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.610s	31.077us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.450s	2.698ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	15.600s	458.602us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.430s	110.174us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.610s	31.077us	20	20	100.00
		keymgr_csr_aliasing	15.600s	458.602us	5	5	100.00
V1		TOTAL			154	155	99.35
V2	cfgen_during_op	keymgr_cfg_regwen	1.504m	1.707ms	50	50	100.00
V2	sideload	keymgr_sideload	42.050s	7.156ms	50	50	100.00
		keymgr_sideload_kmac	1.037m	10.405ms	50	50	100.00
		keymgr_sideload_aes	48.350s	2.938ms	50	50	100.00
		keymgr_sideload_otbn	38.680s	3.263ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	21.480s	3.176ms	50	50	100.00
V2	lc_disable	keymgr_lc_disable	8.130s	523.813us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.540s	393.601us	48	50	96.00
V2	invalid_sw_input	keymgr_sw_invalid_input	1.013m	12.920ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	52.490s	6.616ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	24.050s	1.652ms	50	50	100.00
V2	stress_all	keymgr_stress_all	12.260m	276.111ms	49	50	98.00
V2	intr_test	keymgr_intr_test	0.950s	11.481us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.120s	31.452us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	4.590s	264.368us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	4.590s	264.368us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.310s	18.603us	5	5	100.00
		keymgr_csr_rw	1.610s	31.077us	20	20	100.00
		keymgr_csr_aliasing	15.600s	458.602us	5	5	100.00
		keymgr_same_csr_outstanding	4.150s	384.605us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.310s	18.603us	5	5	100.00
		keymgr_csr_rw	1.610s	31.077us	20	20	100.00
		keymgr_csr_aliasing	15.600s	458.602us	5	5	100.00
		keymgr_same_csr_outstanding	4.150s	384.605us	20	20	100.00
V2		TOTAL			737	740	99.59
V2S	sec_cm_additional_check	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
		keymgr_tl_intg_err	10.770s	311.558us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.820s	357.570us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.820s	357.570us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.820s	357.570us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.820s	357.570us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.740s	461.667us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	10.770s	311.558us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.820s	357.570us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.504m	1.707ms	50	50	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	51.340s	8.975ms	50	50	100.00
		keymgr_csr_rw	1.610s	31.077us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	51.340s	8.975ms	50	50	100.00
		keymgr_csr_rw	1.610s	31.077us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	51.340s	8.975ms	50	50	100.00
		keymgr_csr_rw	1.610s	31.077us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.130s	523.813us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	52.490s	6.616ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	52.490s	6.616ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	51.340s	8.975ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	19.380s	654.843us	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	29.370s	1.289ms	49	50	98.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.130s	523.813us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	29.370s	1.289ms	49	50	98.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	29.370s	1.289ms	49	50	98.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	29.370s	1.289ms	49	50	98.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.700s	4.452ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	29.370s	1.289ms	49	50	98.00
V2S		TOTAL			164	165	99.39
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	30.090s	3.101ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1086	1110	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	16	16	14	87.50
V2S	6	6	5	83.33
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.69	99.04	97.95	98.30	100.00	99.02	98.41	91.14

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:839) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 17 failures:

  • Test keymgr_stress_all_with_rand_reset has 17 failures.

    • 3.keymgr_stress_all_with_rand_reset.62764411472500173746026488988293610003896298286007570590940243820980125727510
      Line 1226, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/3.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 434780254 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 434780254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.keymgr_stress_all_with_rand_reset.104788323731728153423519771245008861467287411776451439284431106653781226993136
      Line 342, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 135168132 ps: (cip_base_vseq.sv:839) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 135168132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 15 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 4 failures:

  • Test keymgr_stress_all has 1 failures.

    • 5.keymgr_stress_all.112208978875624493427504216738046890390905748432094099416018788686056892150458
      Line 1624, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/5.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 2319863335 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 2319863335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 6.keymgr_kmac_rsp_err.75610460329093838158584568714107412717074887394549152470011507949023941212577
      Line 437, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @ 166207716 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 166207716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 16.keymgr_stress_all_with_rand_reset.76002005602293236324699770763948085967948245264455673924652684128791954203151
      Line 2639, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/16.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 406928051 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 406928051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_smoke has 1 failures.

    • 41.keymgr_smoke.80657233765920191686912765105127748344032378873690741604689693587134778543206
      Line 259, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/41.keymgr_smoke/latest/run.log

        UVM_ERROR @   5508057 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @   5508057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_operation_err triggered unexpectedly has 1 failures:

  • Test keymgr_kmac_rsp_err has 1 failures.

    • 1.keymgr_kmac_rsp_err.83845885316531469699286532860044596492325089321783504591156084285403146609129
      Line 371, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest/run.log

        UVM_ERROR @  13868721 ps: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_operation_err triggered unexpectedly
        UVM_INFO @  13868721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (keymgr_custom_cm_vseq.sv:37) [keymgr_custom_cm_vseq] wait timeout occurred! has 1 failures:

  • Test keymgr_custom_cm has 1 failures.

    • 21.keymgr_custom_cm.26729526043165053931429255559681571122806308000425409302001972556813000328155
      Line 368, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/21.keymgr_custom_cm/latest/run.log

        UVM_FATAL @ 10163426829 ps: (keymgr_custom_cm_vseq.sv:37) [uvm_test_top.env.virtual_sequencer.keymgr_custom_cm_vseq] wait timeout occurred!
        UVM_INFO @ 10163426829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:689) [scoreboard] Check failed edn_fifos[*].used() == * (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 42.keymgr_stress_all_with_rand_reset.91022514143626078910297736455908707459677437178208493078578037440059173686880
      Line 356, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/42.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @  26473428 ps: (keymgr_scoreboard.sv:689) [uvm_test_top.env.scoreboard] Check failed edn_fifos[0].used() == 2 (0 [0x0] vs 2 [0x2])
        UVM_INFO @  26473428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.07.28_10.42.23
• 2024.07.27_09.34.01
• 2024.07.26_08.57.56
• 2024.07.25_08.28.14
• 2024.07.24_08.09.31
• 2024.07.23_08.43.01