KEYMGR Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	26.760s	11.321ms	50	50	100.00
V1	random	keymgr_random	1.301m	7.970ms	50	50	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.470s	164.863us	5	5	100.00
V1	csr_rw	keymgr_csr_rw	1.490s	113.716us	20	20	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	16.790s	4.123ms	5	5	100.00
V1	csr_aliasing	keymgr_csr_aliasing	16.730s	998.459us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.140s	31.111us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.490s	113.716us	20	20	100.00
		keymgr_csr_aliasing	16.730s	998.459us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	cfgen_during_op	keymgr_cfg_regwen	1.482m	1.811ms	49	50	98.00
V2	sideload	keymgr_sideload	42.660s	3.591ms	50	50	100.00
		keymgr_sideload_kmac	35.760s	2.621ms	50	50	100.00
		keymgr_sideload_aes	23.280s	3.440ms	50	50	100.00
		keymgr_sideload_otbn	1.038m	5.857ms	50	50	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	22.710s	1.295ms	49	50	98.00
V2	lc_disable	keymgr_lc_disable	8.510s	588.425us	50	50	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	11.230s	517.112us	50	50	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	56.850s	11.984ms	50	50	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	42.970s	3.747ms	50	50	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	23.140s	5.598ms	50	50	100.00
V2	stress_all	keymgr_stress_all	9.012m	44.605ms	48	50	96.00
V2	intr_test	keymgr_intr_test	0.860s	11.791us	50	50	100.00
V2	alert_test	keymgr_alert_test	1.020s	26.593us	50	50	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	5.130s	497.940us	20	20	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	5.130s	497.940us	20	20	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.470s	164.863us	5	5	100.00
		keymgr_csr_rw	1.490s	113.716us	20	20	100.00
		keymgr_csr_aliasing	16.730s	998.459us	5	5	100.00
		keymgr_same_csr_outstanding	2.880s	210.396us	20	20	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.470s	164.863us	5	5	100.00
		keymgr_csr_rw	1.490s	113.716us	20	20	100.00
		keymgr_csr_aliasing	16.730s	998.459us	5	5	100.00
		keymgr_same_csr_outstanding	2.880s	210.396us	20	20	100.00
V2		TOTAL			736	740	99.46
V2S	sec_cm_additional_check	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	tl_intg_err	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
		keymgr_tl_intg_err	11.170s	331.082us	20	20	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.360s	187.895us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.360s	187.895us	20	20	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.360s	187.895us	20	20	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.360s	187.895us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	15.620s	906.937us	20	20	100.00
V2S	prim_count_check	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	prim_fsm_check	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	11.170s	331.082us	20	20	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.360s	187.895us	20	20	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	1.482m	1.811ms	49	50	98.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	1.301m	7.970ms	50	50	100.00
		keymgr_csr_rw	1.490s	113.716us	20	20	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	1.301m	7.970ms	50	50	100.00
		keymgr_csr_rw	1.490s	113.716us	20	20	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	1.301m	7.970ms	50	50	100.00
		keymgr_csr_rw	1.490s	113.716us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	8.510s	588.425us	50	50	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	42.970s	3.747ms	50	50	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	42.970s	3.747ms	50	50	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	1.301m	7.970ms	50	50	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	16.410s	3.313ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	11.590s	2.038ms	50	50	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	8.510s	588.425us	50	50	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	11.590s	2.038ms	50	50	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	11.590s	2.038ms	50	50	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	11.590s	2.038ms	50	50	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	11.130s	1.885ms	5	5	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	11.590s	2.038ms	50	50	100.00
V2S		TOTAL			165	165	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	31.600s	8.831ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			1084	1110	97.66

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	16	16	13	81.25
V2S	6	6	6	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.67	99.04	97.99	98.20	100.00	99.02	98.41	91.07

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:836) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test keymgr_stress_all_with_rand_reset has 21 failures.

    • 1.keymgr_stress_all_with_rand_reset.20860350431932186960373343975539818704033019391932710937047099860656505045818
      Line 447, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 447385402 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 447385402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.keymgr_stress_all_with_rand_reset.47326884778356210346483138152121913671004755608821840492987330012463236974163
      Line 388, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 117442001 ps: (cip_base_vseq.sv:836) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 117442001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:* has 3 failures:

  • Test keymgr_stress_all has 2 failures.

    • 23.keymgr_stress_all.111579529207307916997201711425945372673536957091698381697742054149440326290939
      Line 1440, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/23.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 202805577 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 202805577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.keymgr_stress_all.60228997751913394574540712612058207745438264102857336881847725574433288340019
      Line 913, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/46.keymgr_stress_all/latest/run.log

        UVM_ERROR @ 198095301 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @ 198095301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_direct_to_disabled has 1 failures.

    • 39.keymgr_direct_to_disabled.93265049308647728694479864057419738235766138197297582084448297441326546459108
      Line 299, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest/run.log

        UVM_ERROR @  53866726 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:0
        UVM_INFO @  53866726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:794) [scoreboard] Check failed item.d_data ==gmv(csr) (* [] vs * []) reg name: keymgr_reg_block.start` has 1 failures:

  • Test keymgr_cfg_regwen has 1 failures.

    • 20.keymgr_cfg_regwen.66174892871974075421195466823842008172011417433867641875882412092570531261236
      Line 499, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest/run.log

        UVM_ERROR @  50976728 ps: (keymgr_scoreboard.sv:794) [uvm_test_top.env.scoreboard] Check failed item.d_data == `gmv(csr) (0 [0x0] vs 1 [0x1]) reg name: keymgr_reg_block.start
        UVM_INFO @  50976728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (keymgr_scoreboard.sv:692) [scoreboard] Check failed item.d_data == addr_phase_op_status (* [*] vs * [*]) has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 33.keymgr_stress_all_with_rand_reset.82022911983075972275713782483413798352823493116890617879335296631072856962849
      Line 1170, in log /container/opentitan-public/scratch/os_regression/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 621009100 ps: (keymgr_scoreboard.sv:692) [uvm_test_top.env.scoreboard] Check failed item.d_data == addr_phase_op_status (1 [0x1] vs 3 [0x3])
        UVM_INFO @ 621009100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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