KMAC/MASKED Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.517m	17.069ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.210s	96.788us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.300s	132.499us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.880s	4.324ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.800s	3.723ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.200s	93.802us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.300s	132.499us	20	20	100.00
		kmac_csr_aliasing	11.800s	3.723ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	50.453us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.520s	113.923us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	59.184m	136.519ms	50	50	100.00
V2	burst_write	kmac_burst_write	25.561m	60.215ms	47	50	94.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.406m	1.583s	50	50	100.00
		kmac_test_vectors_sha3_256	39.784m	379.648ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.390m	712.454ms	50	50	100.00
		kmac_test_vectors_sha3_512	27.787m	702.344ms	50	50	100.00
		kmac_test_vectors_shake_128	1.928h	2.018s	50	50	100.00
		kmac_test_vectors_shake_256	1.591h	1.461s	50	50	100.00
		kmac_test_vectors_kmac	7.380s	501.172us	50	50	100.00
		kmac_test_vectors_kmac_xof	6.850s	248.803us	50	50	100.00
V2	sideload	kmac_sideload	9.518m	85.383ms	50	50	100.00
V2	app	kmac_app	7.344m	69.716ms	47	50	94.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.627m	23.225ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.742m	35.911ms	50	50	100.00
V2	error	kmac_error	8.263m	135.178ms	50	50	100.00
V2	key_error	kmac_key_error	10.380s	15.523ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.830s	1.084ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	45.450s	8.555ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.402m	27.050ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	52.300s	1.944ms	50	50	100.00
V2	stress_all	kmac_stress_all	51.494m	230.375ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.930s	18.973us	50	50	100.00
V2	alert_test	kmac_alert_test	0.950s	133.869us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.760s	71.835us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.760s	71.835us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.210s	96.788us	5	5	100.00
		kmac_csr_rw	1.300s	132.499us	20	20	100.00
		kmac_csr_aliasing	11.800s	3.723ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	667.697us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.210s	96.788us	5	5	100.00
		kmac_csr_rw	1.300s	132.499us	20	20	100.00
		kmac_csr_aliasing	11.800s	3.723ms	5	5	100.00
		kmac_same_csr_outstanding	3.030s	667.697us	20	20	100.00
V2		TOTAL			1042	1050	99.24
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.200s	655.747us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.200s	655.747us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.200s	655.747us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.200s	655.747us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.820s	318.264us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	2.040m	9.827ms	5	5	100.00
		kmac_tl_intg_err	6.570s	4.789ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.570s	4.789ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	52.300s	1.944ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.517m	17.069ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.518m	85.383ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.200s	655.747us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	2.040m	9.827ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	2.040m	9.827ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	2.040m	9.827ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.517m	17.069ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	52.300s	1.944ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	2.040m	9.827ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	7.034m	14.882ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.517m	17.069ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.001h	354.225ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			1270	1290	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.33	98.40	93.40	99.93	96.36	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:

Test kmac_stress_all_with_rand_reset has 10 failures.

7.kmac_stress_all_with_rand_reset.3162631324
Line 1825, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 86547378666 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 86547378666 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.kmac_stress_all_with_rand_reset.701911465
Line 757, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 181200590383 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 181200590383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 5 failures:

Test kmac_app has 3 failures.

4.kmac_app.3686039483
Line 395, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_app/latest/run.log

  UVM_FATAL @ 41083160025 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (239 [0xef] vs 118 [0x76]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 41083160025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.kmac_app.257707331
Line 245, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_app/latest/run.log

  UVM_FATAL @ 1181652562 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (28 [0x1c] vs 155 [0x9b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1181652562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test kmac_app_with_partial_data has 1 failures.

8.kmac_app_with_partial_data.409355811
Line 354, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 5391311991 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (236 [0xec] vs 18 [0x12]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5391311991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

44.kmac_stress_all.2807631922
Line 421, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_FATAL @ 39844012057 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (165 [0xa5] vs 172 [0xac]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 39844012057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test kmac_burst_write has 3 failures.

21.kmac_burst_write.3449936380
Line 383, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

40.kmac_burst_write.3772626811
Line 310, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/40.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.entropy_period.prescaler reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 17.kmac_shadow_reg_errors_with_csr_rw.2369601381
    Line 246, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   8719049 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (346 [0x15a] vs 0 [0x0]) Regname: kmac_reg_block.entropy_period.prescaler reset value: 0x0
  UVM_INFO @   8719049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 29.kmac_stress_all_with_rand_reset.976107298
    Line 553, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 26892590924 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 26892590924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```