KMAC/MASKED Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.784m	16.668ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.240s	49.390us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.190s	28.669us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	19.890s	2.154ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.610s	4.327ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.620s	33.626us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.190s	28.669us	20	20	100.00
		kmac_csr_aliasing	11.610s	4.327ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.870s	97.987us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.460s	157.399us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	52.610m	253.038ms	49	50	98.00
V2	burst_write	kmac_burst_write	23.580m	14.238ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.232m	98.511ms	50	50	100.00
		kmac_test_vectors_sha3_256	40.827m	417.445ms	48	50	96.00
		kmac_test_vectors_sha3_384	32.357m	418.152ms	49	50	98.00
		kmac_test_vectors_sha3_512	25.625m	814.864ms	50	50	100.00
		kmac_test_vectors_shake_128	1.694h	2.539s	49	50	98.00
		kmac_test_vectors_shake_256	1.526h	3.142s	50	50	100.00
		kmac_test_vectors_kmac	10.160s	1.336ms	50	50	100.00
		kmac_test_vectors_kmac_xof	8.210s	808.537us	50	50	100.00
V2	sideload	kmac_sideload	9.875m	34.503ms	49	50	98.00
V2	app	kmac_app	7.226m	133.669ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.716m	14.302ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.240m	7.564ms	50	50	100.00
V2	error	kmac_error	8.574m	20.775ms	49	50	98.00
V2	key_error	kmac_key_error	9.120s	11.090ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	56.270s	8.890ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	37.480s	2.113ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.309m	29.330ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	44.780s	918.124us	50	50	100.00
V2	stress_all	kmac_stress_all	48.099m	111.237ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.920s	22.170us	50	50	100.00
V2	alert_test	kmac_alert_test	0.960s	24.167us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.060s	875.032us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.060s	875.032us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.240s	49.390us	5	5	100.00
		kmac_csr_rw	1.190s	28.669us	20	20	100.00
		kmac_csr_aliasing	11.610s	4.327ms	5	5	100.00
		kmac_same_csr_outstanding	3.050s	1.147ms	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.240s	49.390us	5	5	100.00
		kmac_csr_rw	1.190s	28.669us	20	20	100.00
		kmac_csr_aliasing	11.610s	4.327ms	5	5	100.00
		kmac_same_csr_outstanding	3.050s	1.147ms	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.460s	173.736us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.460s	173.736us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.460s	173.736us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.460s	173.736us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.700s	187.334us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.924m	37.164ms	5	5	100.00
		kmac_tl_intg_err	5.350s	910.112us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.350s	910.112us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	44.780s	918.124us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.784m	16.668ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.875m	34.503ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.460s	173.736us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.924m	37.164ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.924m	37.164ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.924m	37.164ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.784m	16.668ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	44.780s	918.124us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.924m	37.164ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.535m	22.139ms	9	10	90.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.784m	16.668ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	55.294m	574.909ms	35	50	70.00
V3		TOTAL			35	50	70.00
		TOTAL			1263	1290	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.02	98.38	93.02	99.93	94.55	96.04	98.89	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 12 failures:
- Test kmac_stress_all_with_rand_reset has 12 failures.
  - 1.kmac_stress_all_with_rand_reset.51862012396476504087236866710620610234238069339413539143881538885377267888693
    Line 712, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 28396720451 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 28396720451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.48193762337317418123976169079795272245500798659592681666465979497089188572294
    Line 588, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 52001962413 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 52001962413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
- Test kmac_test_vectors_sha3_384 has 1 failures.
  - 5.kmac_test_vectors_sha3_384.82985256430136804464285831436238386093517267243491060542073895709676218609104
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_384/latest/run.log
```
  UVM_ERROR @  75283376 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  75283376 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 16.kmac_test_vectors_shake_128.80071978381286172937871958653124664140503593596932504827842908039664172002144
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_ERROR @  38332824 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  38332824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 37.kmac_stress_all_with_rand_reset.60489638651452452022124791470956185668195613010362471810450275763857679262208
    Line 523, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 39285816648 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 39285816648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 2 failures.
  - 38.kmac_test_vectors_sha3_256.34925580159730175401072307615193026164765641430976595443999042981196269917386
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  32199415 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  32199415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.kmac_test_vectors_sha3_256.94393539171853278072718738887319379899263062960565909071851006868465259965351
    Line 277, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  37496966 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  37496966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 18.kmac_stress_all_with_rand_reset.82054804715168428304419010312236281070737951271409140086712323263836993119204
    Line 1418, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 207181419096 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 207181419096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.kmac_stress_all_with_rand_reset.39496267514737202110994608610097263845689753191599011614186463616485452404825
    Line 916, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 244731002469 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 244731002469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 25.kmac_stress_all.53006401565807106907470648728776650115120111225519147715667588643269202670320
    Line 449, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 58208768853 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 58208768853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.kmac_stress_all.26102963398588218174899733884333554006034705774681989814090786858137421313926
    Line 582, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/49.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 138591906631 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 138591906631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 26.kmac_error.54272192413367410094989100666634537088253182085647569869183932781161502607737
    Line 290, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_error/latest/run.log
```
  UVM_FATAL @ 10284754071 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10284754071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_mubi has 1 failures.

3.kmac_mubi.8147790488881854532610559212767153385187241046306122662157002179012462279744
Line 307, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_mubi/latest/run.log

  UVM_FATAL @ 13773170076 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (82 [0x52] vs 231 [0xe7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13773170076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

20.kmac_stress_all.55878819762887282306130579091470148730949195280734658994904762366437879698905
Line 410, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all/latest/run.log

  UVM_FATAL @ 16373725079 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (16 [0x10] vs 245 [0xf5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16373725079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_sideload has 1 failures.
  - 9.kmac_sideload.50573356529244608892213571953528549844513884974209839428896284502209421984219
    Line 459, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 31.kmac_burst_write.6807676719586556770943586717531663584882723154667803715082289228674583983253
    Line 357, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 38.kmac_long_msg_and_output.6930002403350461886579089700519876588474074134993710170004483234836402044010
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:1c6cd69b-739a-4bdf-b530-0150390c6cff
```