b938dde05c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.642m | 40.745ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.170s | 33.141us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.170s | 45.033us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 21.100s | 1.461ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.110s | 397.809us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.490s | 263.365us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.170s | 45.033us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.110s | 397.809us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.820s | 26.271us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.470s | 41.962us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 57.504m | 480.926ms | 50 | 50 | 100.00 |
| V2 | burst_write | kmac_burst_write | 28.193m | 65.858ms | 50 | 50 | 100.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 41.720m | 394.044ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 40.233m | 189.031ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_384 | 35.431m | 792.558ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_512 | 24.658m | 205.453ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.803h | 584.766ms | 48 | 50 | 96.00 | ||
| kmac_test_vectors_shake_256 | 1.497h | 1.932s | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac | 7.340s | 1.089ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_kmac_xof | 7.920s | 4.358ms | 49 | 50 | 98.00 | ||
| V2 | sideload | kmac_sideload | 9.778m | 87.654ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.483m | 66.799ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.517m | 27.696ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.588m | 26.829ms | 46 | 50 | 92.00 |
| V2 | error | kmac_error | 10.570m | 189.815ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 7.580s | 1.235ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 50.240s | 559.928us | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 42.460s | 2.125ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 56.770s | 9.933ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 47.360s | 865.612us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 41.601m | 99.552ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.890s | 105.138us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.970s | 67.718us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.750s | 629.461us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.750s | 629.461us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.170s | 33.141us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 45.033us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.110s | 397.809us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.680s | 451.060us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.170s | 33.141us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.170s | 45.033us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.110s | 397.809us | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.680s | 451.060us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1040 | 1050 | 99.05 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.360s | 96.804us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.360s | 96.804us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.360s | 96.804us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.360s | 96.804us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.160s | 133.285us | 19 | 20 | 95.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.185m | 63.094ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.200s | 378.013us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.200s | 378.013us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 47.360s | 865.612us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.642m | 40.745ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.778m | 87.654ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.360s | 96.804us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.185m | 63.094ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.185m | 63.094ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.185m | 63.094ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.642m | 40.745ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 47.360s | 865.612us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.185m | 63.094ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 5.926m | 175.308ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.642m | 40.745ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 74 | 75 | 98.67 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.549h | 189.228ms | 12 | 50 | 24.00 |
| V3 | TOTAL | 12 | 50 | 24.00 | |||
| TOTAL | 1241 | 1290 | 96.20 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 19 | 76.00 |
| V2S | 5 | 5 | 4 | 80.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.86 | 98.10 | 92.71 | 99.89 | 94.55 | 95.97 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:
1.kmac_stress_all_with_rand_reset.67243138983945893060260220028544012441250087710317845915518851748891237819900
Line 442, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22360980815 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 22360980815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.13856229570826224371521165551830329589308346091614722850015557611963499595258
Line 752, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12345093980 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 12345093980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 5 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
13.kmac_test_vectors_sha3_256.39076761439329391993258116765987713606104396457361414392972624446520946029556
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 111225393 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 111225393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 1 failures.
17.kmac_stress_all_with_rand_reset.16121380869173077517299685728781581758782425932175551327645279176748666333497
Line 1490, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 77479227636 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 77479227636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
30.kmac_entropy_refresh.17556595676023539284139654612596730163249249813645247893288394015050770351444
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_entropy_refresh/latest/run.log
UVM_ERROR @ 76378077 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 76378077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac_xof has 1 failures.
32.kmac_test_vectors_kmac_xof.3405491442089144254176882329466005531856705131401836059366156704585773994632
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_kmac_xof/latest/run.log
UVM_ERROR @ 35629487 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 35629487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_128 has 1 failures.
35.kmac_test_vectors_shake_128.12301717139121420463680115409486907959561792969800513848567110787609503449546
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_shake_128/latest/run.log
UVM_ERROR @ 106756278 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 106756278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 4 failures:
6.kmac_stress_all_with_rand_reset.108513847076579575023920390970113242094298975497758291659424169273183414275360
Line 330, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11822308067 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483704 [0x80000038]) reg name: kmac_reg_block.err_code
UVM_INFO @ 11822308067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.kmac_stress_all_with_rand_reset.102618247356824816087228007961749873085886102194123238406914537634962919274639
Line 2159, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 224402646874 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
UVM_INFO @ 224402646874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
Test kmac_stress_all has 1 failures.
3.kmac_stress_all.98316500708831123892869521321691481463521475673903058898712747644666138609738
Line 705, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all/latest/run.log
UVM_FATAL @ 173860868943 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 173860868943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_stress_all_with_rand_reset has 2 failures.
20.kmac_stress_all_with_rand_reset.78610434799350891104007836886616234888105214539794975341235429781307205208210
Line 2709, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 302672047441 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 302672047441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.kmac_stress_all_with_rand_reset.19084168418264728565364380086841210141871877933468829787559108705342559793311
Line 683, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 226933292042 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 226933292042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:
17.kmac_entropy_refresh.105087708276668903492689265923438503032208036998776523805791451892544886729034
Line 507, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 6668218372 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (153 [0x99] vs 94 [0x5e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 6668218372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.kmac_entropy_refresh.99439276960337464891166546453595413307840037166672161644031583060523203143472
Line 353, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 3039412619 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (118 [0x76] vs 36 [0x24]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 3039412619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
Test kmac_test_vectors_shake_128 has 1 failures.
25.kmac_test_vectors_shake_128.80700420287171471881474376310213938569368163983836387919164558491946727857003
Line 5411, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_128/latest/run.log
UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
29.kmac_error.104673804591991023679360064699028340448957515705459091897845797405527814683757
Line 1003, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_error/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
4.kmac_shadow_reg_errors_with_csr_rw.21379481695291376981009801905834958633493112172271590627398483725172876408262
Line 255, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
UVM_ERROR @ 42800634 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (238515065 [0xe377379] vs 1309414519 [0x4e0c1477]) Regname: kmac_reg_block.prefix_4.prefix_0 reset value: 0x0
UVM_INFO @ 42800634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---