KMAC/MASKED Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: `4fd94db59a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.470m	18.246ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.120s	105.707us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.230s	35.359us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	22.950s	3.349ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.070s	5.348ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	72.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.230s	35.359us	20	20	100.00
		kmac_csr_aliasing	11.070s	5.348ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.810s	38.500us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	78.433us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.790m	128.272ms	46	50	92.00
V2	burst_write	kmac_burst_write	27.985m	63.462ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	45.643m	1.233s	50	50	100.00
		kmac_test_vectors_sha3_256	44.751m	843.822ms	49	50	98.00
		kmac_test_vectors_sha3_384	33.271m	298.936ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.715m	206.801ms	49	50	98.00
		kmac_test_vectors_shake_128	1.907h	563.620ms	50	50	100.00
		kmac_test_vectors_shake_256	1.571h	1.382s	50	50	100.00
		kmac_test_vectors_kmac	7.340s	535.850us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.670s	1.866ms	50	50	100.00
V2	sideload	kmac_sideload	9.684m	108.674ms	50	50	100.00
V2	app	kmac_app	7.083m	71.869ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.033m	20.301ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	6.510m	14.913ms	49	50	98.00
V2	error	kmac_error	8.793m	77.503ms	49	50	98.00
V2	key_error	kmac_key_error	7.690s	4.038ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	41.390s	1.429ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	41.880s	6.624ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.332m	26.927ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	1.049m	3.697ms	50	50	100.00
V2	stress_all	kmac_stress_all	1.211h	805.535ms	47	50	94.00
V2	intr_test	kmac_intr_test	0.860s	22.850us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	114.769us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.860s	140.775us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.860s	140.775us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.120s	105.707us	5	5	100.00
		kmac_csr_rw	1.230s	35.359us	20	20	100.00
		kmac_csr_aliasing	11.070s	5.348ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	414.734us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.120s	105.707us	5	5	100.00
		kmac_csr_rw	1.230s	35.359us	20	20	100.00
		kmac_csr_aliasing	11.070s	5.348ms	5	5	100.00
		kmac_same_csr_outstanding	2.720s	414.734us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.510s	69.296us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.510s	69.296us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.510s	69.296us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.510s	69.296us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.210s	943.768us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.871m	103.253ms	5	5	100.00
		kmac_tl_intg_err	5.240s	298.166us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.240s	298.166us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	1.049m	3.697ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.470m	18.246ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.684m	108.674ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.510s	69.296us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.871m	103.253ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.871m	103.253ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.871m	103.253ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.470m	18.246ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	1.049m	3.697ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.871m	103.253ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.883m	163.010ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.470m	18.246ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.475h	1.346s	13	50	26.00
V3		TOTAL			13	50	26.00
		TOTAL			1238	1290	95.97

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	16	64.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.95	98.10	92.58	99.89	95.45	95.97	98.89	97.75

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
- Test kmac_stress_all_with_rand_reset has 29 failures.
  - 1.kmac_stress_all_with_rand_reset.78532469258937908495482144445785949505683483564865008756305685701527729640139
    Line 755, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 63674071369 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 63674071369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.87525150805574887588237719458001046766270872828411380027173733870622140844808
    Line 1802, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 26775683310 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 26775683310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 27 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:
- Test kmac_stress_all_with_rand_reset has 8 failures.
  - 7.kmac_stress_all_with_rand_reset.8661597183307298319280006915614382431933003899808827946846021173529650655074
    Line 262, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  32490881 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
  UVM_INFO @  32490881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.kmac_stress_all_with_rand_reset.4946045381134692283649459564385866672329439740665769054438468850888412878929
    Line 680, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19961116415 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 19961116415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test kmac_long_msg_and_output has 4 failures.
  - 21.kmac_long_msg_and_output.94155279673419158197136401154380714344107178471575931428603784882795197239846
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:819c361e-0968-41c1-9d2d-68cc411a4e1a
```
  - 24.kmac_long_msg_and_output.52563109871632261130460759551758486121516422046109494799387645396885374448695
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:86dc9f55-1f73-4672-9387-76b7cfa48eaa
```
  - ... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 9.kmac_entropy_refresh.94508612786080639872929197958661944284082842128657224438889759657895018237014
    Line 758, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 2 failures.
  - 31.kmac_burst_write.63449274111344126911271179124368893770290430248334336487912196881728797333091
    Line 1046, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.kmac_burst_write.102455310830460117235348707529576769523978701608563215496819868396475556111346
    Line 880, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_stress_all has 2 failures.

13.kmac_stress_all.12251094541981713481431610681583139273726102227918491836759982751407384183444
Line 411, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_stress_all/latest/run.log

  UVM_FATAL @ 2220823284 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (102 [0x66] vs 115 [0x73]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 2220823284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.kmac_stress_all.27849756155856876444173028294931202123379033015586336942643767153376263938165
Line 1591, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/44.kmac_stress_all/latest/run.log

  UVM_FATAL @ 13900019345 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (205 [0xcd] vs 112 [0x70]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 13900019345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

25.kmac_app.35145747852937876993105053515491381655192547956662526058045054695513470934499
Line 517, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 1647278667 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (88 [0x58] vs 183 [0xb7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1647278667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:
- Test kmac_test_vectors_kmac has 1 failures.
  - 28.kmac_test_vectors_kmac.34789584475592061301726288208704940867960696058179231434481931762759656753520
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_test_vectors_kmac/latest/run.log
```
  UVM_ERROR @  61909555 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  61909555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_256 has 1 failures.
  - 34.kmac_test_vectors_sha3_256.46779035403996221582186796344332292521082772418452606761474302548108948832681
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_256/latest/run.log
```
  UVM_ERROR @  60648973 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  60648973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_sha3_512 has 1 failures.
  - 34.kmac_test_vectors_sha3_512.49250702181000615156579145301413045350129080374836891957825812339662196412944
    Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_test_vectors_sha3_512/latest/run.log
```
  UVM_ERROR @  42468520 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  42468520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 2 failures:
- Test kmac_error has 1 failures.
  - 6.kmac_error.107131512934421544711942917742898287783459199326825969929991080895973927969183
    Line 731, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_error/latest/run.log
```
  UVM_FATAL @ 10016945719 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10016945719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 1 failures.
  - 30.kmac_stress_all.13293734003256524889746054744756467535084056892269561696175548380582482822475
    Line 2471, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 314637855198 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 314637855198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```