KMAC/MASKED Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: `9f4903e77a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.585m	7.224ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	64.803us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.210s	103.432us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	15.710s	307.686us	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.140s	444.517us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.670s	513.751us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.210s	103.432us	20	20	100.00
		kmac_csr_aliasing	9.140s	444.517us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	14.921us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.490s	140.872us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.795m	260.406ms	49	50	98.00
V2	burst_write	kmac_burst_write	25.523m	149.330ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	44.334m	686.136ms	49	50	98.00
		kmac_test_vectors_sha3_256	42.350m	558.634ms	50	50	100.00
		kmac_test_vectors_sha3_384	32.366m	645.435ms	50	50	100.00
		kmac_test_vectors_sha3_512	24.033m	50.534ms	50	50	100.00
		kmac_test_vectors_shake_128	1.875h	1.040s	49	50	98.00
		kmac_test_vectors_shake_256	1.536h	482.527ms	48	50	96.00
		kmac_test_vectors_kmac	7.040s	382.063us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.240s	368.359us	50	50	100.00
V2	sideload	kmac_sideload	9.231m	65.493ms	49	50	98.00
V2	app	kmac_app	7.391m	103.586ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.313m	18.980ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	7.285m	73.771ms	50	50	100.00
V2	error	kmac_error	8.211m	41.311ms	49	50	98.00
V2	key_error	kmac_key_error	7.850s	4.365ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	47.310s	7.658ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	43.250s	5.753ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.110m	24.548ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	36.300s	4.917ms	50	50	100.00
V2	stress_all	kmac_stress_all	55.836m	388.292ms	45	50	90.00
V2	intr_test	kmac_intr_test	0.840s	28.243us	50	50	100.00
V2	alert_test	kmac_alert_test	0.910s	31.980us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.290s	224.981us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.290s	224.981us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	64.803us	5	5	100.00
		kmac_csr_rw	1.210s	103.432us	20	20	100.00
		kmac_csr_aliasing	9.140s	444.517us	5	5	100.00
		kmac_same_csr_outstanding	2.710s	115.345us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	64.803us	5	5	100.00
		kmac_csr_rw	1.210s	103.432us	20	20	100.00
		kmac_csr_aliasing	9.140s	444.517us	5	5	100.00
		kmac_same_csr_outstanding	2.710s	115.345us	20	20	100.00
V2		TOTAL			1035	1050	98.57
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.530s	210.490us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.530s	210.490us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.530s	210.490us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.530s	210.490us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.830s	245.974us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.852m	9.000ms	5	5	100.00
		kmac_tl_intg_err	5.230s	947.185us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.230s	947.185us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	36.300s	4.917ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.585m	7.224ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.231m	65.493ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.530s	210.490us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.852m	9.000ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.852m	9.000ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.852m	9.000ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.585m	7.224ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	36.300s	4.917ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.852m	9.000ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.437m	21.965ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.585m	7.224ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.421h	776.323ms	15	50	30.00
V3		TOTAL			15	50	30.00
		TOTAL			1240	1290	96.12

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	15	60.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.07	98.10	92.43	99.89	96.36	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 26 failures:
- Test kmac_stress_all_with_rand_reset has 26 failures.
  - 1.kmac_stress_all_with_rand_reset.56755113830092274062750179127743750453823619290465606327741207383731336338830
    Line 499, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6155169154 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 6155169154 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.kmac_stress_all_with_rand_reset.94603108687869194265735375262034254268259960784384916789360065365091911006628
    Line 258, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1134550302 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1134550302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 24 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 8 failures:
- Test kmac_stress_all has 4 failures.
  - 5.kmac_stress_all.50967044845428944336677472888374779065851919043806088015139191049909644167991
    Line 1584, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 76255658727 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 76255658727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 17.kmac_stress_all.80794645647662302550386033974512077111085032668013783267683972517431408414902
    Line 1082, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 66331152428 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 66331152428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
- Test kmac_stress_all_with_rand_reset has 3 failures.
  - 20.kmac_stress_all_with_rand_reset.74087469662971656388622454717760265841045527393557809560325484470718943176081
    Line 919, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 173864733693 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 173864733693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 30.kmac_stress_all_with_rand_reset.66258060914235453441980552714310353343914427509953790945163504485767905048823
    Line 663, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/30.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 97995720385 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 97995720385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test kmac_error has 1 failures.
  - 24.kmac_error.18970238306609612676920711730645861511617563394271601194977025936408412502788
    Line 402, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_error/latest/run.log
```
  UVM_FATAL @ 10098207059 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10098207059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 6 failures:

Test kmac_sideload has 1 failures.

0.kmac_sideload.87501715152892116768551857586222544794702169818136331970521853788212299639288
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_sideload/latest/run.log

  UVM_ERROR @  31576595 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31576595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 2 failures.

14.kmac_test_vectors_shake_256.12713123569102841992745637599002307958252337559175354301090588323400433676154
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  44597350 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  44597350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.kmac_test_vectors_shake_256.71429537873849686931316001202159306641991625771027081725956982558557253757965
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @ 196278357 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 196278357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

18.kmac_app.6962340758368839899353197269750090866386803470620466593061973384702420766109
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_app/latest/run.log

  UVM_ERROR @ 127945089 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 127945089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

43.kmac_test_vectors_kmac.34314298522285118931282023261570956947266698351529723678935362109469402496599
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/43.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  77093416 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  77093416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_sha3_224 has 1 failures.

46.kmac_test_vectors_sha3_224.82176323627921181495642014027139347714570821719921915170304778262761224098028
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_test_vectors_sha3_224/latest/run.log

  UVM_ERROR @  31761316 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  31761316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
- Test kmac_stress_all_with_rand_reset has 6 failures.
  - 4.kmac_stress_all_with_rand_reset.99064469361933400287758273193761170495365405638357728948496937015615275014971
    Line 1068, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 38467632755 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 38467632755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.kmac_stress_all_with_rand_reset.72012700529349134329248646337606603274306784958310058007456146114344509358670
    Line 436, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6256074057 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 6256074057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 4.kmac_test_vectors_shake_128.44307671440073741100101490967759127772941985967643803429402392369463031345592
    Line 5390, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_burst_write has 1 failures.
  - 14.kmac_burst_write.76298779945022303787120061554149762924394354188849285633663952210361916727016
    Line 914, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test kmac_long_msg_and_output has 1 failures.
  - 2.kmac_long_msg_and_output.101160673016123288894289528911948564038724458752186169685292487468005874299344
    Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest/run.log
```
  Job ID: smart:39dccedc-68d1-454b-8b59-73559f071358
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_stress_all has 1 failures.
  - 7.kmac_stress_all.94785377390176512533960799161376728197996227603793214624166768428340031894040
    Line 915, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 27223327569 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (240 [0xf0] vs 123 [0x7b]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 27223327569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```