KMAC/MASKED Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	2.055m	16.950ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.030s	57.371us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.270s	33.732us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	10.870s	1.247ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.300s	1.905ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.730s	364.524us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.270s	33.732us	20	20	100.00
		kmac_csr_aliasing	11.300s	1.905ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.760s	13.262us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.550s	41.930us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	55.311m	473.683ms	50	50	100.00
V2	burst_write	kmac_burst_write	24.676m	120.996ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	41.397m	338.067ms	50	50	100.00
		kmac_test_vectors_sha3_256	44.343m	917.203ms	50	50	100.00
		kmac_test_vectors_sha3_384	34.092m	460.136ms	50	50	100.00
		kmac_test_vectors_sha3_512	25.813m	542.118ms	50	50	100.00
		kmac_test_vectors_shake_128	1.857h	524.252ms	48	50	96.00
		kmac_test_vectors_shake_256	1.580h	1.057s	50	50	100.00
		kmac_test_vectors_kmac	8.990s	1.048ms	48	50	96.00
		kmac_test_vectors_kmac_xof	7.880s	506.820us	50	50	100.00
V2	sideload	kmac_sideload	7.963m	178.721ms	50	50	100.00
V2	app	kmac_app	6.312m	15.866ms	50	50	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.537m	9.476ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	6.641m	79.939ms	50	50	100.00
V2	error	kmac_error	8.322m	20.635ms	50	50	100.00
V2	key_error	kmac_key_error	11.720s	12.554ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	49.850s	8.003ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	50.150s	1.091ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.128m	24.539ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	50.410s	835.009us	50	50	100.00
V2	stress_all	kmac_stress_all	47.835m	114.830ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	159.126us	50	50	100.00
V2	alert_test	kmac_alert_test	0.920s	62.229us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.850s	1.243ms	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.850s	1.243ms	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.030s	57.371us	5	5	100.00
		kmac_csr_rw	1.270s	33.732us	20	20	100.00
		kmac_csr_aliasing	11.300s	1.905ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	589.178us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.030s	57.371us	5	5	100.00
		kmac_csr_rw	1.270s	33.732us	20	20	100.00
		kmac_csr_aliasing	11.300s	1.905ms	5	5	100.00
		kmac_same_csr_outstanding	2.780s	589.178us	20	20	100.00
V2		TOTAL			1041	1050	99.14
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.590s	52.498us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.590s	52.498us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.590s	52.498us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.590s	52.498us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.020s	455.672us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.919m	8.515ms	5	5	100.00
		kmac_tl_intg_err	5.200s	491.022us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.200s	491.022us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	50.410s	835.009us	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	2.055m	16.950ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.963m	178.721ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.590s	52.498us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.919m	8.515ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.919m	8.515ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.919m	8.515ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	2.055m	16.950ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	50.410s	835.009us	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.919m	8.515ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.086m	47.600ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	2.055m	16.950ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.324h	545.761ms	17	50	34.00
V3		TOTAL			17	50	34.00
		TOTAL			1248	1290	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	20	80.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.81	98.10	92.43	99.89	94.55	95.91	98.89	97.89

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:829) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
- Test kmac_stress_all_with_rand_reset has 24 failures.
  - 2.kmac_stress_all_with_rand_reset.69639538611343718558652502344639323006367418649896865132771245236143000024821
    Line 819, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 196733452311 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 196733452311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.kmac_stress_all_with_rand_reset.19475713748736765110523243229449737395384272365666695745579916378870505336507
    Line 322, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1345490269 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1345490269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 22 more failures.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
- Test kmac_stress_all_with_rand_reset has 7 failures.
  - 0.kmac_stress_all_with_rand_reset.84048512368499784018295468938176744960678000053875444294860490262095376481016
    Line 896, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 163642852104 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483712 [0x80000040]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 163642852104 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.kmac_stress_all_with_rand_reset.57420297267362421178151744397661700859945885186156964860416449273906399619373
    Line 2687, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 50608038638 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 50608038638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:

Test kmac_test_vectors_kmac has 2 failures.

7.kmac_test_vectors_kmac.86793911370593029015663906162991766006457797029258259246176166418166041491011
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  36866685 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  36866685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_test_vectors_kmac.105496481502920414216579839164223235008614338384541266308892504237727940539288
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  59838397 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  59838397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_128 has 2 failures.

18.kmac_test_vectors_shake_128.38383208006318926991391168144943369175015119324798221271378864099055748014274
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  55140965 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  55140965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

38.kmac_test_vectors_shake_128.8109365079210050223421406183550034253488820384066575202267952554725433700913
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  32002551 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  32002551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 4 failures:
- Test kmac_stress_all_with_rand_reset has 2 failures.
  - 28.kmac_stress_all_with_rand_reset.77684008486574445185900336359089494817479119088888534348728533386491313921591
    Line 551, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17739195697 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 17739195697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.kmac_stress_all_with_rand_reset.102331407876065745199161821451934703114723522824464611165787125151120954590090
    Line 764, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 15965040482 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 15965040482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all has 2 failures.
  - 33.kmac_stress_all.77023138742051300838043223930158635954817237475960138553730412349939368014149
    Line 1056, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 15535181951 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 15535181951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.kmac_stress_all.80930610831997411702502781109795600881317889776810832590463237414976051399529
    Line 1144, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/42.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 59600422209 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 59600422209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 2 failures.
  - 24.kmac_burst_write.33571665183688721388621320357288945139669694327456714114199045041457180406399
    Line 716, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/24.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.kmac_burst_write.43251509272922536477232399190616937287327069453038092607679518124919488571559
    Line 1232, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
- Test kmac_app_with_partial_data has 1 failures.
  - 7.kmac_app_with_partial_data.95479088885978466316526865375967358764490670239487308081728130753640853933585
    Line 293, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest/run.log
```
  UVM_FATAL @ 627014318 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (56 [0x38] vs 94 [0x5e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 627014318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```