KMAC/UNMASKED Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.187m	19.148ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.220s	34.973us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	119.387us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.940s	4.776ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.130s	2.304ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.060s	25.509us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	119.387us	20	20	100.00
		kmac_csr_aliasing	11.130s	2.304ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.730s	11.865us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.500s	38.544us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	42.432m	103.209ms	50	50	100.00
V2	burst_write	kmac_burst_write	13.580m	37.000ms	48	50	96.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.971m	404.358ms	50	50	100.00
		kmac_test_vectors_sha3_256	32.901m	476.769ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.215m	293.511ms	50	50	100.00
		kmac_test_vectors_sha3_512	16.832m	51.952ms	50	50	100.00
		kmac_test_vectors_shake_128	1.518h	1.530s	50	50	100.00
		kmac_test_vectors_shake_256	1.401h	2.716s	50	50	100.00
		kmac_test_vectors_kmac	5.490s	2.226ms	50	50	100.00
		kmac_test_vectors_kmac_xof	5.220s	250.002us	50	50	100.00
V2	sideload	kmac_sideload	7.233m	83.075ms	50	50	100.00
V2	app	kmac_app	5.518m	13.574ms	48	50	96.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.519m	13.966ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	4.776m	17.786ms	49	50	98.00
V2	error	kmac_error	6.360m	75.616ms	50	50	100.00
V2	key_error	kmac_key_error	6.480s	1.232ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	42.430s	6.090ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	38.990s	10.333ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.067m	7.856ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	49.670s	2.765ms	50	50	100.00
V2	stress_all	kmac_stress_all	33.154m	110.988ms	49	50	98.00
V2	intr_test	kmac_intr_test	0.870s	19.742us	50	50	100.00
V2	alert_test	kmac_alert_test	0.860s	19.576us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.680s	663.277us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.680s	663.277us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.220s	34.973us	5	5	100.00
		kmac_csr_rw	1.220s	119.387us	20	20	100.00
		kmac_csr_aliasing	11.130s	2.304ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	792.407us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.220s	34.973us	5	5	100.00
		kmac_csr_rw	1.220s	119.387us	20	20	100.00
		kmac_csr_aliasing	11.130s	2.304ms	5	5	100.00
		kmac_same_csr_outstanding	2.750s	792.407us	20	20	100.00
V2		TOTAL			1044	1050	99.43
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.980s	541.654us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.980s	541.654us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.980s	541.654us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.980s	541.654us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.680s	523.387us	20	20	100.00
V2S	tl_intg_err	kmac_sec_cm	1.175m	8.316ms	5	5	100.00
		kmac_tl_intg_err	5.400s	1.638ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.400s	1.638ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	49.670s	2.765ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.187m	19.148ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	7.233m	83.075ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.980s	541.654us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.175m	8.316ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.175m	8.316ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.175m	8.316ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.187m	19.148ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	49.670s	2.765ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.175m	8.316ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	3.126m	23.272ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.187m	19.148ms	50	50	100.00
V2S		TOTAL			75	75	100.00
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	56.906m	368.302ms	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			1274	1290	98.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	21	84.00
V2S	5	5	5	100.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.78	96.65	92.52	100.00	90.91	94.67	98.82	96.88

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 10 failures:

Test kmac_stress_all_with_rand_reset has 10 failures.

4.kmac_stress_all_with_rand_reset.3784145136
Line 344, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 40542561351 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 40542561351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.kmac_stress_all_with_rand_reset.764058834
Line 373, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10898118793 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 10898118793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app has 2 failures.

15.kmac_app.287866949
Line 241, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/15.kmac_app/latest/run.log

  UVM_FATAL @ 619564542 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (22 [0x16] vs 190 [0xbe]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 619564542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.kmac_app.3700032965
Line 287, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/25.kmac_app/latest/run.log

  UVM_FATAL @ 22829279129 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (198 [0xc6] vs 197 [0xc5]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 22829279129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_entropy_refresh has 1 failures.

17.kmac_entropy_refresh.1957319121
Line 381, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 16513295954 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (6 [0x6] vs 130 [0x82]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 16513295954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

33.kmac_stress_all.1837903316
Line 573, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest/run.log

  UVM_FATAL @ 119865925005 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (249 [0xf9] vs 232 [0xe8]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 119865925005 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:

Test kmac_burst_write has 2 failures.

8.kmac_burst_write.3663871249
Line 320, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.kmac_burst_write.2624678712
Line 296, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/28.kmac_burst_write/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---