KMAC/UNMASKED Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: `0c759b93ab`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.082m	4.031ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.130s	105.409us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.220s	30.146us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.350s	5.370ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	9.310s	1.824ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.070s	241.416us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.220s	30.146us	20	20	100.00
		kmac_csr_aliasing	9.310s	1.824ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	14.191us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.400s	67.146us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	47.123m	275.604ms	50	50	100.00
V2	burst_write	kmac_burst_write	12.985m	52.145ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	38.788m	1.212s	50	50	100.00
		kmac_test_vectors_sha3_256	32.025m	92.464ms	50	50	100.00
		kmac_test_vectors_sha3_384	24.962m	179.177ms	50	50	100.00
		kmac_test_vectors_sha3_512	17.816m	328.379ms	50	50	100.00
		kmac_test_vectors_shake_128	1.447h	1.064s	50	50	100.00
		kmac_test_vectors_shake_256	1.246h	1.455s	50	50	100.00
		kmac_test_vectors_kmac	5.340s	263.610us	50	50	100.00
		kmac_test_vectors_kmac_xof	5.430s	1.015ms	50	50	100.00
V2	sideload	kmac_sideload	6.825m	28.188ms	49	50	98.00
V2	app	kmac_app	6.105m	19.038ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	4.133m	44.660ms	9	10	90.00
V2	entropy_refresh	kmac_entropy_refresh	5.910m	60.817ms	49	50	98.00
V2	error	kmac_error	6.284m	36.232ms	50	50	100.00
V2	key_error	kmac_key_error	6.410s	4.239ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	48.550s	2.415ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	29.550s	1.578ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.232m	70.339ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	37.700s	1.260ms	50	50	100.00
V2	stress_all	kmac_stress_all	46.061m	422.582ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.860s	23.153us	50	50	100.00
V2	alert_test	kmac_alert_test	0.870s	39.165us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.080s	239.684us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.080s	239.684us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.130s	105.409us	5	5	100.00
		kmac_csr_rw	1.220s	30.146us	20	20	100.00
		kmac_csr_aliasing	9.310s	1.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.850s	269.914us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.130s	105.409us	5	5	100.00
		kmac_csr_rw	1.220s	30.146us	20	20	100.00
		kmac_csr_aliasing	9.310s	1.824ms	5	5	100.00
		kmac_same_csr_outstanding	2.850s	269.914us	20	20	100.00
V2		TOTAL			1043	1050	99.33
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.500s	64.208us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.500s	64.208us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.500s	64.208us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.500s	64.208us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.910s	403.611us	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.321m	6.421ms	5	5	100.00
		kmac_tl_intg_err	5.800s	1.393ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	5.800s	1.393ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	37.700s	1.260ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.082m	4.031ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	6.825m	28.188ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.500s	64.208us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.321m	6.421ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.321m	6.421ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.321m	6.421ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.082m	4.031ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	37.700s	1.260ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.321m	6.421ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.618m	23.581ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.082m	4.031ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	46.283m	53.065ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1273	1290	98.68

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	19	76.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.46	96.58	92.46	100.00	88.64	94.67	98.84	97.02

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 9 failures:
- Test kmac_stress_all_with_rand_reset has 9 failures.
  - 8.kmac_stress_all_with_rand_reset.24278169574778000771796185018009937435386519962409221635875050458595398865253
    Line 259, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  95829429 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483664 [0x80000010]) reg name: kmac_reg_block.err_code
  UVM_INFO @  95829429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.kmac_stress_all_with_rand_reset.46840048894693122253551772765758424044041872493507174435693844997364481433319
    Line 648, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/12.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 196818408558 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483760 [0x80000070]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 196818408558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 4 failures:

Test kmac_app_with_partial_data has 1 failures.

0.kmac_app_with_partial_data.53328003818102691374700679612056898505493972166835434096775734203012934369591
Line 299, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest/run.log

  UVM_FATAL @ 5918156336 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (180 [0xb4] vs 116 [0x74]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 5918156336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 2 failures.

17.kmac_stress_all.85055995471227848683739429907822338851123972019293679395560856330489800618169
Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/17.kmac_stress_all/latest/run.log

  UVM_FATAL @ 47486876969 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (148 [0x94] vs 20 [0x14]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 47486876969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.kmac_stress_all.49197070661487995616550600123887094324276496934086307239827257291302507424934
Line 367, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/33.kmac_stress_all/latest/run.log

  UVM_FATAL @ 3746229616 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (187 [0xbb] vs 127 [0x7f]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 3746229616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

43.kmac_app.38913590339291627044431016709884502365799234127230690126995920270377468673170
Line 393, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/43.kmac_app/latest/run.log

  UVM_FATAL @ 18397109787 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (191 [0xbf] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18397109787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_entropy_refresh has 1 failures.
  - 2.kmac_entropy_refresh.114203729399326052668628200743573612160526861394691412326343737561228372439826
    Line 360, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/2.kmac_entropy_refresh/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_sideload has 1 failures.
  - 34.kmac_sideload.55617312245093974993775286573192765388082367802444971544715368807171446945326
    Line 430, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/34.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 6.kmac_shadow_reg_errors_with_csr_rw.4152041445393437522374296604565780809404580433356072126961132843021388281096
    Line 264, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @ 296528641 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (3106857232 [0xb92ee110] vs 0 [0x0]) Regname: kmac_reg_block.prefix_5.prefix_0 reset value: 0x0
  UVM_INFO @ 296528641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 41.kmac_key_error.41857726436012782711939622943841264966889384719302646385479406778675141283975
    Line 273, in log /container/opentitan-public/scratch/os_regression/kmac_unmasked-sim-vcs/41.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 5815245632 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 5815245632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```