Unified Coverage Report :: Module :: sha3pad

Module : sha3pad

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3.u_pad	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3.u_pad

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_sha3

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prefix_slicer	0.00	0.00
u_sentmsg_count	0.00			0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
TOTAL		162	0	0.00
ALWAYS	157	6	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	257	1	0	0.00
ALWAYS	267	6	0	0.00
ALWAYS	279	3	0	0.00
CONT_ASSIGN	286	1	0	0.00
ALWAYS	293	3	0	0.00
ALWAYS	298	76	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	520	1	0	0.00
CONT_ASSIGN	541	1	0	0.00
ALWAYS	558	4	0	0.00
CONT_ASSIGN	581	1	0	0.00
CONT_ASSIGN	588	1	0	0.00
ALWAYS	591	5	0	0.00
ALWAYS	603	5	0	0.00
ALWAYS	615	5	0	0.00
ALWAYS	664	10	0	0.00
ALWAYS	719	9	0	0.00
ALWAYS	779	6	0	0.00
ALWAYS	788	6	0	0.00
ALWAYS	798	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
209	0	1
213	0	1
236	0	1
242	0	1
247	0	1
257	0	1
267	0	1
268	0	1
269	0	1
270	0	1
271	0	1
272	0	1
			==> MISSING_ELSE
279	0	3
286	0	1
293	0	2
294	0	1
298	0	1
301	0	1
302	0	1
304	0	1
306	0	1
307	0	1
309	0	1
310	0	1
312	0	1
314	0	1
316	0	1
325	0	1
327	0	1
328	0	1
330	0	1
333	0	1
345	0	1
347	0	1
348	0	1
350	0	1
351	0	1
352	0	1
354	0	1
356	0	1
361	0	1
363	0	1
364	0	1
366	0	1
375	0	1
377	0	1
378	0	1
380	0	1
381	0	1
383	0	1
385	0	1
386	0	1
387	0	1
388	0	1
389	0	1
392	0	1
394	0	1
400	0	1
402	0	1
403	0	1
405	0	1
414	0	1
416	0	1
418	0	1
421	0	1
424	0	1
425	0	1
426	0	1
427	0	1
428	0	1
430	0	1
435	0	1
437	0	1
438	0	1
447	0	1
451	0	1
452	0	1
454	0	1
455	0	1
456	0	1
458	0	1
460	0	1
466	0	1
467	0	1
469	0	1
470	0	1
472	0	1
474	0	1
480	0	1
481	0	1
494	0	1
495	0	1
			==> MISSING_ELSE
509	0	1
520	0	1
541	0	1
558	0	1
559	0	1
560	0	1
561	0	1
581	0	1
588	0	1
591	0	1
592	0	1
593	0	1
594	0	1
595	0	1
603	0	1
604	0	1
605	0	1
606	0	1
607	0	1
615	0	1
616	0	1
617	0	1
618	0	1
619	0	1
664	0	1
665	0	1
666	0	1
667	0	1
668	0	1
669	0	1
671	0	1
672	0	1
673	0	1
674	0	1
			==> MISSING_ELSE
719	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
727	0	1
779	0	1
780	0	1
781	0	1
782	0	1
783	0	1
784	0	1
			==> MISSING_ELSE
788	0	1
789	0	1
790	0	1
791	0	1
792	0	1
793	0	1
			==> MISSING_ELSE
798	0	1
799	0	1
800	0	1
801	0	1
802	0	1
803	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : sha3pad

	Total	Covered	Percent
Conditions	43	0	0.00
Logical	43	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Module : sha3pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	21	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Not Covered
StMessageWait	383	Not Covered
StPad	389	Not Covered
StPad01	427	Not Covered
StPadFlush	435	Not Covered
StPadIdle	333	Not Covered
StPadRun	421	Not Covered
StPrefix	328	Not Covered
StPrefixWait	348	Not Covered
StTerminalError	495	Not Covered

transitions	Line No.	Covered	Tests
StMessage->StMessageWait	383	Not Covered
StMessage->StPad	389	Not Covered
StMessage->StTerminalError	495	Not Covered
StMessageWait->StMessage	403	Not Covered
StMessageWait->StTerminalError	495	Not Covered
StPad->StPad01	427	Not Covered
StPad->StPadRun	421	Not Covered
StPad->StTerminalError	495	Not Covered
StPad01->StPadFlush	452	Not Covered
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Not Covered
StPadFlush->StTerminalError	495	Not Covered
StPadIdle->StMessage	330	Not Covered
StPadIdle->StPrefix	328	Not Covered
StPadIdle->StTerminalError	495	Not Covered
StPadRun->StPadFlush	435	Not Covered
StPadRun->StTerminalError	495	Not Covered
StPrefix->StPrefixWait	348	Not Covered
StPrefix->StTerminalError	495	Not Covered
StPrefixWait->StMessage	364	Not Covered
StPrefixWait->StTerminalError	495	Not Covered

---

Branch Coverage for Module : sha3pad

	Line No.	Total	Covered	Percent
Branches		93	0	0.00
TERNARY	213	2	0	0.00
TERNARY	236	2	0	0.00
TERNARY	242	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	588	2	0	0.00
CASE	157	6	0	0.00
IF	267	4	0	0.00
IF	279	2	0	0.00
IF	293	2	0	0.00
CASE	316	23	0	0.00
IF	494	2	0	0.00
CASE	558	4	0	0.00
CASE	591	5	0	0.00
CASE	603	5	0	0.00
CASE	615	5	0	0.00
IF	664	4	0	0.00
IF	779	4	0	0.00
IF	788	4	0	0.00
IF	798	4	0	0.00
CASE	719	9	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Not Covered
L224	Not Covered
L256	Not Covered
L384	Not Covered
L512	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Not Covered
Shake	Not Covered
CShake	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Not Covered
7'b0000001	Not Covered
7'b0000011	Not Covered
7'b0000111	Not Covered
7'b0001111	Not Covered
7'b0011111	Not Covered
7'b0111111	Not Covered
7'b1111111	Not Covered
default	Not Covered

Line Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
TOTAL		162	0	0.00
ALWAYS	157	6	0	0.00
CONT_ASSIGN	209	1	0	0.00
CONT_ASSIGN	213	1	0	0.00
CONT_ASSIGN	236	1	0	0.00
CONT_ASSIGN	242	1	0	0.00
CONT_ASSIGN	247	1	0	0.00
CONT_ASSIGN	257	1	0	0.00
ALWAYS	267	6	0	0.00
ALWAYS	279	3	0	0.00
CONT_ASSIGN	286	1	0	0.00
ALWAYS	293	3	0	0.00
ALWAYS	298	76	0	0.00
CONT_ASSIGN	509	1	0	0.00
CONT_ASSIGN	520	1	0	0.00
CONT_ASSIGN	541	1	0	0.00
ALWAYS	558	4	0	0.00
CONT_ASSIGN	581	1	0	0.00
CONT_ASSIGN	588	1	0	0.00
ALWAYS	591	5	0	0.00
ALWAYS	603	5	0	0.00
ALWAYS	615	5	0	0.00
ALWAYS	664	10	0	0.00
ALWAYS	719	9	0	0.00
ALWAYS	779	6	0	0.00
ALWAYS	788	6	0	0.00
ALWAYS	798	6	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
209	0	1
213	0	1
236	0	1
242	0	1
247	0	1
257	0	1
267	0	1
268	0	1
269	0	1
270	0	1
271	0	1
272	0	1
			==> MISSING_ELSE
279	0	3
286	0	1
293	0	2
294	0	1
298	0	1
301	0	1
302	0	1
304	0	1
306	0	1
307	0	1
309	0	1
310	0	1
312	0	1
314	0	1
316	0	1
325	0	1
327	0	1
328	0	1
330	0	1
333	0	1
345	0	1
347	0	1
348	0	1
350	0	1
351	0	1
352	0	1
354	0	1
356	0	1
361	0	1
363	0	1
364	0	1
366	0	1
375	0	1
377	0	1
378	0	1
380	0	1
381	0	1
383	0	1
385	0	1
386	0	1
387	0	1
388	0	1
389	0	1
392	0	1
394	0	1
400	0	1
402	0	1
403	0	1
405	0	1
414	0	1
416	0	1
418	0	1
421	0	1
424	0	1
425	0	1
426	0	1
427	0	1
428	0	1
430	0	1
435	0	1
437	0	1
438	0	1
447	0	1
451	0	1
452	0	1
454	0	1
455	0	1
456	0	1
458	0	1
460	0	1
466	0	1
467	0	1
469	0	1
470	0	1
472	0	1
474	0	1
480	0	1
481	0	1
494	0	1
495	0	1
			==> MISSING_ELSE
509	0	1
520	0	1
541	0	1
558	0	1
559	0	1
560	0	1
561	0	1
581	0	1
588	0	1
591	0	1
592	0	1
593	0	1
594	0	1
595	0	1
603	0	1
604	0	1
605	0	1
606	0	1
607	0	1
615	0	1
616	0	1
617	0	1
618	0	1
619	0	1
664	0	1
665	0	1
666	0	1
667	0	1
668	0	1
669	0	1
671	0	1
672	0	1
673	0	1
674	0	1
			==> MISSING_ELSE
719	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
727	0	1
779	0	1
780	0	1
781	0	1
782	0	1
783	0	1
784	0	1
			==> MISSING_ELSE
788	0	1
789	0	1
790	0	1
791	0	1
792	0	1
793	0	1
			==> MISSING_ELSE
798	0	1
799	0	1
800	0	1
801	0	1
802	0	1
803	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3.u_pad

	Total	Covered	Percent
Conditions	43	0	0.00
Logical	43	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       209
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       213
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       236
 EXPRESSION ((mode_i == CShake) ? 1'b1 : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       236
 SUB-EXPRESSION (mode_i == CShake)
                ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       242
 EXPRESSION ((sent_message == block_addr_limit) ? 1'b1 : 1'b0)
             -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       242
 SUB-EXPRESSION (sent_message == block_addr_limit)
                -----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       247
 EXPRESSION (keccak_valid_o & keccak_ready_i)
             -------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       257
 EXPRESSION ((&msg_strb_i) != 1'b1)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 EXPRESSION (((sent_message + 1'b1) == block_addr_limit) ? 1'b1 : 1'b0)
             ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       286
 SUB-EXPRESSION ((sent_message + 1'b1) == block_addr_limit)
                ---------------------1---------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       377
 EXPRESSION (msg_valid_i && msg_partial)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       388
 EXPRESSION (process_latched || process_i)
             -------1-------    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       418
 EXPRESSION (keccak_ack && end_of_block)
             -----1----    ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       588
 EXPRESSION ((sent_message < block_addr_limit) ? sent_message : '0)
             ----------------1----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       604
 EXPRESSION (msg_valid_i & ((~hold_msg)) & ((~en_msgbuf)))
             -----1-----   ------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       616
 EXPRESSION (en_msgbuf | (keccak_ready_i & ((~hold_msg))))
             ----1----   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       616
 SUB-EXPRESSION (keccak_ready_i & ((~hold_msg)))
                 -------1------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3.u_pad

Summary for FSM :: st

	Total	Covered	Percent
States	10	0	0.00	(Not included in score)
Transitions	17	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StMessage	330	Not Covered
StMessageWait	383	Not Covered
StPad	389	Not Covered
StPad01	427	Not Covered
StPadFlush	435	Not Covered
StPadIdle	333	Not Covered
StPadRun	421	Not Covered
StPrefix	328	Not Covered
StPrefixWait	348	Not Covered
StTerminalError	495	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
StMessage->StMessageWait	383	Not Covered
StMessage->StPad	389	Not Covered
StMessage->StTerminalError	495	Not Covered
StMessageWait->StMessage	403	Not Covered
StMessageWait->StTerminalError	495	Not Covered
StPad->StPad01	427	Not Covered
StPad->StPadRun	421	Not Covered
StPad->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPad01->StPadFlush	452	Not Covered
StPad01->StTerminalError	495	Not Covered
StPadFlush->StPadIdle	470	Not Covered
StPadFlush->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPadIdle->StMessage	330	Not Covered
StPadIdle->StPrefix	328	Not Covered
StPadIdle->StTerminalError	495	Not Covered
StPadRun->StPadFlush	435	Not Covered
StPadRun->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefix->StPrefixWait	348	Not Covered
StPrefix->StTerminalError	495	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StPrefixWait->StMessage	364	Not Covered
StPrefixWait->StTerminalError	495	Not Covered

---

Branch Coverage for Instance : tb.dut.u_sha3.u_pad

	Line No.	Total	Covered	Percent
Branches		93	0	0.00
TERNARY	213	2	0	0.00
TERNARY	236	2	0	0.00
TERNARY	242	2	0	0.00
TERNARY	286	2	0	0.00
TERNARY	588	2	0	0.00
CASE	157	6	0	0.00
IF	267	4	0	0.00
IF	279	2	0	0.00
IF	293	2	0	0.00
CASE	316	23	0	0.00
IF	494	2	0	0.00
CASE	558	4	0	0.00
CASE	591	5	0	0.00
CASE	603	5	0	0.00
CASE	615	5	0	0.00
IF	664	4	0	0.00
IF	779	4	0	0.00
IF	788	4	0	0.00
IF	798	4	0	0.00
CASE	719	9	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3pad.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	213	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	236	((mode_i == CShake)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	242	((sent_message == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	286	(((sent_message + 1'b1) == block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	588	((sent_message < block_addr_limit)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	157	case (strength_i)

Branches:

-1-	Status	Tests
L128	Not Covered
L224	Not Covered
L256	Not Covered
L384	Not Covered
L512	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	267	if ((!rst_ni))
-2-:	269	if (process_i)
-3-:	271	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	279	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	293	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	316	case (st)
-2-:	325	if (start_i)
-3-:	327	if (mode_eq_cshake)
-4-:	347	if (sent_blocksize)
-5-:	363	if (keccak_complete_i)
-6-:	377	if ((msg_valid_i && msg_partial))
-7-:	381	if (sent_blocksize)
-8-:	388	if ((process_latched || process_i))
-9-:	402	if (keccak_complete_i)
-10-:	418	if ((keccak_ack && end_of_block))
-11-:	426	if (keccak_ack)
-12-:	451	if (sent_blocksize)
-13-:	469	if (keccak_complete_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	Status	Tests
StPadIdle	1	1	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	1	0	-	-	-	-	-	-	-	-	-	-	Not Covered
StPadIdle	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	1	-	-	-	-	-	-	-	-	-	Not Covered
StPrefix	-	-	0	-	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	1	-	-	-	-	-	-	-	-	Not Covered
StPrefixWait	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	1	-	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	1	-	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	1	-	-	-	-	-	Not Covered
StMessage	-	-	-	-	0	0	0	-	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	1	-	-	-	-	Not Covered
StMessageWait	-	-	-	-	-	-	-	0	-	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	1	-	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	1	-	-	Not Covered
StPad	-	-	-	-	-	-	-	-	0	0	-	-	Not Covered
StPadRun	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	1	-	Not Covered
StPad01	-	-	-	-	-	-	-	-	-	-	0	-	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	1	Not Covered
StPadFlush	-	-	-	-	-	-	-	-	-	-	-	0	Not Covered
StTerminalError	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	494	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	558	case (mode_i)

Branches:

-1-	Status	Tests
Sha3	Not Covered
Shake	Not Covered
CShake	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	591	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	603	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	615	case (sel_mux)

Branches:

-1-	Status	Tests
MuxFifo	Not Covered
MuxPrefix	Not Covered
MuxFuncPad	Not Covered
MuxZeroEnd	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	664	if ((!rst_ni))
-2-:	667	if (en_msgbuf)
-3-:	672	if (clr_msgbuf)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	779	if ((!rst_ni))
-2-:	781	if (start_i)
-3-:	783	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	788	if ((!rst_ni))
-2-:	790	if (start_i)
-3-:	792	if (process_i)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	798	if ((!rst_ni))
-2-:	800	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed_o))
-3-:	802	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	719	case (msg_strb)

Branches:

-1-	Status	Tests
7'b0000000	Not Covered
7'b0000001	Not Covered
7'b0000011	Not Covered
7'b0000111	Not Covered
7'b0001111	Not Covered
7'b0011111	Not Covered
7'b0111111	Not Covered
7'b1111111	Not Covered
default	Not Covered