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NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
intr_fifo_empty 0.00 0.00 0.00 0.00
intr_kmac_done 0.00 0.00 0.00 0.00
intr_kmac_err 0.00 0.00 0.00 0.00
kmac_csr_assert 100.00 100.00
tlul_assert_device 33.33 0.00 0.00 100.00
u_app_intf 0.00 0.00 0.00 0.00 0.00
u_appid_arb 0.00 0.00 0.00 0.00
u_prim_buf_state_err_check 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_buf_state_kmac_sel 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_buf_state_output_sel 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_buf_state_output_valid 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_errchk 0.00 0.00 0.00 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_kmac_core 0.00 0.00 0.00 0.00 0.00 0.00
gen_key_slicer[0].u_key_slicer 0.00 0.00
u_key_index_count 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_msgfifo 0.00 0.00 0.00 0.00 0.00
u_msgfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_packer 0.00 0.00 0.00 0.00
u_prim_lc_sync 0.00 0.00 0.00
gen_buffs[0].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[2].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[2].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[2].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[2].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[3].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[3].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[3].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[3].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[4].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[4].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[4].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[4].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[5].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[5].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[5].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[5].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_flops.u_prim_flop_2sync 0.00 0.00 0.00
u_sync_1 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_reg 94.28 98.97 96.31 77.47 98.63 100.00
subtree...
u_sha3 0.00 0.00 0.00 0.00 0.00 0.00
u_keccak 0.00 0.00 0.00 0.00 0.00 0.00
u_keccak_p 0.00 0.00 0.00 0.00
u_prim_sec_anchor_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_round_count 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_pad 0.00 0.00 0.00 0.00 0.00 0.00
u_prefix_slicer 0.00 0.00
u_sentmsg_count 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sha3_done_sender 0.00 0.00 0.00
gen_prim_buf.u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_staterd 0.00 0.00 0.00 0.00
gen_slicer[0].u_state_slice 0.00 0.00
u_tlul_adapter 0.00 0.00 0.00 0.00
u_err 0.00 0.00 0.00 0.00
u_reqfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_rsp_gen 0.00 0.00
u_rspfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_sram_byte 0.00 0.00
u_sramreqfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_tlul_data_integ_enc_data 0.00 0.00
u_data_gen 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00
u_data_gen 0.00 0.00
u_tlul_adapter_msgfifo 0.00 0.00 0.00 0.00
u_err 0.00 0.00 0.00 0.00
u_reqfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_rsp_gen 0.00 0.00
u_rspfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_sram_byte 0.00 0.00
u_sramreqfifo 0.00 0.00 0.00 0.00
gen_normal_fifo.u_fifo_cnt 0.00 0.00 0.00
u_tlul_data_integ_enc_data 0.00 0.00
u_data_gen 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00
u_data_gen 0.00 0.00
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