Unified Coverage Report :: Module :: sha3

Module : sha3

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sha3	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_sha3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_keccak	0.00	0.00	0.00	0.00	0.00	0.00
u_pad	0.00	0.00	0.00	0.00	0.00	0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : sha3

	Line No.	Total	Covered	Percent
TOTAL		82	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
CONT_ASSIGN	173	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	179	1	0	0.00
ALWAYS	184	5	0	0.00
ALWAYS	198	3	0	0.00
CONT_ASSIGN	203	1	0	0.00
ALWAYS	207	6	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	220	1	0	0.00
ALWAYS	227	3	0	0.00
ALWAYS	237	38	0	0.00
ALWAYS	332	3	0	0.00
ALWAYS	349	12	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
144	0	1
148	0	1
172	0	1
173	0	1
178	0	1
179	0	1
184	0	1
185	0	1
186	0	1
188	0	1
189	0	1
198	0	2
199	0	1
203	0	1
207	0	2
208	0	2
209	0	1
210	0	1
			==> MISSING_ELSE
214	0	1
217	0	1
218	0	1
220	0	1
227	0	3
237	0	1
240	0	1
241	0	1
242	0	1
243	0	1
245	0	1
247	0	1
248	0	1
250	0	1
252	0	1
254	0	1
255	0	1
257	0	1
259	0	1
264	0	1
265	0	1
267	0	1
268	0	1
269	0	1
271	0	1
276	0	1
277	0	1
279	0	1
281	0	1
282	0	1
284	0	1
285	0	1
286	0	1
288	0	1
290	0	1
295	0	1
296	0	1
298	0	1
303	0	1
308	0	1
309	0	1
321	0	1
322	0	1
			==> MISSING_ELSE
332	0	1
333	0	1
334	0	1
349	0	1
351	0	1
353	0	1
355	0	1
			==> MISSING_ELSE
364	0	1
366	0	1
			==> MISSING_ELSE
375	0	1
376	0	1
			==> MISSING_ELSE
385	0	1
387	0	1
			==> MISSING_ELSE
396	0	1
398	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : sha3

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Module : sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	11	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Not Covered
StFlush_sparse	286	Not Covered
StIdle_sparse	259	Not Covered
StManualRun_sparse	282	Not Covered
StSqueeze_sparse	269	Not Covered
StTerminalError_sparse	308	Not Covered

transitions	Line No.	Covered	Tests
StAbsorb_sparse->StSqueeze_sparse	269	Not Covered
StAbsorb_sparse->StTerminalError_sparse	322	Not Covered
StFlush_sparse->StIdle_sparse	303	Not Covered
StFlush_sparse->StTerminalError_sparse	322	Not Covered
StIdle_sparse->StAbsorb_sparse	255	Not Covered
StIdle_sparse->StTerminalError_sparse	322	Not Covered
StManualRun_sparse->StSqueeze_sparse	296	Not Covered
StManualRun_sparse->StTerminalError_sparse	322	Not Covered
StSqueeze_sparse->StFlush_sparse	286	Not Covered
StSqueeze_sparse->StManualRun_sparse	282	Not Covered
StSqueeze_sparse->StTerminalError_sparse	322	Not Covered

---

Branch Coverage for Module : sha3

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	173	3	0	0.00
TERNARY	179	3	0	0.00
IF	184	2	0	0.00
IF	198	2	0	0.00
IF	207	4	0	0.00
IF	227	2	0	0.00
CASE	252	13	0	0.00
IF	321	2	0	0.00
CASE	332	3	0	0.00
CASE	351	11	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	173	((sha3pad_keccak_run || sw_keccak_run)) ? 
-2-:	173	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	179	(keccak_run) ? 
-2-:	179	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	198	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	208	if (process_i)
-3-:	209	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	252	case (st)
-2-:	254	if (start_i)
-3-:	264	if ((process_i && (!processing)))
-4-:	268	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	281	if (run_i)
-6-:	285	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	295	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	-	Not Covered
StAbsorb_sparse	-	0	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	-	0	1	-	Not Covered
StSqueeze_sparse	-	-	-	0	0	-	Not Covered
StManualRun_sparse	-	-	-	-	-	1	Not Covered
StManualRun_sparse	-	-	-	-	-	0	Not Covered
StFlush_sparse	-	-	-	-	-	-	Not Covered
StTerminalError_sparse	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	332	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Not Covered
MuxRelease	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	351	case (st)
-2-:	353	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	364	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	375	if ((start_i || process_i))
-5-:	385	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	396	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Not Covered
StManualRun_sparse	-	-	-	1	-	Not Covered
StManualRun_sparse	-	-	-	0	-	Not Covered
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
TOTAL		82	0	0.00
CONT_ASSIGN	138	1	0	0.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	148	1	0	0.00
CONT_ASSIGN	172	1	0	0.00
CONT_ASSIGN	173	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	179	1	0	0.00
ALWAYS	184	5	0	0.00
ALWAYS	198	3	0	0.00
CONT_ASSIGN	203	1	0	0.00
ALWAYS	207	6	0	0.00
CONT_ASSIGN	214	1	0	0.00
CONT_ASSIGN	217	1	0	0.00
CONT_ASSIGN	218	1	0	0.00
CONT_ASSIGN	220	1	0	0.00
ALWAYS	227	3	0	0.00
ALWAYS	237	38	0	0.00
ALWAYS	332	3	0	0.00
ALWAYS	349	12	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
138	0	1
144	0	1
148	0	1
172	0	1
173	0	1
178	0	1
179	0	1
184	0	1
185	0	1
186	0	1
188	0	1
189	0	1
198	0	2
199	0	1
203	0	1
207	0	2
208	0	2
209	0	1
210	0	1
			==> MISSING_ELSE
214	0	1
217	0	1
218	0	1
220	0	1
227	0	3
237	0	1
240	0	1
241	0	1
242	0	1
243	0	1
245	0	1
247	0	1
248	0	1
250	0	1
252	0	1
254	0	1
255	0	1
257	0	1
259	0	1
264	0	1
265	0	1
267	0	1
268	0	1
269	0	1
271	0	1
276	0	1
277	0	1
279	0	1
281	0	1
282	0	1
284	0	1
285	0	1
286	0	1
288	0	1
290	0	1
295	0	1
296	0	1
298	0	1
303	0	1
308	0	1
309	0	1
321	0	1
322	0	1
			==> MISSING_ELSE
332	0	1
333	0	1
334	0	1
349	0	1
351	0	1
353	0	1
355	0	1
			==> MISSING_ELSE
364	0	1
366	0	1
			==> MISSING_ELSE
375	0	1
376	0	1
			==> MISSING_ELSE
385	0	1
387	0	1
			==> MISSING_ELSE
396	0	1
398	0	1
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sha3

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       138
 EXPRESSION (round_count_error | msg_count_error)
             --------1--------   -------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       144
 EXPRESSION (sha3_state_error | keccak_round_state_error | sha3pad_state_error)
             --------1-------   ------------2-----------   ---------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       173
 EXPRESSION ((sha3pad_keccak_run || sw_keccak_run) ? 1'b1 : (keccak_complete ? 1'b0 : keccak_run_req_q))
             ------------------1------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       173
 SUB-EXPRESSION (sha3pad_keccak_run || sw_keccak_run)
                 ---------1--------    ------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       173
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_run_req_q)
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       178
 EXPRESSION (run_req_o & run_ack_i & ((~keccak_triggered_q)))
             ----1----   ----2----   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Unreachable
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       179
 EXPRESSION (keccak_run ? 1'b1 : (keccak_complete ? 1'b0 : keccak_triggered_q))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       179
 SUB-EXPRESSION (keccak_complete ? 1'b0 : keccak_triggered_q)
                 -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       264
 EXPRESSION (process_i && ((!processing)))
             ----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       375
 EXPRESSION (start_i || process_i)
             ---1---    ----2----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

FSM Coverage for Instance : tb.dut.u_sha3

Summary for FSM :: st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	9	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: st

---

states	Line No.	Covered	Tests
StAbsorb_sparse	255	Not Covered
StFlush_sparse	286	Not Covered
StIdle_sparse	259	Not Covered
StManualRun_sparse	282	Not Covered
StSqueeze_sparse	269	Not Covered
StTerminalError_sparse	308	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
StAbsorb_sparse->StSqueeze_sparse	269	Not Covered
StAbsorb_sparse->StTerminalError_sparse	322	Not Covered
StFlush_sparse->StIdle_sparse	303	Not Covered
StFlush_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StIdle_sparse->StAbsorb_sparse	255	Not Covered
StIdle_sparse->StTerminalError_sparse	322	Not Covered
StManualRun_sparse->StSqueeze_sparse	296	Not Covered
StManualRun_sparse->StTerminalError_sparse	322	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
StSqueeze_sparse->StFlush_sparse	286	Not Covered
StSqueeze_sparse->StManualRun_sparse	282	Not Covered
StSqueeze_sparse->StTerminalError_sparse	322	Not Covered

---

Branch Coverage for Instance : tb.dut.u_sha3

	Line No.	Total	Covered	Percent
Branches		45	0	0.00
TERNARY	173	3	0	0.00
TERNARY	179	3	0	0.00
IF	184	2	0	0.00
IF	198	2	0	0.00
IF	207	4	0	0.00
IF	227	2	0	0.00
CASE	252	13	0	0.00
IF	321	2	0	0.00
CASE	332	3	0	0.00
CASE	351	11	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv' or '../src/lowrisc_ip_sha3_0.1/rtl/sha3.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	173	((sha3pad_keccak_run || sw_keccak_run)) ? 
-2-:	173	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	179	(keccak_run) ? 
-2-:	179	(keccak_complete) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	184	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	198	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	207	if ((!rst_ni))
-2-:	208	if (process_i)
-3-:	209	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	227	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	252	case (st)
-2-:	254	if (start_i)
-3-:	264	if ((process_i && (!processing)))
-4-:	268	if (prim_mubi_pkg::mubi4_test_true_strict(absorbed))
-5-:	281	if (run_i)
-6-:	285	if (prim_mubi_pkg::mubi4_test_true_strict(done_i))
-7-:	295	if (keccak_complete)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	Status	Tests
StIdle_sparse	1	-	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	-	Not Covered
StAbsorb_sparse	-	0	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	-	0	1	-	Not Covered
StSqueeze_sparse	-	-	-	0	0	-	Not Covered
StManualRun_sparse	-	-	-	-	-	1	Not Covered
StManualRun_sparse	-	-	-	-	-	0	Not Covered
StFlush_sparse	-	-	-	-	-	-	Not Covered
StTerminalError_sparse	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	321	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	332	case (mux_sel)

Branches:

-1-	Status	Tests
MuxGuard	Not Covered
MuxRelease	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	351	case (st)
-2-:	353	if (((process_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-3-:	364	if ((((start_i || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)) || (process_i && processing)))
-4-:	375	if ((start_i || process_i))
-5-:	385	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))
-6-:	396	if ((((start_i || process_i) || run_i) || prim_mubi_pkg::mubi4_test_true_loose(done_i)))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StIdle_sparse	1	-	-	-	-	Not Covered
StIdle_sparse	0	-	-	-	-	Not Covered
StAbsorb_sparse	-	1	-	-	-	Not Covered
StAbsorb_sparse	-	0	-	-	-	Not Covered
StSqueeze_sparse	-	-	1	-	-	Not Covered
StSqueeze_sparse	-	-	0	-	-	Not Covered
StManualRun_sparse	-	-	-	1	-	Not Covered
StManualRun_sparse	-	-	-	0	-	Not Covered
StFlush_sparse	-	-	-	-	1	Not Covered
StFlush_sparse	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered