Unified Coverage Report :: Module :: kmac

Module : kmac

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.11	0.00	0.00	5.54	0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	1.74	0.00	0.00	8.70	0.00	0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
1.74	0.00	0.00	8.70	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
45.20	46.89	61.77	16.56	0.00	45.98	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
intr_fifo_empty	0.00	0.00	0.00			0.00
intr_kmac_done	0.00	0.00	0.00			0.00
intr_kmac_err	0.00	0.00	0.00			0.00
kmac_csr_assert	100.00						100.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_app_intf	0.00	0.00	0.00		0.00	0.00
u_errchk	0.00	0.00	0.00		0.00	0.00
u_kmac_core	0.00	0.00	0.00	0.00	0.00	0.00
u_msgfifo	0.00	0.00	0.00		0.00	0.00
u_prim_lc_sync	0.00	0.00				0.00
u_reg	94.39	98.94	96.80	77.47		98.72	100.00
u_sha3	0.00	0.00	0.00	0.00	0.00	0.00
u_sha3_done_sender	0.00	0.00				0.00
u_state_regs	0.00	0.00				0.00
u_staterd	0.00	0.00	0.00			0.00
u_tlul_adapter_msgfifo	0.00	0.00	0.00			0.00

Line Coverage for Module : kmac

	Line No.	Total	Covered	Percent
TOTAL		161	0	0.00
ALWAYS	346	0	0
ALWAYS	346	2	0	0.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
ALWAYS	429	9	0	0.00
CONT_ASSIGN	464	1	0	0.00
CONT_ASSIGN	465	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	469	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
ALWAYS	488	6	0	0.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	528	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	532	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	535	1	0	0.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	0	0.00
CONT_ASSIGN	543	1	0	0.00
CONT_ASSIGN	545	1	0	0.00
CONT_ASSIGN	546	1	0	0.00
CONT_ASSIGN	549	1	0	0.00
CONT_ASSIGN	550	1	0	0.00
CONT_ASSIGN	553	1	0	0.00
ALWAYS	561	5	0	0.00
CONT_ASSIGN	571	1	0	0.00
CONT_ASSIGN	577	1	0	0.00
CONT_ASSIGN	578	1	0	0.00
CONT_ASSIGN	579	1	0	0.00
CONT_ASSIGN	587	1	0	0.00
CONT_ASSIGN	629	1	0	0.00
CONT_ASSIGN	635	1	0	0.00
CONT_ASSIGN	643	1	0	0.00
CONT_ASSIGN	648	1	0	0.00
ALWAYS	651	5	0	0.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	684	1	0	0.00
ALWAYS	687	7	0	0.00
CONT_ASSIGN	723	1	0	0.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	0	0.00
CONT_ASSIGN	745	1	0	0.00
ALWAYS	765	3	0	0.00
ALWAYS	769	28	0	0.00
CONT_ASSIGN	920	1	0	0.00
CONT_ASSIGN	923	1	0	0.00
CONT_ASSIGN	992	1	0	0.00
CONT_ASSIGN	994	1	0	0.00
CONT_ASSIGN	1029	1	0	0.00
CONT_ASSIGN	1034	1	0	0.00
CONT_ASSIGN	1035	1	0	0.00
CONT_ASSIGN	1037	1	0	0.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	0	0.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	0	0.00
CONT_ASSIGN	1317	1	0	0.00
CONT_ASSIGN	1327	1	0	0.00
CONT_ASSIGN	1328	1	0	0.00
CONT_ASSIGN	1334	1	0	0.00
CONT_ASSIGN	1335	1	0	0.00
CONT_ASSIGN	1336	1	0	0.00
CONT_ASSIGN	1337	1	0	0.00
CONT_ASSIGN	1340	1	0	0.00
CONT_ASSIGN	1349	1	0	0.00
CONT_ASSIGN	1391	1	0	0.00
CONT_ASSIGN	1405	1	0	0.00
CONT_ASSIGN	1412	1	0	0.00
CONT_ASSIGN	1417	1	0	0.00
ALWAYS	1423	6	0	0.00
CONT_ASSIGN	1432	1	0	0.00
CONT_ASSIGN	1434	1	0	0.00
ALWAYS	1446	4	0	0.00
CONT_ASSIGN	1452	1	0	0.00
ALWAYS	1475	4	0	0.00
ALWAYS	1485	3	0	0.00
CONT_ASSIGN	1496	1	0	0.00
CONT_ASSIGN	1500	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	0	1
347	0	1
352	0	1
421	0	1
422	0	1
426	0	1
429	0	1
430	0	1
431	0	1
432	0	1
434	0	1
436	0	1
440	0	1
444	0	1
448	0	1
464	0	1
465	0	1
466	0	1
469	0	1
473	0	1
474	0	1
478	0	1
481	0	1
488	0	1
489	0	1
490	0	1
491	0	1
492	0	1
493	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
513	0	1
518	0	1
525	0	1
528	0	1
529	0	1
530	0	1
532	0	1
533	0	1
535	0	1
537		unreachable
539	0	1
543	0	1
545	0	1
546	0	1
549	0	1
550	0	1
553	0	1
561	0	1
562	0	1
563	0	1
564	0	1
566	0	1
571	0	1
577	0	1
578	0	1
579	0	1
587	0	1
629	0	1
635	0	1
643	0	1
648	0	1
651	0	1
652	0	1
653	0	1
655	0	1
656	0	1
679	0	1
684	0	1
687	0	1
689	0	1
694	0	1
698	0	1
702	0	1
706	0	1
710	0	1
723	0	1
728	0	1
735	0	1
745	0	1
765	0	3
769	0	1
771	0	1
772	0	1
774	0	1
776	0	1
778	0	1
779	0	1
782	0	1
785	0	1
791	0	1
792	0	1
794	0	1
799	0	1
800	0	1
801	0	1
803	0	1
809	0	1
814	0	1
815	0	1
817	0	1
819	0	1
825	0	1
826	0	1
828	0	1
834	0	1
835	0	1
847	0	1
848	0	1
			==> MISSING_ELSE
920	0	1
923	0	1
992	0	1
994	0	1
1029	0	1
1034	0	1
1035	0	1
1037	0	1
1040		unreachable
1161	0	1
1162	0	1
1315	0	1
1316	0	1
1317	0	1
1327	0	1
1328	0	1
1334	0	1
1335	0	1
1336	0	1
1337	0	1
1340	0	1
1349	0	1
1391	0	1
1405	0	1
1412	0	1
1417	0	1
1423	0	1
1424	0	1
1425	0	1
1426	0	1
1427	0	1
1428	0	1
			==> MISSING_ELSE
1432	0	1
1434	0	1
1446	0	1
1447	0	1
1448	0	1
1449	0	1
			==> MISSING_ELSE
1452	0	1
1475	0	1
1476	0	1
1477	0	1
1479	0	1
			==> MISSING_ELSE
1485	0	1
1486	0	1
1489	0	1
1496	0	1
1500	0	1
1502	0	6

---

Cond Coverage for Module : kmac

	Total	Covered	Percent
Conditions	90	0	0.00
Logical	90	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Module : kmac

	Total	Covered	Percent
Totals	71	38	53.52
Total Bits	6534	362	5.54
Total Bits 0->1	3267	181	5.54
Total Bits 1->0	3267	181	5.54

Ports	71	38	53.52
Port Bits	6534	362	5.54
Port Bits 0->1	3267	181	5.54
Port Bits 1->0	3267	181	5.54

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T5,T8	Yes	T7,T5,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T7,T5	Yes	T3,T7,T5	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T6,T4	Yes	T3,T6,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T6,T4	Yes	T3,T6,T4	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT
app_o[0].digest_share1[383:0]	No	No		No		OUTPUT
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	No	No		No		OUTPUT
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	No	No		No		OUTPUT
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req	No	No		No		OUTPUT
entropy_i.edn_bus[31:0]	No	No		No		INPUT
entropy_i.edn_fips	No	No		No		INPUT
entropy_i.edn_ack	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T2,T10,T8	Yes	T2,T10,T8	OUTPUT
intr_fifo_empty_o	Yes	Yes	T2,T10,T11	Yes	T2,T10,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Module : kmac

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Not Covered
KmacIdle	785	Not Covered
KmacKeyBlock	792	Not Covered
KmacMsgFeed	782	Not Covered
KmacPrefix	779	Not Covered
KmacTerminalError	834	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Not Covered
KmacDigest->KmacTerminalError	848	Not Covered
KmacIdle->KmacMsgFeed	782	Not Covered
KmacIdle->KmacPrefix	779	Not Covered
KmacIdle->KmacTerminalError	848	Not Covered
KmacKeyBlock->KmacMsgFeed	801	Not Covered
KmacKeyBlock->KmacTerminalError	848	Not Covered
KmacMsgFeed->KmacDigest	817	Not Covered
KmacMsgFeed->KmacIdle	814	Not Covered
KmacMsgFeed->KmacTerminalError	848	Not Covered
KmacPrefix->KmacKeyBlock	792	Not Covered
KmacPrefix->KmacMsgFeed	792	Not Covered
KmacPrefix->KmacTerminalError	848	Not Covered

---

Branch Coverage for Module : kmac

	Line No.	Total	Covered	Percent
Branches		65	0	0.00
TERNARY	426	2	0	0.00
TERNARY	635	4	0	0.00
TERNARY	643	4	0	0.00
TERNARY	648	2	0	0.00
CASE	434	6	0	0.00
IF	488	3	0	0.00
IF	561	3	0	0.00
IF	651	2	0	0.00
CASE	689	6	0	0.00
IF	765	2	0	0.00
CASE	774	15	0	0.00
IF	847	2	0	0.00
TERNARY	1162	2	0	0.00
IF	1423	4	0	0.00
IF	1446	3	0	0.00
IF	1475	3	0	0.00
IF	1485	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1162	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1423	if ((!rst_ni))
-2-:	1425	if (alert_recov_operation)
-3-:	1427	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1446	if ((!rst_ni))
-2-:	1448	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))
-2-:	1477	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		161	0	0.00
ALWAYS	346	0	0
ALWAYS	346	2	0	0.00
ALWAYS	352	1	0	0.00
CONT_ASSIGN	421	1	0	0.00
CONT_ASSIGN	422	1	0	0.00
CONT_ASSIGN	426	1	0	0.00
ALWAYS	429	9	0	0.00
CONT_ASSIGN	464	1	0	0.00
CONT_ASSIGN	465	1	0	0.00
CONT_ASSIGN	466	1	0	0.00
CONT_ASSIGN	469	1	0	0.00
CONT_ASSIGN	473	1	0	0.00
CONT_ASSIGN	474	1	0	0.00
CONT_ASSIGN	478	1	0	0.00
CONT_ASSIGN	481	1	0	0.00
ALWAYS	488	6	0	0.00
CONT_ASSIGN	513	1	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	525	1	0	0.00
CONT_ASSIGN	528	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	530	1	0	0.00
CONT_ASSIGN	532	1	0	0.00
CONT_ASSIGN	533	1	0	0.00
CONT_ASSIGN	535	1	0	0.00
CONT_ASSIGN	537	0	0
CONT_ASSIGN	539	1	0	0.00
CONT_ASSIGN	543	1	0	0.00
CONT_ASSIGN	545	1	0	0.00
CONT_ASSIGN	546	1	0	0.00
CONT_ASSIGN	549	1	0	0.00
CONT_ASSIGN	550	1	0	0.00
CONT_ASSIGN	553	1	0	0.00
ALWAYS	561	5	0	0.00
CONT_ASSIGN	571	1	0	0.00
CONT_ASSIGN	577	1	0	0.00
CONT_ASSIGN	578	1	0	0.00
CONT_ASSIGN	579	1	0	0.00
CONT_ASSIGN	587	1	0	0.00
CONT_ASSIGN	629	1	0	0.00
CONT_ASSIGN	635	1	0	0.00
CONT_ASSIGN	643	1	0	0.00
CONT_ASSIGN	648	1	0	0.00
ALWAYS	651	5	0	0.00
CONT_ASSIGN	679	1	0	0.00
CONT_ASSIGN	684	1	0	0.00
ALWAYS	687	7	0	0.00
CONT_ASSIGN	723	1	0	0.00
CONT_ASSIGN	728	1	0	0.00
CONT_ASSIGN	735	1	0	0.00
CONT_ASSIGN	745	1	0	0.00
ALWAYS	765	3	0	0.00
ALWAYS	769	28	0	0.00
CONT_ASSIGN	920	1	0	0.00
CONT_ASSIGN	923	1	0	0.00
CONT_ASSIGN	992	1	0	0.00
CONT_ASSIGN	994	1	0	0.00
CONT_ASSIGN	1029	1	0	0.00
CONT_ASSIGN	1034	1	0	0.00
CONT_ASSIGN	1035	1	0	0.00
CONT_ASSIGN	1037	1	0	0.00
CONT_ASSIGN	1040	0	0
ALWAYS	1161	0	0
ALWAYS	1161	2	0	0.00
CONT_ASSIGN	1315	1	0	0.00
CONT_ASSIGN	1316	1	0	0.00
CONT_ASSIGN	1317	1	0	0.00
CONT_ASSIGN	1327	1	0	0.00
CONT_ASSIGN	1328	1	0	0.00
CONT_ASSIGN	1334	1	0	0.00
CONT_ASSIGN	1335	1	0	0.00
CONT_ASSIGN	1336	1	0	0.00
CONT_ASSIGN	1337	1	0	0.00
CONT_ASSIGN	1340	1	0	0.00
CONT_ASSIGN	1349	1	0	0.00
CONT_ASSIGN	1391	1	0	0.00
CONT_ASSIGN	1405	1	0	0.00
CONT_ASSIGN	1412	1	0	0.00
CONT_ASSIGN	1417	1	0	0.00
ALWAYS	1423	6	0	0.00
CONT_ASSIGN	1432	1	0	0.00
CONT_ASSIGN	1434	1	0	0.00
ALWAYS	1446	4	0	0.00
CONT_ASSIGN	1452	1	0	0.00
ALWAYS	1475	4	0	0.00
ALWAYS	1485	3	0	0.00
CONT_ASSIGN	1496	1	0	0.00
CONT_ASSIGN	1500	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00
CONT_ASSIGN	1502	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
346	0	1
347	0	1
352	0	1
421	0	1
422	0	1
426	0	1
429	0	1
430	0	1
431	0	1
432	0	1
434	0	1
436	0	1
440	0	1
444	0	1
448	0	1
464	0	1
465	0	1
466	0	1
469	0	1
473	0	1
474	0	1
478	0	1
481	0	1
488	0	1
489	0	1
490	0	1
491	0	1
492	0	1
493	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
513	0	1
518	0	1
525	0	1
528	0	1
529	0	1
530	0	1
532	0	1
533	0	1
535	0	1
537		unreachable
539	0	1
543	0	1
545	0	1
546	0	1
549	0	1
550	0	1
553	0	1
561	0	1
562	0	1
563	0	1
564	0	1
566	0	1
571	0	1
577	0	1
578	0	1
579	0	1
587	0	1
629	0	1
635	0	1
643	0	1
648	0	1
651	0	1
652	0	1
653	0	1
655	0	1
656	0	1
679	0	1
684	0	1
687	0	1
689	0	1
694	0	1
698	0	1
702	0	1
706	0	1
710	0	1
723	0	1
728	0	1
735	0	1
745	0	1
765	0	3
769	0	1
771	0	1
772	0	1
774	0	1
776	0	1
778	0	1
779	0	1
782	0	1
785	0	1
791	0	1
792	0	1
794	0	1
799	0	1
800	0	1
801	0	1
803	0	1
809	0	1
814	0	1
815	0	1
817	0	1
819	0	1
825	0	1
826	0	1
828	0	1
834	0	1
835	0	1
847	0	1
848	0	1
			==> MISSING_ELSE
920	0	1
923	0	1
992	0	1
994	0	1
1029	0	1
1034	0	1
1035	0	1
1037	0	1
1040		unreachable
1161	0	1
1162	0	1
1315	0	1
1316	0	1
1317	0	1
1327	0	1
1328	0	1
1334	0	1
1335	0	1
1336	0	1
1337	0	1
1340	0	1
1349	0	1
1391	0	1
1405	0	1
1412	0	1
1417	0	1
1423	0	1
1424	0	1
1425	0	1
1426	0	1
1427	0	1
1428	0	1
			==> MISSING_ELSE
1432	0	1
1434	0	1
1446	0	1
1447	0	1
1448	0	1
1449	0	1
			==> MISSING_ELSE
1452	0	1
1475	0	1
1476	0	1
1477	0	1
1479	0	1
			==> MISSING_ELSE
1485	0	1
1486	0	1
1489	0	1
1496	0	1
1500	0	1
1502	0	6

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	90	0	0.00
Logical	90	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       426
 EXPRESSION (cmd_update ? cmd_q : CmdNone)
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       464
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       465
 EXPRESSION (sha3_fsm == StAbsorb)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (sha3_fsm == StSqueeze)
            -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       478
 EXPRESSION (sha3_fsm == StIdle)
            ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       530
 EXPRESSION (reg2hw.cmd.entropy_req.q && reg2hw.cmd.entropy_req.qe)
             ------------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       539
 EXPRESSION (reg2hw.cmd.hash_cnt_clr.qe && reg2hw.cmd.hash_cnt_clr.q)
             -------------1------------    ------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       543
 EXPRESSION (reg2hw.cfg_shadowed.entropy_ready.q & reg2hw.cfg_shadowed.entropy_ready.qe)
             -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       550
 EXPRESSION (cfg_msg_mask & msg_valid & msg_ready)
             ------1-----   ----2----   ----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       563
 EXPRESSION ((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg))
             ----------1---------    ------------------2------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       563
 SUB-EXPRESSION (sha3_fsm == StIdle)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       563
 SUB-EXPRESSION (msgfifo_empty || SecIdleAcceptSwMsg)
                 ------1------    ---------2--------

-1-	-2-	Status	Tests
0	-	Not Covered
1	-	Not Covered

 LINE       571
 EXPRESSION (reg2hw.cmd.err_processed.q & reg2hw.cmd.err_processed.qe)
             -------------1------------   -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       629
 EXPRESSION (msgfifo_empty_q & ((~msgfifo_empty)))
             -------1-------   ---------2--------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       635
 EXPRESSION (msgfifo_full ? 1'b1 : (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)))
             ------1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       635
 SUB-EXPRESSION (msgfifo_empty_negedge ? 1'b0 : (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q))
                 ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       635
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b0 : msgfifo_full_seen_q)
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 EXPRESSION (app_active ? 1'b1 : ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))))
             -----1----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION ((sha3_fsm != StAbsorb) ? 1'b1 : (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q))))
                 -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION (sha3_fsm != StAbsorb)
                -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       643
 SUB-EXPRESSION (msgfifo2kmac_process ? 1'b1 : ((~msgfifo_full_seen_q)))
                 ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       648
 EXPRESSION (msgfifo_empty_gate ? 1'b0 : msgfifo_empty)
             ---------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       679
 EXPRESSION (sha3_err.valid | app_err.valid | entropy_err.valid | errchecker_err.valid)
             -------1------   ------2------   --------3--------   ----------4---------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       723
 EXPRESSION (sha3_count_error | kmac_entropy_hash_counter_error | key_index_error | msgfifo_counter_error)
             --------1-------   ---------------2---------------   -------3-------   ----------4----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Unreachable
1	0	0	0	Not Covered

 LINE       735
 EXPRESSION (sha3_state_error | kmac_errchk_state_error | kmac_core_state_error | kmac_app_state_error | kmac_entropy_state_error | kmac_state_error)
             --------1-------   -----------2-----------   ----------3----------   ----------4---------   ------------5-----------   --------6-------

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
0	0	0	0	0	0	Not Covered
0	0	0	0	0	1	Not Covered
0	0	0	0	1	0	Unreachable
0	0	0	1	0	0	Not Covered
0	0	1	0	0	0	Not Covered
0	1	0	0	0	0	Not Covered
1	0	0	0	0	0	Not Covered

 LINE       776
 EXPRESSION (kmac_cmd == CmdStart)
            -----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       778
 EXPRESSION (CShake == app_sha3_mode)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       792
 EXPRESSION (app_kmac_en ? KmacKeyBlock : KmacMsgFeed)
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1029
 EXPRESSION (tlram_req & tlram_we)
             ----1----   ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1162
 EXPRESSION (reg_state_valid ? reg_state[i] : 'b0)
             -------1-------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.fatal_fault_err.q & reg2hw.alert_test.fatal_fault_err.qe)
                 -----------------1-----------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1405
 SUB-EXPRESSION (reg2hw.alert_test.recov_operation_err.q & reg2hw.alert_test.recov_operation_err.qe)
                 -------------------1-------------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       1434
 EXPRESSION (shadowed_storage_err | alert_intg_err | sparse_fsm_error | counter_error | control_integrity_error)
             ----------1---------   -------2------   --------3-------   ------4------   -----------5-----------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Not Covered
0	0	0	0	1	Not Covered
0	0	0	1	0	Not Covered
0	0	1	0	0	Not Covered
0	1	0	0	0	Not Covered
1	0	0	0	0	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	64	38	59.38
Total Bits	4160	362	8.70
Total Bits 0->1	2080	181	8.70
Total Bits 1->0	2080	181	8.70

Ports	64	38	59.38
Port Bits	4160	362	8.70
Port Bits 0->1	2080	181	8.70
Port Bits 1->0	2080	181	8.70

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T6	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T7,T5,T8	Yes	T7,T5,T8	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T3,T7,T5	Yes	T3,T7,T5	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T6,T4	Yes	T3,T6,T4	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T6,T4	Yes	T3,T6,T4	OUTPUT
keymgr_key_i.key[1:0][255:0]	No	No		No		INPUT
keymgr_key_i.valid	No	No		No		INPUT
app_i[0].last	No	No		No		INPUT
app_i[0].strb[7:0]	No	No		No		INPUT
app_i[0].data[63:0]	No	No		No		INPUT
app_i[0].valid	No	No		No		INPUT
app_i[1].last	No	No		No		INPUT
app_i[1].strb[7:0]	No	No		No		INPUT
app_i[1].data[63:0]	No	No		No		INPUT
app_i[1].valid	No	No		No		INPUT
app_i[2].last	No	No		No		INPUT
app_i[2].strb[7:0]	No	No		No		INPUT
app_i[2].data[63:0]	No	No		No		INPUT
app_i[2].valid	No	No		No		INPUT
app_o[0].error	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT
app_o[0].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[0].digest_share0[383:0]	No	No		No		OUTPUT
app_o[0].done	No	No		No		OUTPUT
app_o[0].ready	No	No		No		OUTPUT
app_o[1].error	No	No		No		OUTPUT
app_o[1].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[1].digest_share0[383:0]	No	No		No		OUTPUT
app_o[1].done	No	No		No		OUTPUT
app_o[1].ready	No	No		No		OUTPUT
app_o[2].error	No	No		No		OUTPUT
app_o[2].digest_share1[383:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac share1 always output 0.
app_o[2].digest_share0[383:0]	No	No		No		OUTPUT
app_o[2].done	No	No		No		OUTPUT
app_o[2].ready	No	No		No		OUTPUT
entropy_o.edn_req[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_bus[31:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_fips[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
entropy_i.edn_ack[0:0]	Excluded	Excluded		Excluded		INPUT	[UNSUPPORTED]: unmasked kmac does not use entropy.
lc_escalate_en_i[3:0]	No	No		No		INPUT
intr_kmac_done_o	Yes	Yes	T2,T10,T8	Yes	T2,T10,T8	OUTPUT
intr_fifo_empty_o	Yes	Yes	T2,T10,T11	Yes	T2,T10,T11	OUTPUT
intr_kmac_err_o	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
en_masking_o	Unreachable	Unreachable		Unreachable		OUTPUT
idle_o[3:0]	Yes	Yes	T3,T4,T9	Yes	T3,T4,T9	OUTPUT

*Tests covering at least one bit in the range

---

FSM Coverage for Instance : tb.dut

Summary for FSM :: kmac_st

	Total	Covered	Percent
States	6	0	0.00	(Not included in score)
Transitions	13	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: kmac_st

---

states	Line No.	Covered	Tests
KmacDigest	817	Not Covered
KmacIdle	785	Not Covered
KmacKeyBlock	792	Not Covered
KmacMsgFeed	782	Not Covered
KmacPrefix	779	Not Covered
KmacTerminalError	834	Not Covered

transitions	Line No.	Covered	Tests
KmacDigest->KmacIdle	826	Not Covered
KmacDigest->KmacTerminalError	848	Not Covered
KmacIdle->KmacMsgFeed	782	Not Covered
KmacIdle->KmacPrefix	779	Not Covered
KmacIdle->KmacTerminalError	848	Not Covered
KmacKeyBlock->KmacMsgFeed	801	Not Covered
KmacKeyBlock->KmacTerminalError	848	Not Covered
KmacMsgFeed->KmacDigest	817	Not Covered
KmacMsgFeed->KmacIdle	814	Not Covered
KmacMsgFeed->KmacTerminalError	848	Not Covered
KmacPrefix->KmacKeyBlock	792	Not Covered
KmacPrefix->KmacMsgFeed	792	Not Covered
KmacPrefix->KmacTerminalError	848	Not Covered

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		65	0	0.00
TERNARY	426	2	0	0.00
TERNARY	635	4	0	0.00
TERNARY	643	4	0	0.00
TERNARY	648	2	0	0.00
CASE	434	6	0	0.00
IF	488	3	0	0.00
IF	561	3	0	0.00
IF	651	2	0	0.00
CASE	689	6	0	0.00
IF	765	2	0	0.00
CASE	774	15	0	0.00
IF	847	2	0	0.00
TERNARY	1162	2	0	0.00
IF	1423	4	0	0.00
IF	1446	3	0	0.00
IF	1475	3	0	0.00
IF	1485	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv' or '../src/lowrisc_ip_kmac_0.1/rtl/kmac.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	426	(cmd_update) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	635	(msgfifo_full) ? 
-2-:	635	(msgfifo_empty_negedge) ? 
-3-:	635	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	643	(app_active) ? 
-2-:	643	((sha3_fsm != StAbsorb)) ? 
-3-:	643	(msgfifo2kmac_process) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	648	(msgfifo_empty_gate) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	434	case (kmac_cmd)

Branches:

-1-	Status	Tests
CmdStart	Not Covered
CmdProcess	Not Covered
CmdManualRun	Not Covered
CmdDone	Not Covered
CmdNone	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	488	if ((!rst_ni))
-2-:	490	if (engine_stable)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	561	if ((!rst_ni))
-2-:	563	if (((sha3_fsm == StIdle) && (msgfifo_empty || SecIdleAcceptSwMsg)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	651	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	689	case (1'b1)

Branches:

-1-	Status	Tests
app_err.valid	Not Covered
errchecker_err.valid	Not Covered
sha3_err.valid	Not Covered
entropy_err.valid	Not Covered
msgfifo_err.valid	Not Covered
default	Not Covered

	LineNo.	Expression
-1-:	765	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	774	case (kmac_st)
-2-:	776	if ((kmac_cmd == CmdStart))
-3-:	778	if ((CShake == app_sha3_mode))
-4-:	791	if (sha3_block_processed)
-5-:	792	(app_kmac_en) ? 
-6-:	800	if (sha3_block_processed)
-7-:	809	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_true_strict(sha3_done)))
-8-:	815	if ((prim_mubi_pkg::mubi4_test_true_strict(sha3_absorbed) && prim_mubi_pkg::mubi4_test_false_loose(sha3_done)))
-9-:	825	if (prim_mubi_pkg::mubi4_test_true_strict(sha3_done))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	Status	Tests
KmacIdle	1	1	-	-	-	-	-	-	Not Covered
KmacIdle	1	0	-	-	-	-	-	-	Not Covered
KmacIdle	0	-	-	-	-	-	-	-	Not Covered
KmacPrefix	-	-	1	1	-	-	-	-	Not Covered
KmacPrefix	-	-	1	0	-	-	-	-	Not Covered
KmacPrefix	-	-	0	-	-	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	1	-	-	-	Not Covered
KmacKeyBlock	-	-	-	-	0	-	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	1	-	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	1	-	Not Covered
KmacMsgFeed	-	-	-	-	-	0	0	-	Not Covered
KmacDigest	-	-	-	-	-	-	-	1	Not Covered
KmacDigest	-	-	-	-	-	-	-	0	Not Covered
KmacTerminalError	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	847	if (lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1162	(reg_state_valid) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	1423	if ((!rst_ni))
-2-:	1425	if (alert_recov_operation)
-3-:	1427	if (err_processed)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

	LineNo.	Expression
-1-:	1446	if ((!rst_ni))
-2-:	1448	if (alert_fatal)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1475	if ((!rst_ni))
-2-:	1477	if (alerts[1])

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	1485	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered