Unified Coverage Report :: Module :: kmac_csr_assert_fpv

Module : kmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_kmac_csr_assert_0/kmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.kmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.kmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
1.74	0.00	0.00	8.70	0.00	0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : kmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	14	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	14	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1418747	3014	0	0
entropy_period_rd_A	1418747	1672	0	0
intr_enable_rd_A	1418747	2536	0	0
prefix_0_rd_A	1418747	1620	0	0
prefix_10_rd_A	1418747	1785	0	0
prefix_1_rd_A	1418747	1704	0	0
prefix_2_rd_A	1418747	1788	0	0
prefix_3_rd_A	1418747	1710	0	0
prefix_4_rd_A	1418747	1714	0	0
prefix_5_rd_A	1418747	1799	0	0
prefix_6_rd_A	1418747	1702	0	0
prefix_7_rd_A	1418747	1666	0	0
prefix_8_rd_A	1418747	1867	0	0
prefix_9_rd_A	1418747	1617	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	3014	0	0
T3	38480	3	0	0
T4	7073	0	0	0
T5	2886	6	0	0
T6	8864	0	0	0
T7	12894	124	0	0
T8	1455	0	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	4	0	0
T13	0	54	0	0
T14	0	58	0	0
T15	0	15	0	0
T16	0	184	0	0
T21	1327	0	0	0
T23	0	2	0	0
T24	0	2	0	0

entropy_period_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1672	0	0
T3	38480	136	0	0
T4	7073	54	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	15	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	11	0	0
T18	0	10	0	0
T21	1327	0	0	0
T23	0	103	0	0
T26	0	70	0	0
T27	0	20	0	0
T57	0	78	0	0
T77	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	2536	0	0
T3	38480	118	0	0
T4	7073	35	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	9	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	3	0	0
T18	0	14	0	0
T21	1327	0	0	0
T23	0	155	0	0
T26	0	90	0	0
T27	0	19	0	0
T57	0	95	0	0
T78	0	22	0	0

prefix_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1620	0	0
T3	38480	104	0	0
T4	7073	14	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	13	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	10	0	0
T18	0	3	0	0
T21	1327	0	0	0
T23	0	92	0	0
T26	0	56	0	0
T27	0	34	0	0
T57	0	28	0	0
T77	0	3	0	0

prefix_10_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1785	0	0
T3	38480	93	0	0
T4	7073	20	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	13	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	9	0	0
T18	0	3	0	0
T21	1327	0	0	0
T23	0	65	0	0
T26	0	42	0	0
T27	0	21	0	0
T57	0	64	0	0
T77	0	7	0	0

prefix_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1704	0	0
T3	38480	102	0	0
T4	7073	13	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	8	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	3	0	0
T18	0	11	0	0
T21	1327	0	0	0
T23	0	79	0	0
T26	0	43	0	0
T27	0	17	0	0
T57	0	38	0	0
T79	0	28	0	0

prefix_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1788	0	0
T3	38480	89	0	0
T4	7073	24	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	5	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	3	0	0
T18	0	6	0	0
T21	1327	0	0	0
T23	0	77	0	0
T26	0	43	0	0
T27	0	17	0	0
T57	0	61	0	0
T77	0	14	0	0

prefix_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1710	0	0
T3	38480	90	0	0
T4	7073	28	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	8	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	9	0	0
T18	0	12	0	0
T21	1327	0	0	0
T23	0	108	0	0
T26	0	44	0	0
T27	0	21	0	0
T57	0	53	0	0
T77	0	4	0	0

prefix_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1714	0	0
T3	38480	59	0	0
T4	7073	34	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	7	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	6	0	0
T18	0	10	0	0
T21	1327	0	0	0
T23	0	92	0	0
T26	0	64	0	0
T27	0	19	0	0
T57	0	48	0	0
T77	0	13	0	0

prefix_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1799	0	0
T3	38480	92	0	0
T4	7073	33	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	6	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	4	0	0
T18	0	12	0	0
T21	1327	0	0	0
T23	0	99	0	0
T26	0	47	0	0
T27	0	11	0	0
T57	0	66	0	0
T77	0	7	0	0

prefix_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1702	0	0
T3	38480	70	0	0
T4	7073	33	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	4	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	5	0	0
T18	0	2	0	0
T21	1327	0	0	0
T23	0	67	0	0
T26	0	50	0	0
T27	0	19	0	0
T57	0	38	0	0
T77	0	16	0	0

prefix_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1666	0	0
T3	38480	84	0	0
T4	7073	23	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	9	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	9	0	0
T18	0	7	0	0
T21	1327	0	0	0
T23	0	82	0	0
T26	0	55	0	0
T27	0	16	0	0
T57	0	59	0	0
T80	0	1	0	0

prefix_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1867	0	0
T3	38480	69	0	0
T4	7073	31	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	12	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	5	0	0
T18	0	6	0	0
T21	1327	0	0	0
T23	0	89	0	0
T26	0	33	0	0
T27	0	17	0	0
T57	0	65	0	0
T77	0	8	0	0

prefix_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1418747	1617	0	0
T3	38480	78	0	0
T4	7073	36	0	0
T5	2886	0	0	0
T6	8864	0	0	0
T7	12894	0	0	0
T8	1455	0	0	0
T9	0	5	0	0
T10	1361	0	0	0
T11	1384	0	0	0
T12	5217	9	0	0
T18	0	6	0	0
T21	1327	0	0	0
T23	0	71	0	0
T26	0	47	0	0
T27	0	23	0	0
T57	0	42	0	0
T79	0	10	0	0