LC_CTRL Simulation Results

Friday May 19 2023 07:05:15 UTC

GitHub Revision: `30db5a999`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2235272161

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	5.810s	979.298us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.040s	21.272us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.120s	18.692us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.560s	64.118us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.540s	166.506us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	39.852us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.120s	18.692us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	166.506us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	16.420s	148.129us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.000s	400.433us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.950s	31.002us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.160s	86.178us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.640s	1.256ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_prog_failure	4.160s	86.178us	50	50	100.00
		lc_ctrl_errors	18.640s	1.256ms	50	50	100.00
		lc_ctrl_security_escalation	16.440s	1.833ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.636m	5.020ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.450s	847.842us	20	20	100.00
		lc_ctrl_jtag_errors	2.255m	5.454ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	17.240s	749.288us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	34.430s	1.132ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	20.450s	847.842us	20	20	100.00
		lc_ctrl_jtag_errors	2.255m	5.454ms	20	20	100.00
		lc_ctrl_jtag_access	32.010s	1.438ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	40.620s	1.640ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	6.580s	273.170us	10	10	100.00
		lc_ctrl_jtag_csr_rw	4.500s	187.723us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	22.080s	2.667ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	28.420s	1.404ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.790s	39.068us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.960s	126.883us	9	10	90.00
		lc_ctrl_jtag_alert_test	2.200s	72.577us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	29.570s	1.676ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.430s	25.332us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.473m	19.566ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.350s	149.246us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.910s	138.517us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.910s	138.517us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.040s	21.272us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	18.692us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	166.506us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	99.284us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.040s	21.272us	5	5	100.00
		lc_ctrl_csr_rw	1.120s	18.692us	20	20	100.00
		lc_ctrl_csr_aliasing	1.540s	166.506us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	99.284us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
		lc_ctrl_tl_intg_err	4.680s	580.431us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.680s	580.431us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.000s	400.433us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	1.007m	357.837us	50	50	100.00
		lc_ctrl_sec_cm	1.110m	241.975us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.440s	1.833ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	16.420s	148.129us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	34.430s	1.132ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	25.940s	2.593ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	25.940s	2.593ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.730s	11.394ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.630s	3.551ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.630s	3.551ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	18.492m	125.686ms	9	50	18.00
V3		TOTAL			9	50	18.00
		TOTAL			988	1030	95.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	97.18	94.99	91.98	100.00	95.88	98.73	94.82

Failure Buckets

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: Job failed: the job consumes more ram than allocated, try to request more ram for the job. has 30 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 30 failures.
  - 0.lc_ctrl_stress_all_with_rand_reset.2954085862
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fbd21aa1-61c9-44c1-a045-44beec380b6a
```
  - 2.lc_ctrl_stress_all_with_rand_reset.504132026
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:fe4b6cd2-1c6a-4c79-9b5f-0ae222cc1bf3
```
  - ... and 28 more failures.

UVM_FATAL (lc_ctrl_scoreboard.sv:265) scoreboard [scoreboard] Access unexpected addr * has 6 failures:

Test lc_ctrl_stress_all_with_rand_reset has 6 failures.

7.lc_ctrl_stress_all_with_rand_reset.1567388360
Line 14178, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 21441213988 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xd82cc800
  UVM_INFO @ 21441213988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.lc_ctrl_stress_all_with_rand_reset.2654483716
Line 25887, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 16825516893 ps: (lc_ctrl_scoreboard.sv:265) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Access unexpected addr 0xa8b2d404
  UVM_INFO @ 16825516893 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 4 failures.
  - 8.lc_ctrl_stress_all_with_rand_reset.795122909
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/8.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:bdc4830a-b6bc-426c-bb79-edf4d0540446
```
  - 9.lc_ctrl_stress_all_with_rand_reset.3672595930
    Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:51f72be2-a946-44de-94ca-3c6f72f16ffa
```
  - ... and 2 more failures.
UVM_ERROR (jtag_riscv_monitor.sv:80) monitor [monitor] Bad status - DmiReserved(*) has 1 failures:
- Test lc_ctrl_jtag_csr_mem_rw_with_rand_reset has 1 failures.
  - 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1188756860
    Line 312, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @  62200705 ps: (jtag_riscv_monitor.sv:80) uvm_test_top.env.m_jtag_riscv_agent.monitor [uvm_test_top.env.m_jtag_riscv_agent.monitor] Bad status - DmiReserved(0x1)
  UVM_INFO @  62200705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: lc_ctrl_reg_block.status.ready reset value: * called from ../src/lowrisc_dv_lc_ctrl_env_*/seq_lib/lc_ctrl_errors_vseq.sv: * has 1 failures:
- Test lc_ctrl_stress_all_with_rand_reset has 1 failures.
  - 39.lc_ctrl_stress_all_with_rand_reset.889095842
    Line 37541, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 118295778872 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: lc_ctrl_reg_block.status.ready reset value: 0x0 called from ../src/lowrisc_dv_lc_ctrl_env_0.1/seq_lib/lc_ctrl_errors_vseq.sv: 290
  UVM_INFO @ 118295778872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```