LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.170s	122.513us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.260s	72.300us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.050s	108.578us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.210s	1.416ms	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.390s	84.944us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.720s	82.403us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.050s	108.578us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	84.944us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.410s	110.172us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.360s	607.867us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	22.501us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.560s	668.759us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	20.300s	1.602ms	49	50	98.00
V2	security_escalation	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_prog_failure	5.560s	668.759us	50	50	100.00
		lc_ctrl_errors	20.300s	1.602ms	49	50	98.00
		lc_ctrl_security_escalation	15.750s	931.262us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.437m	4.698ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.180s	4.189ms	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	46.928ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	19.300s	10.623ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	28.360s	3.331ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	27.180s	4.189ms	20	20	100.00
		lc_ctrl_jtag_errors	1.923m	46.928ms	20	20	100.00
		lc_ctrl_jtag_access	19.460s	5.775ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	38.710s	2.808ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.540s	502.849us	10	10	100.00
		lc_ctrl_jtag_csr_rw	1.850s	215.676us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	38.790s	7.219ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.280s	5.107ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.000s	96.088us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.360s	655.154us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.010s	62.362us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	10.580s	4.250ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.600s	42.761us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	9.133m	67.416ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.280s	43.175us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.570s	114.116us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.570s	114.116us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.260s	72.300us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	108.578us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	84.944us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	142.382us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.260s	72.300us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	108.578us	20	20	100.00
		lc_ctrl_csr_aliasing	1.390s	84.944us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.800s	142.382us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
		lc_ctrl_tl_intg_err	5.130s	698.419us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.130s	698.419us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.360s	607.867us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.480s	2.380ms	50	50	100.00
		lc_ctrl_sec_cm	36.280s	1.920ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.750s	931.262us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.410s	110.172us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	28.360s	3.331ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.400s	873.860us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.400s	873.860us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	25.020s	3.030ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	23.550s	750.479us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	23.550s	750.479us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	57.154m	75.159ms	16	50	32.00
V3		TOTAL			16	50	32.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.92	97.79	95.89	93.30	97.62	98.34	99.00	96.47

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 30 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.36669793156204332597401031069615198898588235995999164639056542576598130877450
      Line 7957, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4059443753 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4059443753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.57109150410353843310304807553060728776259571945519665605094066134884216251603
      Line 27045, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19253978138 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 19253978138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 13.lc_ctrl_stress_all_with_rand_reset.66984982013934005496554822221555515563402455555949184019571273477081167095929
      Line 11565, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 31884524469 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 31884524469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 23.lc_ctrl_stress_all_with_rand_reset.110155654853363105516763215787580241816759039699016318703432208501323417821514
      Line 45082, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 105128286866 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 105128286866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 22.lc_ctrl_errors.101197971777649758444486630160525174759818031027358462592795625054152492386708
      Line 1167, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/22.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 369556474 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 369556474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 49.lc_ctrl_stress_all_with_rand_reset.89196348076805051695548567554096007817682028442020719082909065963142036909588
      Line 30688, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

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