LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.330s	152.549us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.080s	71.049us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.160s	18.077us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.210s	91.065us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	39.510us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	195.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.160s	18.077us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	39.510us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	9.980s	248.052us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.060s	380.173us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.000s	11.960us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.700s	653.694us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	27.580s	2.761ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_prog_failure	4.700s	653.694us	50	50	100.00
		lc_ctrl_errors	27.580s	2.761ms	50	50	100.00
		lc_ctrl_security_escalation	19.370s	1.716ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.518m	2.889ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.490s	3.949ms	20	20	100.00
		lc_ctrl_jtag_errors	1.429m	14.385ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	12.280s	457.106us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	22.550s	4.639ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.490s	3.949ms	20	20	100.00
		lc_ctrl_jtag_errors	1.429m	14.385ms	20	20	100.00
		lc_ctrl_jtag_access	20.000s	1.665ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.200s	7.736ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.210s	2.160ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.720s	89.891us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.050s	3.475ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.470s	3.944ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.560s	180.406us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	3.840s	116.462us	10	10	100.00
		lc_ctrl_jtag_alert_test	1.980s	235.463us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	18.070s	737.896us	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.490s	18.978us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	7.757m	226.464ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.570s	37.682us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	3.690s	103.135us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	3.690s	103.135us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.080s	71.049us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.077us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	39.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	154.625us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.080s	71.049us	5	5	100.00
		lc_ctrl_csr_rw	1.160s	18.077us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	39.510us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.810s	154.625us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
		lc_ctrl_tl_intg_err	4.440s	163.644us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.440s	163.644us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.060s	380.173us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.340s	1.213ms	50	50	100.00
		lc_ctrl_sec_cm	34.500s	817.376us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	19.370s	1.716ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	9.980s	248.052us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	22.550s	4.639ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.240s	1.006ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.240s	1.006ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	28.180s	860.922us	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	16.480s	1.890ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	16.480s	1.890ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.806h	28.779ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.20	97.79	95.53	93.30	100.00	98.34	99.00	96.43

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.95840365009000418466936125733901870850802673487903546928194948173567067461856
      Line 3940, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 24698456357 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 24698456357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.63912476097542197621134491028677436330826654599244781802362916009676536519898
      Line 72277, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 101014634850 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 101014634850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.114826861921024005847955792933733960873181617877727287191283538873280530329872
      Line 19682, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 104243434908 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 104243434908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 46.lc_ctrl_stress_all_with_rand_reset.98300834576654036861310530613690723809338674796433206562829391944979302745634
      Line 15316, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8773814249 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8773814249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.73753617092275417653043719647837555294022223468485724819214423710588834955694
      Line 34574, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

    • 38.lc_ctrl_stress_all_with_rand_reset.50047725637829835437408815729384730900769523121567344157349126422973831204175
      Line 38432, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 5.lc_ctrl_jtag_priority.47685905991810713191815689639524047989947395436986125848298234995083511470487
      Line 537, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10008015516 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10008015516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 5.lc_ctrl_stress_all_with_rand_reset.5821457327643957612140520205190234115155138657450961196816418902206017240538
      Line 12478, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14181875100 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 14181875100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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