7773b039d0
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | lc_ctrl_smoke | 0 | 50 | 0.00 | ||
V1 | csr_hw_reset | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
V1 | csr_rw | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
V1 | csr_bit_bash | lc_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
V1 | csr_aliasing | lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
V1 | csr_mem_rw_with_rand_reset | lc_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
V1 | regwen_csr_and_corresponding_lockable_csr | lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
V1 | TOTAL | 0 | 105 | 0.00 | |||
V2 | state_post_trans | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
V2 | regwen_during_op | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
V2 | rand_wr_claim_transition_if | lc_ctrl_claim_transition_if | 0 | 10 | 0.00 | ||
V2 | lc_prog_failure | lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||
V2 | lc_state_failure | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
V2 | lc_errors | lc_ctrl_errors | 0 | 50 | 0.00 | ||
V2 | security_escalation | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_prog_failure | 0 | 50 | 0.00 | ||||
lc_ctrl_errors | 0 | 50 | 0.00 | ||||
lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||||
lc_ctrl_jtag_state_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
V2 | jtag_access | lc_ctrl_jtag_smoke | 0 | 20 | 0.00 | ||
lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_prog_failure | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_errors | 0 | 20 | 0.00 | ||||
lc_ctrl_jtag_access | 0 | 50 | 0.00 | ||||
lc_ctrl_jtag_regwen_during_op | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_hw_reset | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_rw | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_bit_bash | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_aliasing | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_same_csr_outstanding | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_csr_mem_rw_with_rand_reset | 0 | 10 | 0.00 | ||||
lc_ctrl_jtag_alert_test | 0 | 10 | 0.00 | ||||
V2 | jtag_priority | lc_ctrl_jtag_priority | 0 | 10 | 0.00 | ||
V2 | lc_ctrl_volatile_unlock | lc_ctrl_volatile_unlock_smoke | 0 | 50 | 0.00 | ||
V2 | stress_all | lc_ctrl_stress_all | 0 | 50 | 0.00 | ||
V2 | alert_test | lc_ctrl_alert_test | 0 | 50 | 0.00 | ||
V2 | tl_d_oob_addr_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_illegal_access | lc_ctrl_tl_errors | 0 | 20 | 0.00 | ||
V2 | tl_d_outstanding_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | tl_d_partial_access | lc_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
lc_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
lc_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
lc_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
V2 | TOTAL | 0 | 700 | 0.00 | |||
V2S | tl_intg_err | lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||
lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
V2S | sec_cm_bus_integrity | lc_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
V2S | sec_cm_transition_config_regwen | lc_ctrl_regwen_during_op | 0 | 10 | 0.00 | ||
V2S | sec_cm_manuf_state_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_transition_ctr_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_manuf_state_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_transition_ctr_bkgn_chk | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_state_config_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_kmac_fsm_sparse | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_local_esc | lc_ctrl_state_failure | 0 | 50 | 0.00 | ||
lc_ctrl_sec_cm | 0 | 5 | 0.00 | ||||
V2S | sec_cm_main_fsm_global_esc | lc_ctrl_security_escalation | 0 | 50 | 0.00 | ||
V2S | sec_cm_main_ctrl_flow_consistency | lc_ctrl_state_post_trans | 0 | 50 | 0.00 | ||
lc_ctrl_jtag_state_post_trans | 0 | 20 | 0.00 | ||||
V2S | sec_cm_intersig_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_valid_ctrl_mubi | lc_ctrl_sec_mubi | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_digest | lc_ctrl_sec_token_digest | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_mux_ctrl_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
V2S | sec_cm_token_valid_mux_redun | lc_ctrl_sec_token_mux | 0 | 50 | 0.00 | ||
V2S | TOTAL | 0 | 175 | 0.00 | |||
V3 | stress_all_with_rand_reset | lc_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 0 | 1030 | 0.00 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 0 | 0.00 |
V2 | 27 | 27 | 0 | 0.00 |
V2S | 5 | 5 | 0 | 0.00 |
V3 | 1 | 1 | 0 | 0.00 |
User terminated with CTRL-C
has 1030 failures:
0.lc_ctrl_smoke.12819724784714591115892810126973762736975356733764477804921254092493228281795
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_smoke/latest/run.log
1.lc_ctrl_smoke.15712473215362775877387510398994248427938714019910880656193547537931903940826
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_volatile_unlock_smoke.33588009773680502969584297498469451203168421199550023882870163631078761559948
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest/run.log
1.lc_ctrl_volatile_unlock_smoke.1350999769098862416534809148717606510345059227195704575734777092963921708566
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_failure.40600839177311000906778653431457052187928359940630717874500740042789845207811
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_failure/latest/run.log
1.lc_ctrl_state_failure.79437088513858163099771245128937464582484080673989488637133483185260667143029
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_failure/latest/run.log
... and 48 more failures.
0.lc_ctrl_state_post_trans.110632223462314344550621905768966583373778273320571279971397025513886302798696
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_state_post_trans/latest/run.log
1.lc_ctrl_state_post_trans.8771902492341668704950685928345931163078299572223656117157157764269517118254
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_state_post_trans/latest/run.log
... and 48 more failures.
0.lc_ctrl_prog_failure.20024224456747457124564176819251580039656974071484369989114047293088844881839
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_prog_failure/latest/run.log
1.lc_ctrl_prog_failure.71404477630061443083894490007453202475100958721108536450423209273774671586271
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_prog_failure/latest/run.log
... and 48 more failures.
Job killed most likely because its dependent job failed.
has 2 failures:
cov_merge
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_merge/merged.vdb/cov_merge.log
cov_report
Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log