LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: 2723ca659d

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.500s	131.428us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	21.081us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.070s	16.484us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.990s	94.092us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.410s	34.389us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.100s	105.256us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.070s	16.484us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	34.389us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	13.380s	94.309us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	21.890s	688.260us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.960s	12.372us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.690s	124.057us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.010s	1.191ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_prog_failure	4.690s	124.057us	50	50	100.00
		lc_ctrl_errors	24.010s	1.191ms	50	50	100.00
		lc_ctrl_security_escalation	15.620s	1.889ms	50	50	100.00
		lc_ctrl_jtag_state_failure	1.586m	11.468ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.180s	799.882us	20	20	100.00
		lc_ctrl_jtag_errors	1.160m	2.556ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	13.020s	539.624us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	25.150s	2.088ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	22.180s	799.882us	20	20	100.00
		lc_ctrl_jtag_errors	1.160m	2.556ms	20	20	100.00
		lc_ctrl_jtag_access	23.700s	1.029ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	33.960s	12.734ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.200s	237.604us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.050s	107.199us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	52.790s	2.547ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	14.570s	5.485ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.930s	161.620us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.910s	301.274us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.180s	117.845us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.430s	3.225ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.660s	55.763us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	14.412m	26.403ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.610s	485.410us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.360s	117.849us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.360s	117.849us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	21.081us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	16.484us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	34.389us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	88.336us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	21.081us	5	5	100.00
		lc_ctrl_csr_rw	1.070s	16.484us	20	20	100.00
		lc_ctrl_csr_aliasing	1.410s	34.389us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.930s	88.336us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
		lc_ctrl_tl_intg_err	4.240s	749.763us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.240s	749.763us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	21.890s	688.260us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	35.260s	513.645us	50	50	100.00
		lc_ctrl_sec_cm	36.500s	416.062us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.620s	1.889ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	13.380s	94.309us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	25.150s	2.088ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	28.910s	802.159us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	28.910s	802.159us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	19.620s	2.322ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.480s	807.528us	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.480s	807.528us	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	2.711h	50.127ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.54067274068221817069515533057511385299953739047372551840497683793940549654167
      Line 4408, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5078513061 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5078513061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.49305679238423616988580061156208886966312926335485908295822683233306924060447
      Line 31915, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 169033934249 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 169033934249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.37250786712057254501786351604439905367170004660665874813232869325278668023313
      Line 16442, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 25065810182 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 25065810182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.70814866069977278111537094064282717554560654399575693505186426910158809214267
      Line 19158, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 39278592915 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 39278592915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 14.lc_ctrl_stress_all_with_rand_reset.99369829297149149416639448293522468850286854742700838543084871883824794407085
      Line 8502, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 26658174970 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 26658174970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 33.lc_ctrl_stress_all_with_rand_reset.23244848091281218149207378950171245470968131043243196109480909810507468311817
      Line 39550, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 35778616664 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 35778616664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 2.lc_ctrl_stress_all_with_rand_reset.93237446237888923954045431236542394862115321503209766016105524726150983101283
      Line 60413, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 5.lc_ctrl_jtag_priority.75902205331900976630034758159258677810383018016129452270825018418646822277896
      Line 449, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10014254602 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10014254602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": symlink /workspace/mnt/input/cov_merge /workspace/mnt/input/cov_merge: file exists has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:18492d86-a1cc-4aeb-a259-51322593e62f
      

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