LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	8.350s	916.930us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.240s	18.291us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.250s	18.935us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.060s	132.318us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.460s	261.089us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.130s	26.812us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.250s	18.935us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	261.089us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.210s	122.272us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	18.100s	299.122us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.090s	13.890us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.110s	585.543us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	24.770s	566.979us	48	50	96.00
V2	security_escalation	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_prog_failure	5.110s	585.543us	50	50	100.00
		lc_ctrl_errors	24.770s	566.979us	48	50	96.00
		lc_ctrl_security_escalation	16.720s	500.658us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.902m	3.402ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.760s	582.241us	20	20	100.00
		lc_ctrl_jtag_errors	1.981m	4.548ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	18.390s	14.558ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	24.310s	3.460ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	15.760s	582.241us	20	20	100.00
		lc_ctrl_jtag_errors	1.981m	4.548ms	20	20	100.00
		lc_ctrl_jtag_access	19.660s	852.731us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	34.810s	5.021ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.250s	454.490us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.300s	103.342us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	46.470s	4.271ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	27.850s	1.262ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.470s	75.658us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.710s	301.913us	10	10	100.00
		lc_ctrl_jtag_alert_test	3.450s	551.468us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	28.230s	2.588ms	9	10	90.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.610s	23.401us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.942m	14.814ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.590s	182.372us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.500s	1.858ms	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.500s	1.858ms	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.240s	18.291us	5	5	100.00
		lc_ctrl_csr_rw	1.250s	18.935us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	261.089us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	101.333us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.240s	18.291us	5	5	100.00
		lc_ctrl_csr_rw	1.250s	18.935us	20	20	100.00
		lc_ctrl_csr_aliasing	1.460s	261.089us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.980s	101.333us	20	20	100.00
V2		TOTAL			696	700	99.43
V2S	tl_intg_err	lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
		lc_ctrl_tl_intg_err	4.210s	106.978us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	4.210s	106.978us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	18.100s	299.122us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.790s	408.173us	50	50	100.00
		lc_ctrl_sec_cm	37.280s	1.886ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.720s	500.658us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.210s	122.272us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	24.310s	3.460ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	22.800s	511.120us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	22.800s	511.120us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.630s	3.418ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.000s	2.704ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.000s	2.704ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	32.586m	100.008ms	19	50	38.00
V3		TOTAL			19	50	38.00
		TOTAL			995	1030	96.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	24	88.89
V2S	5	5	5	100.00
V3	1	1	0	0.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 29 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.43870652387673291049611973172631437797458315403039610264041563576682092680019
      Line 3591, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 10129457532 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 10129457532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.43621189583507511887646944882832807756698140910100892962799769278369504854404
      Line 16720, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22681872983 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22681872983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 9.lc_ctrl_stress_all_with_rand_reset.8304655077497117841857267383893367972614548707870530297605773367011630470906
      Line 29984, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28655441528 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 28655441528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 40.lc_ctrl_stress_all_with_rand_reset.95798051766140377185661155314318873035521718783568974724026136039357092283392
      Line 20122, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/40.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18573619757 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 18573619757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! has 1 failures:

  • Test lc_ctrl_jtag_priority has 1 failures.

    • 6.lc_ctrl_jtag_priority.28965853966018101298814009940573625377719512396315404368177561578161524663488
      Line 571, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_jtag_priority/latest/run.log

        UVM_FATAL @ 10007890820 ps: (lc_ctrl_jtag_priority_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.lc_ctrl_jtag_priority_vseq] timeout occurred!
        UVM_INFO @ 10007890820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 1 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 6.lc_ctrl_stress_all.48690043222630879446859952702541754755712899028926585968553537543625310987758
      Line 3451, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/6.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 6334277213 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 6334277213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:769) [lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 15.lc_ctrl_errors.63338265240474699041143004369819546401023547722282562250745800598226464801633
      Line 1225, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/15.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 892239416 ps: (lc_ctrl_errors_vseq.sv:769) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed otp_error_act == otp_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 892239416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_errors has 1 failures.

    • 37.lc_ctrl_errors.50341606937336195204912285985904648424413368097785506629211639845333061112284
      Line 1855, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_errors/latest/run.log

        UVM_ERROR @ 588284141 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 588284141 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_cov_report killed due to: Exit reason: Error: failed to prepare tarball mounts: error in prepare GCS mounts: failed to untar/move file from "/workspace/.downloads/*/output.tar.gz" to "/workspace/mnt/input": stat /workspace/mnt/input/cov_merge: too many levels of symbolic links has 1 failures:

  • Test lc_ctrl has 1 failures.

    • cov_report
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/cov_report/cov_report.log

        Job ID: smart:4665ed75-e4ff-4825-b8b1-232ce03fe758
      

Past Results

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• 2024.04.16_04.11.56
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• 2024.04.08_19.17.42
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