LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.050s	101.812us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	14.468us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	14.752us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	1.890s	51.547us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.270s	17.272us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	2.050s	492.394us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	14.752us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	17.272us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	11.490s	107.464us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	25.810s	386.163us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	12.829us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.480s	529.507us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.460s	1.391ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_prog_failure	5.480s	529.507us	50	50	100.00
		lc_ctrl_errors	22.460s	1.391ms	50	50	100.00
		lc_ctrl_security_escalation	18.390s	975.326us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.804m	16.943ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.030s	751.816us	20	20	100.00
		lc_ctrl_jtag_errors	1.607m	12.743ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	14.460s	600.379us	20	20	100.00
		lc_ctrl_jtag_state_post_trans	32.700s	3.962ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.030s	751.816us	20	20	100.00
		lc_ctrl_jtag_errors	1.607m	12.743ms	20	20	100.00
		lc_ctrl_jtag_access	17.460s	8.104ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	41.650s	11.284ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.500s	1.404ms	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.520s	605.899us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.730s	1.751ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	10.430s	788.229us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.970s	46.916us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.740s	651.989us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.520s	85.978us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	20.450s	2.713ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.370s	66.984us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	8.963m	15.273ms	49	50	98.00
V2	alert_test	lc_ctrl_alert_test	1.380s	28.755us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	5.410s	150.562us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	5.410s	150.562us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	14.468us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	14.752us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	17.272us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.780s	76.767us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	14.468us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	14.752us	20	20	100.00
		lc_ctrl_csr_aliasing	1.270s	17.272us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.780s	76.767us	20	20	100.00
V2		TOTAL			699	700	99.86
V2S	tl_intg_err	lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
		lc_ctrl_tl_intg_err	5.220s	331.606us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.220s	331.606us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	25.810s	386.163us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	37.560s	1.057ms	50	50	100.00
		lc_ctrl_sec_cm	40.770s	809.482us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	18.390s	975.326us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	11.490s	107.464us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	32.700s	3.962ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.260s	566.967us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.260s	566.967us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	26.850s	4.844ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	17.210s	3.446ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	17.210s	3.446ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	42.387m	22.727ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	26	96.30
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.21	97.79	95.89	93.30	100.00	98.34	98.51	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 21 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.35426895551055773847992145244677897210061420278091795821272309693781470437529
      Line 325, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 453404355 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 453404355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.lc_ctrl_stress_all_with_rand_reset.85943292098070556184781929923381730138253689996659516029971458197570242314289
      Line 13404, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20952624992 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 20952624992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.77656915800103825879037958954688298123752936014026294177883289134390150619050
      Line 35663, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 92604924877 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 92604924877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 29.lc_ctrl_stress_all_with_rand_reset.99589587744930519958472586607699729592814585407010015587543904497972275552524
      Line 41845, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 71403175227 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 71403175227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all has 1 failures.

    • 26.lc_ctrl_stress_all.38570838149275749970688654615249026429305063815568358715266081192317390869716
      Line 14337, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/26.lc_ctrl_stress_all/latest/run.log

        UVM_ERROR @ 21833102663 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 21833102663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.39636729456571717866821614334614019981661143104194464464756509668280959462901
      Line 22397, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 19623732296 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 19623732296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 33.lc_ctrl_stress_all_with_rand_reset.79529574629497412832815523173875199902036198363106897679473698592545831563224
      Line 12911, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6475777176 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 6475777176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• 2024.04.16_04.13.10
• 2024.04.16_04.11.56
• 2024.04.12_19.14.24
• 2024.04.12_19.14.16
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