LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: 1c75f24e99

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	7.740s	190.237us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	0.990s	62.223us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.100s	17.187us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.580s	260.349us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.280s	135.335us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.910s	34.823us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.100s	17.187us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	135.335us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.020s	172.532us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	20.760s	1.284ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.970s	11.524us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.350s	475.558us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	22.270s	2.688ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_prog_failure	5.350s	475.558us	50	50	100.00
		lc_ctrl_errors	22.270s	2.688ms	50	50	100.00
		lc_ctrl_security_escalation	15.600s	1.120ms	50	50	100.00
		lc_ctrl_jtag_state_failure	2.122m	3.765ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.680s	4.797ms	20	20	100.00
		lc_ctrl_jtag_errors	1.121m	2.205ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.660s	3.463ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	37.710s	4.968ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	29.680s	4.797ms	20	20	100.00
		lc_ctrl_jtag_errors	1.121m	2.205ms	20	20	100.00
		lc_ctrl_jtag_access	30.070s	3.007ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	32.020s	4.810ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.060s	345.500us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.870s	365.665us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	21.040s	6.461ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	21.330s	984.584us	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	2.000s	103.973us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	6.380s	253.931us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.620s	94.504us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	14.050s	6.585ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.220s	16.390us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	19.286m	40.585ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.370s	29.590us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.540s	639.069us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.540s	639.069us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	0.990s	62.223us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	17.187us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	135.335us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	197.554us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	0.990s	62.223us	5	5	100.00
		lc_ctrl_csr_rw	1.100s	17.187us	20	20	100.00
		lc_ctrl_csr_aliasing	1.280s	135.335us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.060s	197.554us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
		lc_ctrl_tl_intg_err	3.920s	230.520us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	3.920s	230.520us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	20.760s	1.284ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	36.320s	1.332ms	50	50	100.00
		lc_ctrl_sec_cm	42.190s	4.499ms	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.600s	1.120ms	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.020s	172.532us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	37.710s	4.968ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	24.030s	2.393ms	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	24.030s	2.393ms	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	24.050s	2.603ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	19.490s	3.095ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	19.490s	3.095ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.970h	146.083ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			1003	1030	97.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.32	97.89	96.31	93.31	100.00	98.55	98.51	96.64

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 20 failures.

    • 3.lc_ctrl_stress_all_with_rand_reset.110938520371050846487441476006311486729357495206510407448799991372762526381973
      Line 12269, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 12890209899 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 12890209899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.78875358045756025245681306248686890083473253134154972850459053236898415158999
      Line 21369, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 47797771132 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 47797771132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 7.lc_ctrl_stress_all_with_rand_reset.18894444019581618991078895457525893962214226128211628685371349056710042916486
      Line 11887, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/7.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20197450209 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20197450209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 16.lc_ctrl_stress_all_with_rand_reset.83622909655893141511511307538979880419281302861751274018006936963966868576418
      Line 39462, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 34806932935 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 34806932935 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 4.lc_ctrl_stress_all_with_rand_reset.95163780997517442384458981003150849658916779706317608269985011783193491261427
      Line 31714, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20948089434 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 20948089434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (* [*] vs * [*]) has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 24.lc_ctrl_stress_all_with_rand_reset.36989473934348298717834734940952597172649766361028654022780585178729190733504
      Line 26676, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 43540840394 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed flash_rma_error_act == flash_rma_error_exp (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 43540840394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job lc_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 35.lc_ctrl_stress_all_with_rand_reset.115170965139831145782043738703533070543094757807708682473809280091603192918117
      Log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Job ID: smart:9d713d90-7fb9-4405-ab60-8382855e790d
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_regwen_during_op_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_prog_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 37.lc_ctrl_stress_all_with_rand_reset.86343072657941141170191700415261729307598841338660387684943345254796282695160
      Line 397, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 883004410 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_regwen_during_op_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_prog_error fired unexpectedly!
        UVM_INFO @ 883004410 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 39.lc_ctrl_stress_all_with_rand_reset.35811702159982968042145289444400772738159000276714616150375676245455028032845
      Line 53376, in log /container/opentitan-public/scratch/os_regression/lc_ctrl-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

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• 2024.04.17_05.12.38
• 2024.04.16_04.13.10
• 2024.04.16_04.11.56
• 2024.04.12_19.14.24
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