LC_CTRL/VOLATILE_UNLOCK_DISABLED Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.560s	176.648us	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.200s	15.832us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.050s	16.693us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	2.600s	131.287us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.330s	24.156us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	44.789us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.050s	16.693us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	24.156us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.680s	85.431us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	23.480s	349.476us	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	1.010s	26.583us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	5.440s	113.047us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
V2	lc_errors	lc_ctrl_errors	18.120s	1.781ms	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_prog_failure	5.440s	113.047us	50	50	100.00
		lc_ctrl_errors	18.120s	1.781ms	50	50	100.00
		lc_ctrl_security_escalation	16.180s	763.438us	50	50	100.00
		lc_ctrl_jtag_state_failure	1.687m	10.258ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.660s	2.198ms	20	20	100.00
		lc_ctrl_jtag_errors	1.752m	7.995ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	9.980s	1.682ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	36.250s	4.606ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	17.660s	2.198ms	20	20	100.00
		lc_ctrl_jtag_errors	1.752m	7.995ms	20	20	100.00
		lc_ctrl_jtag_access	22.150s	3.875ms	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	35.580s	1.263ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	3.470s	477.220us	10	10	100.00
		lc_ctrl_jtag_csr_rw	2.850s	98.054us	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	50.920s	2.402ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	11.010s	1.902ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.960s	44.767us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.980s	1.571ms	10	10	100.00
		lc_ctrl_jtag_alert_test	2.050s	96.958us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	36.320s	13.849ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.300s	21.571us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.361m	20.558ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.340s	23.998us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.940s	261.930us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.940s	261.930us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.200s	15.832us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	16.693us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	24.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	188.211us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.200s	15.832us	5	5	100.00
		lc_ctrl_csr_rw	1.050s	16.693us	20	20	100.00
		lc_ctrl_csr_aliasing	1.330s	24.156us	5	5	100.00
		lc_ctrl_same_csr_outstanding	2.070s	188.211us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
		lc_ctrl_tl_intg_err	5.370s	1.112ms	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	5.370s	1.112ms	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	23.480s	349.476us	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.810s	259.648us	50	50	100.00
		lc_ctrl_sec_cm	42.480s	833.405us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	16.180s	763.438us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.680s	85.431us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	36.250s	4.606ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	21.510s	461.516us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	21.510s	461.516us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.450s	2.115ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	21.800s	2.512ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	21.800s	2.512ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.944h	29.521ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			1002	1030	97.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.86	97.82	95.66	93.31	97.62	98.52	99.00	96.11

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 24 failures.

    • 1.lc_ctrl_stress_all_with_rand_reset.83916598469163406906418568129781692421945530038057407364346877949707617184051
      Line 43345, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 68029140378 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 68029140378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 5.lc_ctrl_stress_all_with_rand_reset.114600234826178292958638086903250547082938806329474452726673397715239745235029
      Line 334, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 620862718 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 620862718 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 2 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 2 failures.

    • 26.lc_ctrl_stress_all_with_rand_reset.67150965026026245020642170618108724854998903017865701645270130924521124654180
      Line 4676, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 20867345647 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 20867345647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.lc_ctrl_stress_all_with_rand_reset.18188045796603932212551806279717422718781075420354390864344309797447909006562
      Line 30743, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 27539464009 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 27539464009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 27.lc_ctrl_stress_all_with_rand_reset.19134004446028079066247336864850694489495681739361027299440247259658570707834
      Line 51007, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 759454600461 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 759454600461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[CNST-STOF] Constraint solver timeout failure has 1 failures:

  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 28.lc_ctrl_stress_all_with_rand_reset.28573090674008997825874854522115600059716932179429638213661115517428763578685
      Line 47419, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        Error-[CNST-STOF] Constraint solver timeout failure
        ../src/lowrisc_dv_sec_cm_0/prim_sparse_fsm_flop_if.sv, 43
          Exceeded cpu time limit during solve.
          Please use the run-time switch +ntb_solver_cpu_limit to increase the cpu
          limit.  The default cpu limit is 1000 seconds per partition.
      

Past Results

• Latest
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• 2024.04.24_08.00.56
• 2024.04.22_07.24.48