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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.99 97.92 95.84 93.40 97.62 98.52 99.00 96.64


Total test records in report: 1004
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T815 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1411132458 Aug 27 06:59:39 AM UTC 24 Aug 27 06:59:41 AM UTC 24 18766651 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3883984896 Aug 27 06:57:44 AM UTC 24 Aug 27 06:59:41 AM UTC 24 4165358026 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3317387608 Aug 27 06:59:37 AM UTC 24 Aug 27 06:59:41 AM UTC 24 61841021 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1676142777 Aug 27 06:59:23 AM UTC 24 Aug 27 06:59:42 AM UTC 24 2072342640 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3514807904 Aug 27 06:59:33 AM UTC 24 Aug 27 06:59:43 AM UTC 24 336962593 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4142384360 Aug 27 06:58:45 AM UTC 24 Aug 27 07:00:19 AM UTC 24 11006759932 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1039280667 Aug 27 06:59:29 AM UTC 24 Aug 27 06:59:43 AM UTC 24 372146769 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1174830331 Aug 27 06:59:35 AM UTC 24 Aug 27 06:59:44 AM UTC 24 466966627 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.4284920533 Aug 27 06:59:33 AM UTC 24 Aug 27 06:59:45 AM UTC 24 391735548 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3162581028 Aug 27 06:59:40 AM UTC 24 Aug 27 06:59:45 AM UTC 24 266636974 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.3592829443 Aug 27 06:59:14 AM UTC 24 Aug 27 06:59:45 AM UTC 24 375618464 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1086203290 Aug 27 06:59:29 AM UTC 24 Aug 27 06:59:46 AM UTC 24 824534729 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.818998238 Aug 27 06:59:33 AM UTC 24 Aug 27 06:59:46 AM UTC 24 1211947302 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.3926843382 Aug 27 06:59:44 AM UTC 24 Aug 27 06:59:47 AM UTC 24 14237818 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.415323316 Aug 27 06:59:44 AM UTC 24 Aug 27 06:59:47 AM UTC 24 20239229 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.720113842 Aug 27 06:59:35 AM UTC 24 Aug 27 06:59:48 AM UTC 24 1835359776 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3088008747 Aug 27 06:59:35 AM UTC 24 Aug 27 06:59:49 AM UTC 24 220787917 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1315727754 Aug 27 06:59:36 AM UTC 24 Aug 27 06:59:49 AM UTC 24 357374322 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.422220922 Aug 27 06:59:41 AM UTC 24 Aug 27 06:59:49 AM UTC 24 170711993 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3640384796 Aug 27 06:59:28 AM UTC 24 Aug 27 06:59:50 AM UTC 24 8324501475 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.173220489 Aug 27 06:59:46 AM UTC 24 Aug 27 06:59:50 AM UTC 24 35642127 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2994104544 Aug 27 06:56:11 AM UTC 24 Aug 27 06:59:50 AM UTC 24 43254481486 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2801360295 Aug 27 06:59:41 AM UTC 24 Aug 27 06:59:50 AM UTC 24 1887301111 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3295787309 Aug 27 06:59:41 AM UTC 24 Aug 27 06:59:50 AM UTC 24 220352442 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2204119520 Aug 27 06:59:40 AM UTC 24 Aug 27 06:59:50 AM UTC 24 272210114 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2504416092 Aug 27 06:59:44 AM UTC 24 Aug 27 06:59:51 AM UTC 24 94361216 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1101748715 Aug 27 06:59:22 AM UTC 24 Aug 27 06:59:52 AM UTC 24 977529629 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.1924741516 Aug 27 06:59:50 AM UTC 24 Aug 27 06:59:52 AM UTC 24 48648538 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2707824112 Aug 27 06:59:25 AM UTC 24 Aug 27 06:59:53 AM UTC 24 338856468 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2872945849 Aug 27 06:59:43 AM UTC 24 Aug 27 06:59:54 AM UTC 24 822524706 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.605264152 Aug 27 06:59:33 AM UTC 24 Aug 27 06:59:54 AM UTC 24 420777743 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3152438451 Aug 27 06:59:41 AM UTC 24 Aug 27 06:59:54 AM UTC 24 427801922 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.3548493452 Aug 27 06:59:46 AM UTC 24 Aug 27 06:59:55 AM UTC 24 55228258 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.882534364 Aug 27 06:59:47 AM UTC 24 Aug 27 06:59:58 AM UTC 24 730718312 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.2800454259 Aug 27 06:59:47 AM UTC 24 Aug 27 06:59:58 AM UTC 24 276829796 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1872514452 Aug 27 06:59:48 AM UTC 24 Aug 27 06:59:58 AM UTC 24 563969237 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.3967350027 Aug 27 06:59:47 AM UTC 24 Aug 27 06:59:59 AM UTC 24 903515469 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4116738344 Aug 27 06:59:43 AM UTC 24 Aug 27 07:00:01 AM UTC 24 692835741 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.515732899 Aug 27 06:58:45 AM UTC 24 Aug 27 07:00:01 AM UTC 24 1800211172 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.1929729890 Aug 27 06:59:40 AM UTC 24 Aug 27 07:00:02 AM UTC 24 849376298 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1412425872 Aug 27 06:59:48 AM UTC 24 Aug 27 07:00:03 AM UTC 24 348037934 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.603051396 Aug 27 06:57:55 AM UTC 24 Aug 27 07:00:04 AM UTC 24 5854348758 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1081540705 Aug 27 06:59:48 AM UTC 24 Aug 27 07:00:04 AM UTC 24 413389677 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3191794720 Aug 27 06:59:46 AM UTC 24 Aug 27 07:00:08 AM UTC 24 541660308 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3710039935 Aug 27 06:59:43 AM UTC 24 Aug 27 07:00:21 AM UTC 24 7416427566 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1095207681 Aug 27 06:58:30 AM UTC 24 Aug 27 07:00:27 AM UTC 24 13202281486 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.4071417766 Aug 27 06:59:18 AM UTC 24 Aug 27 07:00:32 AM UTC 24 3086370174 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1255956586 Aug 27 06:57:25 AM UTC 24 Aug 27 07:00:35 AM UTC 24 12452695518 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3297060118 Aug 27 06:59:29 AM UTC 24 Aug 27 07:00:36 AM UTC 24 3745684484 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2657178585 Aug 27 06:58:49 AM UTC 24 Aug 27 07:00:38 AM UTC 24 13385729345 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.319343631 Aug 27 06:54:04 AM UTC 24 Aug 27 07:00:38 AM UTC 24 52554587461 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3317348276 Aug 27 06:56:54 AM UTC 24 Aug 27 07:00:47 AM UTC 24 18989944434 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1920339990 Aug 27 06:59:05 AM UTC 24 Aug 27 07:00:50 AM UTC 24 11483922409 ps
T125 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2857039293 Aug 27 06:59:29 AM UTC 24 Aug 27 07:00:53 AM UTC 24 16201797189 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.188660234 Aug 27 06:58:36 AM UTC 24 Aug 27 07:00:58 AM UTC 24 6083772754 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2924590218 Aug 27 06:58:19 AM UTC 24 Aug 27 07:01:01 AM UTC 24 17201692078 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2424280040 Aug 27 06:58:59 AM UTC 24 Aug 27 07:01:14 AM UTC 24 8188238271 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.1860962257 Aug 27 06:59:50 AM UTC 24 Aug 27 07:01:19 AM UTC 24 12115614293 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3234030109 Aug 27 06:56:45 AM UTC 24 Aug 27 07:01:33 AM UTC 24 56283168741 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.790665945 Aug 27 06:57:18 AM UTC 24 Aug 27 07:01:46 AM UTC 24 9135049451 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.358945670 Aug 27 06:58:54 AM UTC 24 Aug 27 07:02:21 AM UTC 24 6173532414 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1828121500 Aug 27 06:59:11 AM UTC 24 Aug 27 07:02:36 AM UTC 24 42896907919 ps
T123 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2001243672 Aug 27 06:58:36 AM UTC 24 Aug 27 07:02:44 AM UTC 24 57422317602 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.101243120 Aug 27 06:59:37 AM UTC 24 Aug 27 07:02:52 AM UTC 24 11011704718 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.507009339 Aug 27 06:58:03 AM UTC 24 Aug 27 07:03:19 AM UTC 24 46359732892 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2237166297 Aug 27 06:58:26 AM UTC 24 Aug 27 07:04:09 AM UTC 24 16681068153 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.856084765 Aug 27 06:58:14 AM UTC 24 Aug 27 07:05:04 AM UTC 24 36416590134 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.581969393 Aug 27 06:59:43 AM UTC 24 Aug 27 07:08:07 AM UTC 24 63017700146 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3325855165 Aug 27 06:56:22 AM UTC 24 Aug 27 07:15:27 AM UTC 24 75431681378 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.855853637 Aug 27 06:59:52 AM UTC 24 Aug 27 06:59:54 AM UTC 24 31657867 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2118516404 Aug 27 06:59:52 AM UTC 24 Aug 27 06:59:55 AM UTC 24 245009682 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1358366366 Aug 27 06:59:52 AM UTC 24 Aug 27 06:59:55 AM UTC 24 89760374 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2967479455 Aug 27 06:59:53 AM UTC 24 Aug 27 06:59:56 AM UTC 24 190748384 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.404123942 Aug 27 06:59:54 AM UTC 24 Aug 27 06:59:57 AM UTC 24 36928518 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.84778110 Aug 27 06:59:54 AM UTC 24 Aug 27 06:59:57 AM UTC 24 12230768 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.991534585 Aug 27 06:59:53 AM UTC 24 Aug 27 06:59:57 AM UTC 24 106772681 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2904056165 Aug 27 06:59:53 AM UTC 24 Aug 27 06:59:57 AM UTC 24 1070385230 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2839139223 Aug 27 06:59:54 AM UTC 24 Aug 27 06:59:57 AM UTC 24 21360491 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1255232353 Aug 27 06:59:51 AM UTC 24 Aug 27 06:59:57 AM UTC 24 1022997299 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3006972740 Aug 27 06:59:56 AM UTC 24 Aug 27 06:59:58 AM UTC 24 23827409 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.97304401 Aug 27 06:59:56 AM UTC 24 Aug 27 06:59:58 AM UTC 24 238358438 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2675227905 Aug 27 06:59:56 AM UTC 24 Aug 27 06:59:58 AM UTC 24 27891603 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1848713107 Aug 27 06:59:56 AM UTC 24 Aug 27 06:59:59 AM UTC 24 35143126 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4209512717 Aug 27 06:59:56 AM UTC 24 Aug 27 06:59:59 AM UTC 24 99363624 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1173294476 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:01 AM UTC 24 17843710 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2723346532 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:02 AM UTC 24 200570427 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2165941663 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:02 AM UTC 24 180045028 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3918583008 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:02 AM UTC 24 153489906 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.188451005 Aug 27 06:59:52 AM UTC 24 Aug 27 07:00:02 AM UTC 24 334043141 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2330388685 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:02 AM UTC 24 253394533 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1006896238 Aug 27 06:59:52 AM UTC 24 Aug 27 07:00:04 AM UTC 24 1787880441 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3560310805 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 13090407 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1784794407 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 29150751 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1366318517 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 14369746 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3140640753 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 17032179 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1261871994 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 94465024 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.58779921 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:06 AM UTC 24 241908876 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2639748074 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:07 AM UTC 24 164577313 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3549839036 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:08 AM UTC 24 412659690 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.23170590 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:09 AM UTC 24 48905257 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1617605117 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:09 AM UTC 24 13876929 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3208464213 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:09 AM UTC 24 28947657 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.676803023 Aug 27 06:59:57 AM UTC 24 Aug 27 07:00:09 AM UTC 24 492186061 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.848796723 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:09 AM UTC 24 35555593 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.472985291 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:09 AM UTC 24 26916886 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1741167551 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:09 AM UTC 24 54288883 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4222195692 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:09 AM UTC 24 261063658 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1255026583 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:09 AM UTC 24 93396479 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3734193773 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:09 AM UTC 24 57899888 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2546894188 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 23154415 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2815457488 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:10 AM UTC 24 66115418 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2600359492 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:15 AM UTC 24 97670713 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2054092241 Aug 27 06:59:58 AM UTC 24 Aug 27 07:00:10 AM UTC 24 1687268128 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020598418 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:10 AM UTC 24 346372691 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2530990881 Aug 27 07:00:08 AM UTC 24 Aug 27 07:00:11 AM UTC 24 216503693 ps
T140 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.571752329 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:11 AM UTC 24 67356389 ps
T136 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1609529349 Aug 27 07:00:08 AM UTC 24 Aug 27 07:00:11 AM UTC 24 27029976 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3672187310 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:11 AM UTC 24 347614852 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.319812187 Aug 27 07:00:06 AM UTC 24 Aug 27 07:00:11 AM UTC 24 89780596 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.674167032 Aug 27 07:00:09 AM UTC 24 Aug 27 07:00:12 AM UTC 24 139083594 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877391000 Aug 27 07:00:08 AM UTC 24 Aug 27 07:00:12 AM UTC 24 3204782342 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.250117592 Aug 27 07:00:09 AM UTC 24 Aug 27 07:00:12 AM UTC 24 39271951 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3356849448 Aug 27 07:00:08 AM UTC 24 Aug 27 07:00:12 AM UTC 24 128980335 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4227899610 Aug 27 07:00:10 AM UTC 24 Aug 27 07:00:12 AM UTC 24 358495510 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.474222545 Aug 27 07:00:10 AM UTC 24 Aug 27 07:00:12 AM UTC 24 29941068 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.918569296 Aug 27 07:00:10 AM UTC 24 Aug 27 07:00:12 AM UTC 24 80071742 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2908109318 Aug 27 07:00:09 AM UTC 24 Aug 27 07:00:13 AM UTC 24 1013729304 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.128178769 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:14 AM UTC 24 24055924 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.468141819 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:14 AM UTC 24 152186465 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.180891900 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:14 AM UTC 24 48831175 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.812469555 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:14 AM UTC 24 1698201299 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3282412004 Aug 27 07:00:07 AM UTC 24 Aug 27 07:00:15 AM UTC 24 2173569178 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.659026374 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:15 AM UTC 24 17900990 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4155426229 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:15 AM UTC 24 15729161 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3226778808 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 149713576 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.487333585 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 42972340 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3074983648 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 62176858 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1598316310 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 59484668 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2087482388 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:16 AM UTC 24 170345079 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1210008063 Aug 27 07:00:01 AM UTC 24 Aug 27 07:00:16 AM UTC 24 474350308 ps
T914 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1425605276 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:16 AM UTC 24 680050701 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1383005642 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:16 AM UTC 24 239549249 ps
T915 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1897920947 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:17 AM UTC 24 52311923 ps
T916 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3810047453 Aug 27 07:00:15 AM UTC 24 Aug 27 07:00:17 AM UTC 24 47900316 ps
T917 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2283748775 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:18 AM UTC 24 13768811 ps
T918 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1679786114 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:17 AM UTC 24 89861458 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.353741385 Aug 27 07:00:15 AM UTC 24 Aug 27 07:00:18 AM UTC 24 244952905 ps
T919 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1263443414 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:18 AM UTC 24 16101701 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2104890740 Aug 27 07:00:15 AM UTC 24 Aug 27 07:00:19 AM UTC 24 59242020 ps
T920 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3644111855 Aug 27 07:00:17 AM UTC 24 Aug 27 07:00:19 AM UTC 24 68704221 ps
T921 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.647415809 Aug 27 07:00:14 AM UTC 24 Aug 27 07:00:19 AM UTC 24 1303645708 ps
T922 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3494605611 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:19 AM UTC 24 152238933 ps
T923 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1974992063 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:19 AM UTC 24 331878374 ps
T924 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2563383905 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:19 AM UTC 24 31692623 ps
T925 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4191476309 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:20 AM UTC 24 169213894 ps
T926 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3040565158 Aug 27 07:00:17 AM UTC 24 Aug 27 07:00:20 AM UTC 24 88143709 ps
T927 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.263763591 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:20 AM UTC 24 75931559 ps
T928 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1014870750 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:20 AM UTC 24 11836252 ps
T929 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1038999224 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:21 AM UTC 24 292903994 ps
T930 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2957469099 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:21 AM UTC 24 59261787 ps
T931 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.42385164 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:21 AM UTC 24 809468999 ps
T932 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2594324056 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:21 AM UTC 24 267117838 ps
T933 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.435231204 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:22 AM UTC 24 514855136 ps
T934 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.344424164 Aug 27 07:00:11 AM UTC 24 Aug 27 07:00:22 AM UTC 24 691582060 ps
T935 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3050800507 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:22 AM UTC 24 708793662 ps
T936 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2418054991 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:22 AM UTC 24 456676363 ps
T937 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1787890287 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:22 AM UTC 24 52275909 ps
T938 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3788036606 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:22 AM UTC 24 70010300 ps
T939 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1760868097 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 62711141 ps
T940 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1778233311 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 78179190 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2158892896 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 118225255 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2127019184 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:23 AM UTC 24 109349020 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2157221195 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 231020518 ps
T941 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1512820637 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 102137570 ps
T942 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4271153781 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:23 AM UTC 24 457344163 ps
T943 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3598478204 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:24 AM UTC 24 28417492 ps
T944 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1011583812 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:24 AM UTC 24 147333701 ps
T945 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3376269796 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:24 AM UTC 24 52709878 ps
T946 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.97492483 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:24 AM UTC 24 78499278 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2750690560 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:26 AM UTC 24 22691300 ps
T947 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1697332901 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:26 AM UTC 24 111217982 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3587383061 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 11636500 ps
T948 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.268627394 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 41567657 ps
T949 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.964290183 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 369718281 ps
T950 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.616802648 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 24446463 ps
T951 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3819742600 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:27 AM UTC 24 243541133 ps
T952 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2308237600 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 290091849 ps
T953 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1806249425 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:27 AM UTC 24 204116844 ps
T954 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.825408218 Aug 27 07:00:00 AM UTC 24 Aug 27 07:00:27 AM UTC 24 967880522 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.243274441 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:28 AM UTC 24 65724094 ps
T955 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1207337447 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:28 AM UTC 24 15784888 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1850281194 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:28 AM UTC 24 201998942 ps
T956 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2074884512 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:28 AM UTC 24 209739581 ps
T957 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2295611847 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:28 AM UTC 24 131959765 ps
T958 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.612428555 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:28 AM UTC 24 80596972 ps
T959 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2584356910 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:28 AM UTC 24 66084987 ps
T960 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3737754813 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:29 AM UTC 24 129053484 ps
T961 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.521043751 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:29 AM UTC 24 2702379963 ps
T962 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1232515721 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:33 AM UTC 24 38204583 ps
T963 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3315610685 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:29 AM UTC 24 353566599 ps
T964 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2295452666 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:33 AM UTC 24 329543243 ps
T965 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3519378394 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:29 AM UTC 24 1159133856 ps
T966 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2699525183 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:29 AM UTC 24 40444659 ps
T967 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3211908664 Aug 27 07:00:18 AM UTC 24 Aug 27 07:00:29 AM UTC 24 3339017757 ps
T968 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2234573042 Aug 27 07:00:27 AM UTC 24 Aug 27 07:00:29 AM UTC 24 34855819 ps
T969 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.327160071 Aug 27 07:00:27 AM UTC 24 Aug 27 07:00:30 AM UTC 24 457447541 ps
T970 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2764000198 Aug 27 07:00:27 AM UTC 24 Aug 27 07:00:31 AM UTC 24 69276599 ps
T138 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1329717378 Aug 27 07:00:26 AM UTC 24 Aug 27 07:00:31 AM UTC 24 219289763 ps
T971 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.598510596 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:32 AM UTC 24 38676116 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.44133221 Aug 27 07:00:27 AM UTC 24 Aug 27 07:00:31 AM UTC 24 77217088 ps
T972 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.417960216 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:31 AM UTC 24 18655877 ps
T973 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2673703046 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:31 AM UTC 24 32185701 ps
T974 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1381523525 Aug 27 07:00:16 AM UTC 24 Aug 27 07:00:32 AM UTC 24 2399861198 ps
T975 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2264492546 Aug 27 07:00:30 AM UTC 24 Aug 27 07:00:32 AM UTC 24 56037868 ps
T976 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.342288099 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:32 AM UTC 24 12604317 ps
T977 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1319246821 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:32 AM UTC 24 59927648 ps
T978 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4071958060 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:32 AM UTC 24 226505656 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4049636560 Aug 27 07:00:30 AM UTC 24 Aug 27 07:00:32 AM UTC 24 26452088 ps
T979 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3839101590 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:32 AM UTC 24 87397086 ps
T980 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1727807267 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:32 AM UTC 24 46234535 ps
T981 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1290931873 Aug 27 07:00:30 AM UTC 24 Aug 27 07:00:32 AM UTC 24 25456855 ps
T982 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.100978852 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:33 AM UTC 24 30815519 ps
T983 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3039557289 Aug 27 07:00:22 AM UTC 24 Aug 27 07:00:33 AM UTC 24 3737189935 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1385271543 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:33 AM UTC 24 33477066 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3697413495 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:33 AM UTC 24 74189859 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3843009627 Aug 27 07:00:30 AM UTC 24 Aug 27 07:00:33 AM UTC 24 68011101 ps
T984 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2475489022 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:34 AM UTC 24 41127850 ps
T985 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1186889694 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:34 AM UTC 24 207998135 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.342388295 Aug 27 07:00:29 AM UTC 24 Aug 27 07:00:34 AM UTC 24 121266011 ps
T986 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.27125738 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:34 AM UTC 24 135375278 ps
T137 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2725478440 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:35 AM UTC 24 925650585 ps
T987 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.56833456 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:35 AM UTC 24 15960832 ps
T988 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.509572117 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:35 AM UTC 24 16846245 ps
T989 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2281453954 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:35 AM UTC 24 30479140 ps
T990 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3721446463 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 50362335 ps
T991 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3316804144 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 67636905 ps
T992 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.988123918 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 130316192 ps
T993 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1955666368 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 85358448 ps
T994 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4182320768 Aug 27 07:00:31 AM UTC 24 Aug 27 07:00:36 AM UTC 24 358564442 ps
T995 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2660975753 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 29244568 ps
T996 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4192336278 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 52463868 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2157370048 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:36 AM UTC 24 44167256 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3281147835 Aug 27 07:00:35 AM UTC 24 Aug 27 07:00:37 AM UTC 24 36345544 ps
T997 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3466673749 Aug 27 07:00:35 AM UTC 24 Aug 27 07:00:37 AM UTC 24 18140414 ps
T998 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2353711972 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:37 AM UTC 24 158029456 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3504409592 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:37 AM UTC 24 114179317 ps
T999 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.900882821 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:38 AM UTC 24 168575324 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1809699536 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:38 AM UTC 24 205789412 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.272808087 Aug 27 07:00:35 AM UTC 24 Aug 27 07:00:38 AM UTC 24 81802925 ps
T1000 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2742569364 Aug 27 07:00:35 AM UTC 24 Aug 27 07:00:38 AM UTC 24 318544372 ps
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