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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.99 97.92 95.84 93.40 97.62 98.52 99.00 96.64


Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T1001 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3027511507 Aug 27 07:00:33 AM UTC 24 Aug 27 07:00:39 AM UTC 24 122680120 ps
T1002 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.343690820 Aug 27 07:00:24 AM UTC 24 Aug 27 07:00:43 AM UTC 24 829052723 ps
T1003 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1434909806 Aug 27 07:00:20 AM UTC 24 Aug 27 07:00:45 AM UTC 24 4760062034 ps
T1004 /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2824145844 Aug 27 07:00:13 AM UTC 24 Aug 27 07:00:46 AM UTC 24 20198551712 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.1910004892
Short name T15
Test name
Test status
Simulation time 642124318 ps
CPU time 7.67 seconds
Started Aug 27 06:53:48 AM UTC 24
Finished Aug 27 06:53:56 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910004892 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1910004892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.3145603347
Short name T14
Test name
Test status
Simulation time 973565881 ps
CPU time 15.97 seconds
Started Aug 27 06:53:49 AM UTC 24
Finished Aug 27 06:54:06 AM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145603347
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l
c_ctrl_jtag_state_post_trans.3145603347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.4269737875
Short name T57
Test name
Test status
Simulation time 384418131 ps
CPU time 10.48 seconds
Started Aug 27 06:54:03 AM UTC 24
Finished Aug 27 06:54:14 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269737875 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.4269737875
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1025776005
Short name T17
Test name
Test status
Simulation time 344622451 ps
CPU time 7.17 seconds
Started Aug 27 06:53:52 AM UTC 24
Finished Aug 27 06:54:00 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1025776005 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke
n_mux.1025776005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.35810068
Short name T7
Test name
Test status
Simulation time 301690535 ps
CPU time 5.29 seconds
Started Aug 27 06:53:50 AM UTC 24
Finished Aug 27 06:53:57 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35810068 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.35810068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3984734332
Short name T74
Test name
Test status
Simulation time 2365130226 ps
CPU time 83.76 seconds
Started Aug 27 06:54:27 AM UTC 24
Finished Aug 27 06:55:54 AM UTC 24
Peak memory 281368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984734332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3984734332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.2814244629
Short name T19
Test name
Test status
Simulation time 573582984 ps
CPU time 9.96 seconds
Started Aug 27 06:53:47 AM UTC 24
Finished Aug 27 06:53:59 AM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814244629 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.2814244629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.4209512717
Short name T128
Test name
Test status
Simulation time 99363624 ps
CPU time 2.33 seconds
Started Aug 27 06:59:56 AM UTC 24
Finished Aug 27 06:59:59 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=4209512717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.4209512717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2412439485
Short name T64
Test name
Test status
Simulation time 921524510 ps
CPU time 17.13 seconds
Started Aug 27 06:53:54 AM UTC 24
Finished Aug 27 06:54:12 AM UTC 24
Peak memory 289852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412439485 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2412439485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3462141922
Short name T67
Test name
Test status
Simulation time 1161385283 ps
CPU time 17.75 seconds
Started Aug 27 06:53:59 AM UTC 24
Finished Aug 27 06:54:18 AM UTC 24
Peak memory 238168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462141922 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3462141922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2584987713
Short name T281
Test name
Test status
Simulation time 808179100 ps
CPU time 19.41 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:39 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584987713 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2584987713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2237166297
Short name T62
Test name
Test status
Simulation time 16681068153 ps
CPU time 338.33 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 07:04:09 AM UTC 24
Peak memory 263100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2237166297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 35.lc_ctrl_stress_all.2237166297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.1312004724
Short name T46
Test name
Test status
Simulation time 2521291646 ps
CPU time 37.14 seconds
Started Aug 27 06:53:49 AM UTC 24
Finished Aug 27 06:54:27 AM UTC 24
Peak memory 262624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312004724
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_c
trl_jtag_state_failure.1312004724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3356849448
Short name T143
Test name
Test status
Simulation time 128980335 ps
CPU time 2.82 seconds
Started Aug 27 07:00:08 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3356849448 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_t
l_intg_err.3356849448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.3472135981
Short name T103
Test name
Test status
Simulation time 46649538 ps
CPU time 1.58 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:09 AM UTC 24
Peak memory 218720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472135981 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3472135981
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1366318517
Short name T238
Test name
Test status
Simulation time 14369746 ps
CPU time 1.15 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366318517 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_
aliasing.1366318517
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1358366366
Short name T129
Test name
Test status
Simulation time 89760374 ps
CPU time 2.45 seconds
Started Aug 27 06:59:52 AM UTC 24
Finished Aug 27 06:59:55 AM UTC 24
Peak memory 235852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1358366366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1358366366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.851567272
Short name T26
Test name
Test status
Simulation time 365469367 ps
CPU time 13.59 seconds
Started Aug 27 06:53:48 AM UTC 24
Finished Aug 27 06:54:02 AM UTC 24
Peak memory 229944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851567272 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.851567272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.4183938078
Short name T58
Test name
Test status
Simulation time 12624778553 ps
CPU time 80.16 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:56:09 AM UTC 24
Peak memory 281636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183938078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.4183938078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.2437598482
Short name T13
Test name
Test status
Simulation time 569907501 ps
CPU time 8.04 seconds
Started Aug 27 06:53:49 AM UTC 24
Finished Aug 27 06:53:58 AM UTC 24
Peak memory 236284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437598482
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_jtag_prog_failure.2437598482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.3939807166
Short name T63
Test name
Test status
Simulation time 90799716 ps
CPU time 9.73 seconds
Started Aug 27 06:53:57 AM UTC 24
Finished Aug 27 06:54:08 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939807166 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3939807166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3918583008
Short name T130
Test name
Test status
Simulation time 153489906 ps
CPU time 2.52 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918583008 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.3918583008
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2725478440
Short name T137
Test name
Test status
Simulation time 925650585 ps
CPU time 2.62 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:35 AM UTC 24
Peak memory 235636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725478440 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
tl_intg_err.2725478440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.3144403901
Short name T602
Test name
Test status
Simulation time 1848299485 ps
CPU time 64.91 seconds
Started Aug 27 06:56:38 AM UTC 24
Finished Aug 27 06:57:44 AM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144403901
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_errors.3144403901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3852635353
Short name T314
Test name
Test status
Simulation time 1059132304 ps
CPU time 23.82 seconds
Started Aug 27 06:54:39 AM UTC 24
Finished Aug 27 06:55:04 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852635353 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3852635353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.4195840095
Short name T10
Test name
Test status
Simulation time 774041016 ps
CPU time 10.1 seconds
Started Aug 27 06:54:12 AM UTC 24
Finished Aug 27 06:54:23 AM UTC 24
Peak memory 230096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195840095 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.4195840095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.3510900678
Short name T25
Test name
Test status
Simulation time 644662283 ps
CPU time 10.07 seconds
Started Aug 27 06:53:52 AM UTC 24
Finished Aug 27 06:54:03 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510900678 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3510900678
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1329717378
Short name T138
Test name
Test status
Simulation time 219289763 ps
CPU time 4.13 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:31 AM UTC 24
Peak memory 229960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329717378 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
tl_intg_err.1329717378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.202595158
Short name T171
Test name
Test status
Simulation time 1309608253 ps
CPU time 11.43 seconds
Started Aug 27 06:55:42 AM UTC 24
Finished Aug 27 06:55:54 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202595158 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.202595158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.1837694586
Short name T72
Test name
Test status
Simulation time 1857732654 ps
CPU time 34.13 seconds
Started Aug 27 06:54:38 AM UTC 24
Finished Aug 27 06:55:13 AM UTC 24
Peak memory 291904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837694586 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1837694586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2330388685
Short name T131
Test name
Test status
Simulation time 253394533 ps
CPU time 2.86 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 235796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330388685 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_t
l_intg_err.2330388685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2157221195
Short name T151
Test name
Test status
Simulation time 231020518 ps
CPU time 2 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 232468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157221195 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_t
l_intg_err.2157221195
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2127019184
Short name T152
Test name
Test status
Simulation time 109349020 ps
CPU time 4.03 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127019184 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_t
l_intg_err.2127019184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.84778110
Short name T159
Test name
Test status
Simulation time 12230768 ps
CPU time 1.41 seconds
Started Aug 27 06:59:54 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84778110 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.84778110
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3104205280
Short name T109
Test name
Test status
Simulation time 24519417919 ps
CPU time 118.51 seconds
Started Aug 27 06:57:19 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 285604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104205280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3104205280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.3092137854
Short name T77
Test name
Test status
Simulation time 109341597 ps
CPU time 2.85 seconds
Started Aug 27 06:55:38 AM UTC 24
Finished Aug 27 06:55:42 AM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092137854 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3092137854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.4038054237
Short name T2
Test name
Test status
Simulation time 12936098 ps
CPU time 1.23 seconds
Started Aug 27 06:53:48 AM UTC 24
Finished Aug 27 06:53:50 AM UTC 24
Peak memory 217236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4038054237 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.4038054237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.991534585
Short name T126
Test name
Test status
Simulation time 106772681 ps
CPU time 2.85 seconds
Started Aug 27 06:59:53 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 229524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991534585 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl
_intg_err.991534585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3520495493
Short name T4
Test name
Test status
Simulation time 434955222 ps
CPU time 3.78 seconds
Started Aug 27 06:53:46 AM UTC 24
Finished Aug 27 06:53:51 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520495493 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3520495493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.976809
Short name T1
Test name
Test status
Simulation time 213674001 ps
CPU time 1.37 seconds
Started Aug 27 06:53:45 AM UTC 24
Finished Aug 27 06:53:47 AM UTC 24
Peak memory 223232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976809 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc
_ctrl_volatile_unlock_smoke.976809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.25054295
Short name T252
Test name
Test status
Simulation time 20789112 ps
CPU time 1.23 seconds
Started Aug 27 06:54:00 AM UTC 24
Finished Aug 27 06:54:02 AM UTC 24
Peak memory 218800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25054295 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.25054295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.4116189457
Short name T260
Test name
Test status
Simulation time 35941726 ps
CPU time 1.23 seconds
Started Aug 27 06:54:09 AM UTC 24
Finished Aug 27 06:54:12 AM UTC 24
Peak memory 217304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116189457 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4116189457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.2863473806
Short name T257
Test name
Test status
Simulation time 42560392 ps
CPU time 1.15 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:54:53 AM UTC 24
Peak memory 219056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863473806 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.2863473806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.1302002808
Short name T258
Test name
Test status
Simulation time 11378429 ps
CPU time 1.2 seconds
Started Aug 27 06:55:00 AM UTC 24
Finished Aug 27 06:55:02 AM UTC 24
Peak memory 217236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302002808 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1302002808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.3300425657
Short name T259
Test name
Test status
Simulation time 13449028 ps
CPU time 1.02 seconds
Started Aug 27 06:55:18 AM UTC 24
Finished Aug 27 06:55:20 AM UTC 24
Peak memory 216936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300425657 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3300425657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2764000198
Short name T970
Test name
Test status
Simulation time 69276599 ps
CPU time 2.71 seconds
Started Aug 27 07:00:27 AM UTC 24
Finished Aug 27 07:00:31 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764000198 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2764000198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.44133221
Short name T153
Test name
Test status
Simulation time 77217088 ps
CPU time 2.83 seconds
Started Aug 27 07:00:27 AM UTC 24
Finished Aug 27 07:00:31 AM UTC 24
Peak memory 229884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44133221 -asse
rt nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl
_intg_err.44133221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.342388295
Short name T139
Test name
Test status
Simulation time 121266011 ps
CPU time 4.02 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:34 AM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342388295 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_t
l_intg_err.342388295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3504409592
Short name T157
Test name
Test status
Simulation time 114179317 ps
CPU time 3.12 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:37 AM UTC 24
Peak memory 235628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504409592 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
tl_intg_err.3504409592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.319812187
Short name T132
Test name
Test status
Simulation time 89780596 ps
CPU time 3.96 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:11 AM UTC 24
Peak memory 229968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319812187 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl
_intg_err.319812187
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1819744354
Short name T190
Test name
Test status
Simulation time 3592788628 ps
CPU time 64.33 seconds
Started Aug 27 06:54:10 AM UTC 24
Finished Aug 27 06:55:16 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819744354
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_c
trl_jtag_state_failure.1819744354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3006972740
Short name T179
Test name
Test status
Simulation time 23827409 ps
CPU time 1.46 seconds
Started Aug 27 06:59:56 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 218492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006972740 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_
aliasing.3006972740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2839139223
Short name T879
Test name
Test status
Simulation time 21360491 ps
CPU time 1.72 seconds
Started Aug 27 06:59:54 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 218916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839139223 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_
bit_bash.2839139223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.404123942
Short name T158
Test name
Test status
Simulation time 36928518 ps
CPU time 1.39 seconds
Started Aug 27 06:59:54 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404123942 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_h
w_reset.404123942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2967479455
Short name T162
Test name
Test status
Simulation time 190748384 ps
CPU time 1.92 seconds
Started Aug 27 06:59:53 AM UTC 24
Finished Aug 27 06:59:56 AM UTC 24
Peak memory 218464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2967479455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2967479455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.188451005
Short name T882
Test name
Test status
Simulation time 334043141 ps
CPU time 9.43 seconds
Started Aug 27 06:59:52 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=188451005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.188451005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1006896238
Short name T883
Test name
Test status
Simulation time 1787880441 ps
CPU time 11.52 seconds
Started Aug 27 06:59:52 AM UTC 24
Finished Aug 27 07:00:04 AM UTC 24
Peak memory 218976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1006896238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1006896238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1255232353
Short name T161
Test name
Test status
Simulation time 1022997299 ps
CPU time 4.69 seconds
Started Aug 27 06:59:51 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 221376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1255232353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1255232353
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2118516404
Short name T134
Test name
Test status
Simulation time 245009682 ps
CPU time 2.17 seconds
Started Aug 27 06:59:52 AM UTC 24
Finished Aug 27 06:59:55 AM UTC 24
Peak memory 219324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2118516404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_csr_rw.2118516404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.855853637
Short name T133
Test name
Test status
Simulation time 31657867 ps
CPU time 1.73 seconds
Started Aug 27 06:59:52 AM UTC 24
Finished Aug 27 06:59:54 AM UTC 24
Peak memory 218964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=855853637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.855853637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2675227905
Short name T180
Test name
Test status
Simulation time 27891603 ps
CPU time 1.82 seconds
Started Aug 27 06:59:56 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26752
27905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
lc_ctrl_same_csr_outstanding.2675227905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2904056165
Short name T127
Test name
Test status
Simulation time 1070385230 ps
CPU time 3 seconds
Started Aug 27 06:59:53 AM UTC 24
Finished Aug 27 06:59:57 AM UTC 24
Peak memory 231836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904056165 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2904056165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2639748074
Short name T886
Test name
Test status
Simulation time 164577313 ps
CPU time 2.09 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:07 AM UTC 24
Peak memory 218264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639748074 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_
bit_bash.2639748074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1784794407
Short name T884
Test name
Test status
Simulation time 29150751 ps
CPU time 1.12 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784794407 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_
hw_reset.1784794407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1261871994
Short name T181
Test name
Test status
Simulation time 94465024 ps
CPU time 1.5 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1261871994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1261871994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3560310805
Short name T247
Test name
Test status
Simulation time 13090407 ps
CPU time 1.06 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 218516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560310805 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3560310805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2165941663
Short name T881
Test name
Test status
Simulation time 180045028 ps
CPU time 2.38 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 219180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2165941663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2165941663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2054092241
Short name T894
Test name
Test status
Simulation time 1687268128 ps
CPU time 10.61 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:10 AM UTC 24
Peak memory 219088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2054092241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2054092241
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.676803023
Short name T889
Test name
Test status
Simulation time 492186061 ps
CPU time 11.03 seconds
Started Aug 27 06:59:57 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 219388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=676803023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.676803023
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.97304401
Short name T880
Test name
Test status
Simulation time 238358438 ps
CPU time 1.54 seconds
Started Aug 27 06:59:56 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=97304401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.97304401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2723346532
Short name T192
Test name
Test status
Simulation time 200570427 ps
CPU time 2.4 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 229896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723346532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2723346532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1848713107
Short name T253
Test name
Test status
Simulation time 35143126 ps
CPU time 1.78 seconds
Started Aug 27 06:59:56 AM UTC 24
Finished Aug 27 06:59:59 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1848713107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_csr_rw.1848713107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1173294476
Short name T246
Test name
Test status
Simulation time 17843710 ps
CPU time 1.76 seconds
Started Aug 27 06:59:58 AM UTC 24
Finished Aug 27 07:00:01 AM UTC 24
Peak memory 218620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1173294476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1173294476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3140640753
Short name T248
Test name
Test status
Simulation time 17032179 ps
CPU time 1.18 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31406
40753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
lc_ctrl_same_csr_outstanding.3140640753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.612428555
Short name T958
Test name
Test status
Simulation time 80596972 ps
CPU time 1.32 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=612428555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.612428555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1207337447
Short name T955
Test name
Test status
Simulation time 15784888 ps
CPU time 0.95 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207337447 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1207337447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2699525183
Short name T966
Test name
Test status
Simulation time 40444659 ps
CPU time 1.98 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 228792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26995
25183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.lc_ctrl_same_csr_outstanding.2699525183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3737754813
Short name T960
Test name
Test status
Simulation time 129053484 ps
CPU time 1.82 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 228376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737754813 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3737754813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3839101590
Short name T979
Test name
Test status
Simulation time 87397086 ps
CPU time 1.73 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3839101590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3839101590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2234573042
Short name T968
Test name
Test status
Simulation time 34855819 ps
CPU time 1.22 seconds
Started Aug 27 07:00:27 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234573042 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2234573042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.327160071
Short name T969
Test name
Test status
Simulation time 457447541 ps
CPU time 1.6 seconds
Started Aug 27 07:00:27 AM UTC 24
Finished Aug 27 07:00:30 AM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32716
0071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
lc_ctrl_same_csr_outstanding.327160071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1319246821
Short name T977
Test name
Test status
Simulation time 59927648 ps
CPU time 1.32 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1319246821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1319246821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.417960216
Short name T972
Test name
Test status
Simulation time 18655877 ps
CPU time 1.04 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:31 AM UTC 24
Peak memory 218076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417960216 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.417960216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1727807267
Short name T980
Test name
Test status
Simulation time 46234535 ps
CPU time 1.64 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17278
07267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.lc_ctrl_same_csr_outstanding.1727807267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1232515721
Short name T962
Test name
Test status
Simulation time 38204583 ps
CPU time 2.7 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232515721 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1232515721
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.342288099
Short name T976
Test name
Test status
Simulation time 12604317 ps
CPU time 1.13 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=342288099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.342288099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2673703046
Short name T973
Test name
Test status
Simulation time 32185701 ps
CPU time 1.02 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:31 AM UTC 24
Peak memory 218512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673703046 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2673703046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.598510596
Short name T971
Test name
Test status
Simulation time 38676116 ps
CPU time 1.51 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59851
0596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
lc_ctrl_same_csr_outstanding.598510596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2295452666
Short name T964
Test name
Test status
Simulation time 329543243 ps
CPU time 2.49 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 229556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295452666 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2295452666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3697413495
Short name T154
Test name
Test status
Simulation time 74189859 ps
CPU time 2.92 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 229588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697413495 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
tl_intg_err.3697413495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2264492546
Short name T975
Test name
Test status
Simulation time 56037868 ps
CPU time 0.93 seconds
Started Aug 27 07:00:30 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2264492546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2264492546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4049636560
Short name T243
Test name
Test status
Simulation time 26452088 ps
CPU time 1.25 seconds
Started Aug 27 07:00:30 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049636560 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4049636560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1290931873
Short name T981
Test name
Test status
Simulation time 25456855 ps
CPU time 1.42 seconds
Started Aug 27 07:00:30 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12909
31873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.lc_ctrl_same_csr_outstanding.1290931873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1186889694
Short name T985
Test name
Test status
Simulation time 207998135 ps
CPU time 3.44 seconds
Started Aug 27 07:00:29 AM UTC 24
Finished Aug 27 07:00:34 AM UTC 24
Peak memory 231532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1186889694 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1186889694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3843009627
Short name T150
Test name
Test status
Simulation time 68011101 ps
CPU time 2.9 seconds
Started Aug 27 07:00:30 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843009627 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
tl_intg_err.3843009627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2475489022
Short name T984
Test name
Test status
Simulation time 41127850 ps
CPU time 1.63 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:34 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2475489022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2475489022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1385271543
Short name T244
Test name
Test status
Simulation time 33477066 ps
CPU time 1.24 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 218064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385271543 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1385271543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.100978852
Short name T982
Test name
Test status
Simulation time 30815519 ps
CPU time 1.11 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10097
8852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
lc_ctrl_same_csr_outstanding.100978852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.27125738
Short name T986
Test name
Test status
Simulation time 135375278 ps
CPU time 2.37 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:34 AM UTC 24
Peak memory 233664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27125738 -assert nopostpro
c +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.27125738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2660975753
Short name T995
Test name
Test status
Simulation time 29244568 ps
CPU time 1.79 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2660975753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2660975753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.56833456
Short name T987
Test name
Test status
Simulation time 15960832 ps
CPU time 1 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:35 AM UTC 24
Peak memory 218128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56833456 -assert nopost
proc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.56833456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3721446463
Short name T990
Test name
Test status
Simulation time 50362335 ps
CPU time 1.5 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 228552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37214
46463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.lc_ctrl_same_csr_outstanding.3721446463
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4182320768
Short name T994
Test name
Test status
Simulation time 358564442 ps
CPU time 3.63 seconds
Started Aug 27 07:00:31 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 229484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182320768 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.4182320768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2157370048
Short name T156
Test name
Test status
Simulation time 44167256 ps
CPU time 2.2 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 223364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157370048 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
tl_intg_err.2157370048
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3316804144
Short name T991
Test name
Test status
Simulation time 67636905 ps
CPU time 1.3 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 230364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3316804144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3316804144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.988123918
Short name T992
Test name
Test status
Simulation time 130316192 ps
CPU time 1.31 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988123918 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.988123918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2281453954
Short name T989
Test name
Test status
Simulation time 30479140 ps
CPU time 1.28 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:35 AM UTC 24
Peak memory 218600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22814
53954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.lc_ctrl_same_csr_outstanding.2281453954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.900882821
Short name T999
Test name
Test status
Simulation time 168575324 ps
CPU time 3.67 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 229576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900882821 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.900882821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1809699536
Short name T141
Test name
Test status
Simulation time 205789412 ps
CPU time 3.96 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 229960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809699536 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
tl_intg_err.1809699536
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4192336278
Short name T996
Test name
Test status
Simulation time 52463868 ps
CPU time 1.45 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=4192336278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4192336278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.509572117
Short name T988
Test name
Test status
Simulation time 16846245 ps
CPU time 1.13 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:35 AM UTC 24
Peak memory 218124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509572117 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.509572117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1955666368
Short name T993
Test name
Test status
Simulation time 85358448 ps
CPU time 1.29 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 218504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19556
66368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.lc_ctrl_same_csr_outstanding.1955666368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3027511507
Short name T1001
Test name
Test status
Simulation time 122680120 ps
CPU time 4.92 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:39 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027511507 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.3027511507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2742569364
Short name T1000
Test name
Test status
Simulation time 318544372 ps
CPU time 1.8 seconds
Started Aug 27 07:00:35 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2742569364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2742569364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3281147835
Short name T245
Test name
Test status
Simulation time 36345544 ps
CPU time 0.92 seconds
Started Aug 27 07:00:35 AM UTC 24
Finished Aug 27 07:00:37 AM UTC 24
Peak memory 219076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281147835 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3281147835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3466673749
Short name T997
Test name
Test status
Simulation time 18140414 ps
CPU time 1.11 seconds
Started Aug 27 07:00:35 AM UTC 24
Finished Aug 27 07:00:37 AM UTC 24
Peak memory 217560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34666
73749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.lc_ctrl_same_csr_outstanding.3466673749
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2353711972
Short name T998
Test name
Test status
Simulation time 158029456 ps
CPU time 2.9 seconds
Started Aug 27 07:00:33 AM UTC 24
Finished Aug 27 07:00:37 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353711972 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2353711972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.272808087
Short name T155
Test name
Test status
Simulation time 81802925 ps
CPU time 1.88 seconds
Started Aug 27 07:00:35 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 222224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272808087 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_t
l_intg_err.272808087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3208464213
Short name T888
Test name
Test status
Simulation time 28947657 ps
CPU time 1.39 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208464213 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_
aliasing.3208464213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.848796723
Short name T890
Test name
Test status
Simulation time 35555593 ps
CPU time 1.49 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848796723 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_b
it_bash.848796723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.23170590
Short name T239
Test name
Test status
Simulation time 48905257 ps
CPU time 1.12 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23170590 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw
_reset.23170590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3734193773
Short name T193
Test name
Test status
Simulation time 57899888 ps
CPU time 1.74 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3734193773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3734193773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1617605117
Short name T182
Test name
Test status
Simulation time 13876929 ps
CPU time 1.13 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617605117 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1617605117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1741167551
Short name T891
Test name
Test status
Simulation time 54288883 ps
CPU time 1.75 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=1741167551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1741167551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1210008063
Short name T913
Test name
Test status
Simulation time 474350308 ps
CPU time 10.59 seconds
Started Aug 27 07:00:01 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 219160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1210008063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1210008063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.825408218
Short name T954
Test name
Test status
Simulation time 967880522 ps
CPU time 22.37 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 218484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=825408218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.825408218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.58779921
Short name T885
Test name
Test status
Simulation time 241908876 ps
CPU time 1.49 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:06 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=58779921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.58779921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020598418
Short name T194
Test name
Test status
Simulation time 346372691 ps
CPU time 2.75 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:10 AM UTC 24
Peak memory 229636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020598418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4020598418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3549839036
Short name T887
Test name
Test status
Simulation time 412659690 ps
CPU time 3.11 seconds
Started Aug 27 07:00:00 AM UTC 24
Finished Aug 27 07:00:08 AM UTC 24
Peak memory 219188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3549839036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_csr_rw.3549839036
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1255026583
Short name T183
Test name
Test status
Simulation time 93396479 ps
CPU time 2.08 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 229436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1255026583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1255026583
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2815457488
Short name T250
Test name
Test status
Simulation time 66115418 ps
CPU time 2 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:10 AM UTC 24
Peak memory 218500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28154
57488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
lc_ctrl_same_csr_outstanding.2815457488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.571752329
Short name T140
Test name
Test status
Simulation time 67356389 ps
CPU time 3.42 seconds
Started Aug 27 07:00:06 AM UTC 24
Finished Aug 27 07:00:11 AM UTC 24
Peak memory 229520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571752329 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.571752329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.918569296
Short name T899
Test name
Test status
Simulation time 80071742 ps
CPU time 1.62 seconds
Started Aug 27 07:00:10 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 218520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918569296 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_a
liasing.918569296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2908109318
Short name T900
Test name
Test status
Simulation time 1013729304 ps
CPU time 1.85 seconds
Started Aug 27 07:00:09 AM UTC 24
Finished Aug 27 07:00:13 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908109318 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_
bit_bash.2908109318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.250117592
Short name T240
Test name
Test status
Simulation time 39271951 ps
CPU time 1.28 seconds
Started Aug 27 07:00:09 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250117592 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_h
w_reset.250117592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.474222545
Short name T898
Test name
Test status
Simulation time 29941068 ps
CPU time 1.44 seconds
Started Aug 27 07:00:10 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=474222545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.474222545
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.674167032
Short name T897
Test name
Test status
Simulation time 139083594 ps
CPU time 1.09 seconds
Started Aug 27 07:00:09 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 218772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674167032 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.674167032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2530990881
Short name T895
Test name
Test status
Simulation time 216503693 ps
CPU time 1.73 seconds
Started Aug 27 07:00:08 AM UTC 24
Finished Aug 27 07:00:11 AM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=2530990881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2530990881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.812469555
Short name T904
Test name
Test status
Simulation time 1698201299 ps
CPU time 6.16 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:14 AM UTC 24
Peak memory 218520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=812469555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.812469555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3282412004
Short name T905
Test name
Test status
Simulation time 2173569178 ps
CPU time 6.67 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:15 AM UTC 24
Peak memory 219420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3282412004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3282412004
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3672187310
Short name T896
Test name
Test status
Simulation time 347614852 ps
CPU time 3.2 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:11 AM UTC 24
Peak memory 221560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3672187310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3672187310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877391000
Short name T142
Test name
Test status
Simulation time 3204782342 ps
CPU time 2.71 seconds
Started Aug 27 07:00:08 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 236104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877391000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2877391000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4222195692
Short name T892
Test name
Test status
Simulation time 261063658 ps
CPU time 1.57 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=4222195692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_csr_rw.4222195692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.472985291
Short name T249
Test name
Test status
Simulation time 26916886 ps
CPU time 1.18 seconds
Started Aug 27 07:00:07 AM UTC 24
Finished Aug 27 07:00:09 AM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=472985291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.472985291
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.4227899610
Short name T251
Test name
Test status
Simulation time 358495510 ps
CPU time 1.31 seconds
Started Aug 27 07:00:10 AM UTC 24
Finished Aug 27 07:00:12 AM UTC 24
Peak memory 218572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42278
99610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
lc_ctrl_same_csr_outstanding.4227899610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1609529349
Short name T136
Test name
Test status
Simulation time 27029976 ps
CPU time 1.83 seconds
Started Aug 27 07:00:08 AM UTC 24
Finished Aug 27 07:00:11 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609529349 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1609529349
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2546894188
Short name T893
Test name
Test status
Simulation time 23154415 ps
CPU time 1.53 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 218336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546894188 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_
aliasing.2546894188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1598316310
Short name T911
Test name
Test status
Simulation time 59484668 ps
CPU time 1.81 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 218552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598316310 -asser
t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_
bit_bash.1598316310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.659026374
Short name T906
Test name
Test status
Simulation time 17900990 ps
CPU time 1.21 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:15 AM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659026374 -assert
nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_h
w_reset.659026374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.487333585
Short name T909
Test name
Test status
Simulation time 42972340 ps
CPU time 1.61 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 232408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=487333585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.487333585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4155426229
Short name T907
Test name
Test status
Simulation time 15729161 ps
CPU time 1.3 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:15 AM UTC 24
Peak memory 219132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4155426229 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4155426229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.128178769
Short name T901
Test name
Test status
Simulation time 24055924 ps
CPU time 1.28 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:14 AM UTC 24
Peak memory 218720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=128178769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.128178769
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.42385164
Short name T931
Test name
Test status
Simulation time 809468999 ps
CPU time 9.13 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:21 AM UTC 24
Peak memory 219052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=42385164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.42385164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.344424164
Short name T934
Test name
Test status
Simulation time 691582060 ps
CPU time 9.74 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 218560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=344424164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.344424164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1425605276
Short name T914
Test name
Test status
Simulation time 680050701 ps
CPU time 4.24 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 221228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1425605276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1425605276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.468141819
Short name T902
Test name
Test status
Simulation time 152186465 ps
CPU time 1.52 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:14 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468141819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.468141819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2600359492
Short name T160
Test name
Test status
Simulation time 97670713 ps
CPU time 3.12 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:15 AM UTC 24
Peak memory 219180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=2600359492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2600359492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.180891900
Short name T903
Test name
Test status
Simulation time 48831175 ps
CPU time 1.7 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:14 AM UTC 24
Peak memory 228372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=180891900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.180891900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1897920947
Short name T915
Test name
Test status
Simulation time 52311923 ps
CPU time 2.76 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:17 AM UTC 24
Peak memory 219320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18979
20947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
lc_ctrl_same_csr_outstanding.1897920947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1383005642
Short name T144
Test name
Test status
Simulation time 239549249 ps
CPU time 4 seconds
Started Aug 27 07:00:11 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 229488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383005642 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1383005642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2087482388
Short name T912
Test name
Test status
Simulation time 170345079 ps
CPU time 2.06 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 235784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087482388 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_t
l_intg_err.2087482388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2563383905
Short name T924
Test name
Test status
Simulation time 31692623 ps
CPU time 2.23 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2563383905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2563383905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2283748775
Short name T917
Test name
Test status
Simulation time 13768811 ps
CPU time 1.24 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:18 AM UTC 24
Peak memory 218068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283748775 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2283748775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3810047453
Short name T916
Test name
Test status
Simulation time 47900316 ps
CPU time 1.61 seconds
Started Aug 27 07:00:15 AM UTC 24
Finished Aug 27 07:00:17 AM UTC 24
Peak memory 215516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=3810047453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3810047453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.435231204
Short name T933
Test name
Test status
Simulation time 514855136 ps
CPU time 7.39 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 219404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=435231204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.435231204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2824145844
Short name T1004
Test name
Test status
Simulation time 20198551712 ps
CPU time 31.89 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:46 AM UTC 24
Peak memory 219320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2824145844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2824145844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3074983648
Short name T910
Test name
Test status
Simulation time 62176858 ps
CPU time 1.66 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 220116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3074983648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3074983648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.647415809
Short name T921
Test name
Test status
Simulation time 1303645708 ps
CPU time 3.37 seconds
Started Aug 27 07:00:14 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 231676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647415809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.647415809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1679786114
Short name T918
Test name
Test status
Simulation time 89861458 ps
CPU time 3.27 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:17 AM UTC 24
Peak memory 219100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1679786114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_csr_rw.1679786114
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3226778808
Short name T908
Test name
Test status
Simulation time 149713576 ps
CPU time 1.31 seconds
Started Aug 27 07:00:13 AM UTC 24
Finished Aug 27 07:00:16 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3226778808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3226778808
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1263443414
Short name T919
Test name
Test status
Simulation time 16101701 ps
CPU time 1.19 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:18 AM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12634
43414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
lc_ctrl_same_csr_outstanding.1263443414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.353741385
Short name T145
Test name
Test status
Simulation time 244952905 ps
CPU time 2.29 seconds
Started Aug 27 07:00:15 AM UTC 24
Finished Aug 27 07:00:18 AM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=353741385 -assert nopostpr
oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.353741385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2104890740
Short name T148
Test name
Test status
Simulation time 59242020 ps
CPU time 2.95 seconds
Started Aug 27 07:00:15 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 229896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104890740 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_t
l_intg_err.2104890740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2957469099
Short name T930
Test name
Test status
Simulation time 59261787 ps
CPU time 1.88 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:21 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2957469099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2957469099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1014870750
Short name T928
Test name
Test status
Simulation time 11836252 ps
CPU time 1.14 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:20 AM UTC 24
Peak memory 218076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014870750 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1014870750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3644111855
Short name T920
Test name
Test status
Simulation time 68704221 ps
CPU time 1.2 seconds
Started Aug 27 07:00:17 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=3644111855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3644111855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1381523525
Short name T974
Test name
Test status
Simulation time 2399861198 ps
CPU time 13.96 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1381523525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1381523525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3050800507
Short name T935
Test name
Test status
Simulation time 708793662 ps
CPU time 4.77 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 219088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3050800507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3050800507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1974992063
Short name T923
Test name
Test status
Simulation time 331878374 ps
CPU time 2 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 220116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1974992063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1974992063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3040565158
Short name T926
Test name
Test status
Simulation time 88143709 ps
CPU time 2.03 seconds
Started Aug 27 07:00:17 AM UTC 24
Finished Aug 27 07:00:20 AM UTC 24
Peak memory 235700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040565158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3040565158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3494605611
Short name T922
Test name
Test status
Simulation time 152238933 ps
CPU time 1.89 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 218600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=3494605611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_csr_rw.3494605611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4191476309
Short name T925
Test name
Test status
Simulation time 169213894 ps
CPU time 1.95 seconds
Started Aug 27 07:00:16 AM UTC 24
Finished Aug 27 07:00:20 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=4191476309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4191476309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.263763591
Short name T927
Test name
Test status
Simulation time 75931559 ps
CPU time 1.08 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:20 AM UTC 24
Peak memory 218072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26376
3591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_same_csr_outstanding.263763591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2594324056
Short name T932
Test name
Test status
Simulation time 267117838 ps
CPU time 2.38 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:21 AM UTC 24
Peak memory 231540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594324056 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2594324056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1778233311
Short name T940
Test name
Test status
Simulation time 78179190 ps
CPU time 1.51 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=1778233311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1778233311
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1787890287
Short name T937
Test name
Test status
Simulation time 52275909 ps
CPU time 1.22 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 218136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787890287 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1787890287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.4271153781
Short name T942
Test name
Test status
Simulation time 457344163 ps
CPU time 2.4 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=4271153781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.4271153781
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1434909806
Short name T1003
Test name
Test status
Simulation time 4760062034 ps
CPU time 23.58 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:45 AM UTC 24
Peak memory 219320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1434909806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.1434909806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3211908664
Short name T967
Test name
Test status
Simulation time 3339017757 ps
CPU time 9.58 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 219540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3211908664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3211908664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2418054991
Short name T936
Test name
Test status
Simulation time 456676363 ps
CPU time 2.85 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 221596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2418054991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2418054991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2158892896
Short name T146
Test name
Test status
Simulation time 118225255 ps
CPU time 1.88 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 228316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158892896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2158892896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1038999224
Short name T929
Test name
Test status
Simulation time 292903994 ps
CPU time 1.73 seconds
Started Aug 27 07:00:18 AM UTC 24
Finished Aug 27 07:00:21 AM UTC 24
Peak memory 218488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1038999224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_csr_rw.1038999224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1760868097
Short name T939
Test name
Test status
Simulation time 62711141 ps
CPU time 1.54 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=1760868097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1760868097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3788036606
Short name T938
Test name
Test status
Simulation time 70010300 ps
CPU time 1.21 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 218664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37880
36606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
lc_ctrl_same_csr_outstanding.3788036606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3598478204
Short name T943
Test name
Test status
Simulation time 28417492 ps
CPU time 2.73 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:24 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598478204 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3598478204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.964290183
Short name T949
Test name
Test status
Simulation time 369718281 ps
CPU time 1.81 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=964290183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.964290183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2750690560
Short name T241
Test name
Test status
Simulation time 22691300 ps
CPU time 1.26 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:26 AM UTC 24
Peak memory 218076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750690560 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2750690560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1011583812
Short name T944
Test name
Test status
Simulation time 147333701 ps
CPU time 1.24 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:24 AM UTC 24
Peak memory 218592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=1011583812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.1011583812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3519378394
Short name T965
Test name
Test status
Simulation time 1159133856 ps
CPU time 5.98 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 218484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3519378394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3519378394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3039557289
Short name T983
Test name
Test status
Simulation time 3737189935 ps
CPU time 10.57 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:33 AM UTC 24
Peak memory 219576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=3039557289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3039557289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1512820637
Short name T941
Test name
Test status
Simulation time 102137570 ps
CPU time 1.83 seconds
Started Aug 27 07:00:20 AM UTC 24
Finished Aug 27 07:00:23 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=1512820637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1512820637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.521043751
Short name T961
Test name
Test status
Simulation time 2702379963 ps
CPU time 5.71 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 229620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521043751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_di
sabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.521043751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.97492483
Short name T946
Test name
Test status
Simulation time 78499278 ps
CPU time 1.51 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:24 AM UTC 24
Peak memory 218492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=97492483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_rw.97492483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3376269796
Short name T945
Test name
Test status
Simulation time 52709878 ps
CPU time 1.45 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:24 AM UTC 24
Peak memory 230776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=3376269796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3376269796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1697332901
Short name T947
Test name
Test status
Simulation time 111217982 ps
CPU time 1.38 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:26 AM UTC 24
Peak memory 220180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16973
32901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
lc_ctrl_same_csr_outstanding.1697332901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3819742600
Short name T951
Test name
Test status
Simulation time 243541133 ps
CPU time 4.18 seconds
Started Aug 27 07:00:22 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 231612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819742600 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3819742600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.243274441
Short name T147
Test name
Test status
Simulation time 65724094 ps
CPU time 2.79 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 229564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243274441 -ass
ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl
_intg_err.243274441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2584356910
Short name T959
Test name
Test status
Simulation time 66084987 ps
CPU time 1.5 seconds
Started Aug 27 07:00:26 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 230360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2584356910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2584356910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3587383061
Short name T242
Test name
Test status
Simulation time 11636500 ps
CPU time 1.17 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 218156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587383061 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3587383061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.268627394
Short name T948
Test name
Test status
Simulation time 41567657 ps
CPU time 1.41 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 218664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c
reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim
.tcl +ntb_random_seed=268627394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.268627394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.4071958060
Short name T978
Test name
Test status
Simulation time 226505656 ps
CPU time 6.56 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 218080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=4071958060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.4071958060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.343690820
Short name T1002
Test name
Test status
Simulation time 829052723 ps
CPU time 17.4 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:43 AM UTC 24
Peak memory 218796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=343690820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.343690820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2074884512
Short name T956
Test name
Test status
Simulation time 209739581 ps
CPU time 2.71 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 221224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r
iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t
cl +ntb_random_seed=2074884512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2074884512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3315610685
Short name T963
Test name
Test status
Simulation time 353566599 ps
CPU time 3.42 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:29 AM UTC 24
Peak memory 235780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti
meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque
ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3315610685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_d
isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3315610685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1806249425
Short name T953
Test name
Test status
Simulation time 204116844 ps
CPU time 2.25 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 219508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m
ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt
b_random_seed=1806249425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_csr_rw.1806249425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2308237600
Short name T952
Test name
Test status
Simulation time 290091849 ps
CPU time 1.86 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 218132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c
reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv
/tools/sim.tcl +ntb_random_seed=2308237600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_
top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2308237600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.616802648
Short name T950
Test name
Test status
Simulation time 24446463 ps
CPU time 1.6 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 218548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61680
2648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.l
c_ctrl_same_csr_outstanding.616802648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2295611847
Short name T957
Test name
Test status
Simulation time 131959765 ps
CPU time 2.75 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 231536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295611847 -assert nopostp
roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2295611847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1850281194
Short name T149
Test name
Test status
Simulation time 201998942 ps
CPU time 2.46 seconds
Started Aug 27 07:00:24 AM UTC 24
Finished Aug 27 07:00:28 AM UTC 24
Peak memory 223496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850281194 -as
sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_t
l_intg_err.1850281194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.2270435066
Short name T31
Test name
Test status
Simulation time 29524144 ps
CPU time 1.3 seconds
Started Aug 27 06:53:56 AM UTC 24
Finished Aug 27 06:53:58 AM UTC 24
Peak memory 217368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270435066 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2270435066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4041536546
Short name T100
Test name
Test status
Simulation time 21676066293 ps
CPU time 36.53 seconds
Started Aug 27 06:53:50 AM UTC 24
Finished Aug 27 06:54:28 AM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041536546
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_errors.4041536546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.513295930
Short name T8
Test name
Test status
Simulation time 163585225 ps
CPU time 6.75 seconds
Started Aug 27 06:53:50 AM UTC 24
Finished Aug 27 06:53:58 AM UTC 24
Peak memory 230176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513295930 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_prio
rity.513295930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2346895748
Short name T29
Test name
Test status
Simulation time 1335596895 ps
CPU time 24.37 seconds
Started Aug 27 06:53:50 AM UTC 24
Finished Aug 27 06:54:16 AM UTC 24
Peak memory 230064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346895748
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l
c_ctrl_jtag_regwen_during_op.2346895748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.2257434002
Short name T6
Test name
Test status
Simulation time 230106660 ps
CPU time 4.67 seconds
Started Aug 27 06:53:48 AM UTC 24
Finished Aug 27 06:53:53 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257434002
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_smoke.2257434002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.3293428609
Short name T23
Test name
Test status
Simulation time 1699381872 ps
CPU time 18.33 seconds
Started Aug 27 06:53:52 AM UTC 24
Finished Aug 27 06:54:11 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293428609 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_t
oken_digest.3293428609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.3456699653
Short name T3
Test name
Test status
Simulation time 91912917 ps
CPU time 4.01 seconds
Started Aug 27 06:53:45 AM UTC 24
Finished Aug 27 06:53:50 AM UTC 24
Peak memory 225832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456699653 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3456699653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.4199619338
Short name T48
Test name
Test status
Simulation time 754991143 ps
CPU time 28.04 seconds
Started Aug 27 06:53:45 AM UTC 24
Finished Aug 27 06:54:14 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4199619338 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.4199619338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.2111638260
Short name T5
Test name
Test status
Simulation time 78643788 ps
CPU time 3.85 seconds
Started Aug 27 06:53:46 AM UTC 24
Finished Aug 27 06:53:51 AM UTC 24
Peak memory 234596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111638260 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2111638260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.4118904252
Short name T60
Test name
Test status
Simulation time 6584437980 ps
CPU time 188.09 seconds
Started Aug 27 06:53:52 AM UTC 24
Finished Aug 27 06:57:03 AM UTC 24
Peak memory 262804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4118904252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 0.lc_ctrl_stress_all.4118904252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.1535729118
Short name T21
Test name
Test status
Simulation time 1331720920 ps
CPU time 10.16 seconds
Started Aug 27 06:53:59 AM UTC 24
Finished Aug 27 06:54:10 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535729118 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1535729118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.1431386846
Short name T9
Test name
Test status
Simulation time 107405386 ps
CPU time 2.92 seconds
Started Aug 27 06:54:02 AM UTC 24
Finished Aug 27 06:54:05 AM UTC 24
Peak memory 229748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431386846 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1431386846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.4287627390
Short name T101
Test name
Test status
Simulation time 12599602791 ps
CPU time 47.35 seconds
Started Aug 27 06:54:02 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287627390
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_errors.4287627390
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.3620101552
Short name T28
Test name
Test status
Simulation time 530772746 ps
CPU time 10.29 seconds
Started Aug 27 06:54:02 AM UTC 24
Finished Aug 27 06:54:13 AM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620101552 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_pri
ority.3620101552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.489868539
Short name T229
Test name
Test status
Simulation time 5526091873 ps
CPU time 16.69 seconds
Started Aug 27 06:54:01 AM UTC 24
Finished Aug 27 06:54:19 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489868539
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_jtag_prog_failure.489868539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1206505968
Short name T24
Test name
Test status
Simulation time 4191136651 ps
CPU time 21.24 seconds
Started Aug 27 06:54:03 AM UTC 24
Finished Aug 27 06:54:25 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206505968
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.l
c_ctrl_jtag_regwen_during_op.1206505968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1982781143
Short name T20
Test name
Test status
Simulation time 133905042 ps
CPU time 6.41 seconds
Started Aug 27 06:54:00 AM UTC 24
Finished Aug 27 06:54:07 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982781143
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_smoke.1982781143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.485292479
Short name T267
Test name
Test status
Simulation time 1498413517 ps
CPU time 29.45 seconds
Started Aug 27 06:54:00 AM UTC 24
Finished Aug 27 06:54:31 AM UTC 24
Peak memory 262692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485292479
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_jtag_state_failure.485292479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.142469894
Short name T43
Test name
Test status
Simulation time 11326266950 ps
CPU time 23 seconds
Started Aug 27 06:54:01 AM UTC 24
Finished Aug 27 06:54:26 AM UTC 24
Peak memory 272976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142469894
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc
_ctrl_jtag_state_post_trans.142469894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.3169224237
Short name T27
Test name
Test status
Simulation time 129889164 ps
CPU time 3.03 seconds
Started Aug 27 06:53:58 AM UTC 24
Finished Aug 27 06:54:02 AM UTC 24
Peak memory 236544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169224237 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3169224237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.525681009
Short name T49
Test name
Test status
Simulation time 254832287 ps
CPU time 7.07 seconds
Started Aug 27 06:54:00 AM UTC 24
Finished Aug 27 06:54:08 AM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525681009 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.525681009
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.417153363
Short name T71
Test name
Test status
Simulation time 413931800 ps
CPU time 36.76 seconds
Started Aug 27 06:54:05 AM UTC 24
Finished Aug 27 06:54:43 AM UTC 24
Peak memory 291876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417153363 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.417153363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.2442797929
Short name T120
Test name
Test status
Simulation time 427646788 ps
CPU time 10.48 seconds
Started Aug 27 06:54:03 AM UTC 24
Finished Aug 27 06:54:14 AM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442797929 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_t
oken_digest.2442797929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.1467027715
Short name T50
Test name
Test status
Simulation time 368152693 ps
CPU time 7.6 seconds
Started Aug 27 06:54:03 AM UTC 24
Finished Aug 27 06:54:12 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467027715 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke
n_mux.1467027715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.1622306973
Short name T32
Test name
Test status
Simulation time 93462593 ps
CPU time 1.72 seconds
Started Aug 27 06:53:56 AM UTC 24
Finished Aug 27 06:53:59 AM UTC 24
Peak memory 229104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622306973 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1622306973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.2848573747
Short name T106
Test name
Test status
Simulation time 899234702 ps
CPU time 29.3 seconds
Started Aug 27 06:53:57 AM UTC 24
Finished Aug 27 06:54:28 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848573747 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2848573747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.319343631
Short name T122
Test name
Test status
Simulation time 52554587461 ps
CPU time 388.96 seconds
Started Aug 27 06:54:04 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 297736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=319343631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 1.lc_ctrl_stress_all.319343631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1800475698
Short name T105
Test name
Test status
Simulation time 5904063792 ps
CPU time 65.89 seconds
Started Aug 27 06:54:04 AM UTC 24
Finished Aug 27 06:55:12 AM UTC 24
Peak memory 281368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800475698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1800475698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1695841705
Short name T16
Test name
Test status
Simulation time 13854923 ps
CPU time 1.29 seconds
Started Aug 27 06:53:57 AM UTC 24
Finished Aug 27 06:54:00 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695841705 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_volatile_unlock_smoke.1695841705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.2481161147
Short name T366
Test name
Test status
Simulation time 113651240 ps
CPU time 1.32 seconds
Started Aug 27 06:55:31 AM UTC 24
Finished Aug 27 06:55:33 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481161147 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2481161147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.2237122617
Short name T51
Test name
Test status
Simulation time 411582265 ps
CPU time 8.83 seconds
Started Aug 27 06:55:26 AM UTC 24
Finished Aug 27 06:55:36 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237122617 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2237122617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.3751824472
Short name T38
Test name
Test status
Simulation time 1557311989 ps
CPU time 6.15 seconds
Started Aug 27 06:55:28 AM UTC 24
Finished Aug 27 06:55:35 AM UTC 24
Peak memory 229868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751824472 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_acce
ss.3751824472
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.1547160588
Short name T59
Test name
Test status
Simulation time 8052812452 ps
CPU time 36.01 seconds
Started Aug 27 06:55:28 AM UTC 24
Finished Aug 27 06:56:05 AM UTC 24
Peak memory 237972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547160588
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_errors.1547160588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.2904194530
Short name T389
Test name
Test status
Simulation time 690040452 ps
CPU time 16.45 seconds
Started Aug 27 06:55:27 AM UTC 24
Finished Aug 27 06:55:45 AM UTC 24
Peak memory 236284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904194530
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_jtag_prog_failure.2904194530
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.3864966729
Short name T369
Test name
Test status
Simulation time 374640232 ps
CPU time 5.58 seconds
Started Aug 27 06:55:27 AM UTC 24
Finished Aug 27 06:55:34 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3864966729
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_smoke.3864966729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.869221370
Short name T518
Test name
Test status
Simulation time 13995332863 ps
CPU time 94.89 seconds
Started Aug 27 06:55:27 AM UTC 24
Finished Aug 27 06:57:05 AM UTC 24
Peak memory 291404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869221370
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_jtag_state_failure.869221370
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.1102482330
Short name T177
Test name
Test status
Simulation time 2789244159 ps
CPU time 28.04 seconds
Started Aug 27 06:55:27 AM UTC 24
Finished Aug 27 06:55:57 AM UTC 24
Peak memory 260672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102482330
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.
lc_ctrl_jtag_state_post_trans.1102482330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.1869028168
Short name T365
Test name
Test status
Simulation time 102694695 ps
CPU time 4.93 seconds
Started Aug 27 06:55:26 AM UTC 24
Finished Aug 27 06:55:32 AM UTC 24
Peak memory 232128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1869028168 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1869028168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.883725756
Short name T384
Test name
Test status
Simulation time 318439992 ps
CPU time 12.31 seconds
Started Aug 27 06:55:29 AM UTC 24
Finished Aug 27 06:55:43 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883725756 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.883725756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3211262509
Short name T381
Test name
Test status
Simulation time 1246780077 ps
CPU time 10.26 seconds
Started Aug 27 06:55:29 AM UTC 24
Finished Aug 27 06:55:41 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211262509 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_
token_digest.3211262509
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.2200022344
Short name T378
Test name
Test status
Simulation time 248545718 ps
CPU time 9.22 seconds
Started Aug 27 06:55:29 AM UTC 24
Finished Aug 27 06:55:40 AM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200022344 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_tok
en_mux.2200022344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1271075246
Short name T265
Test name
Test status
Simulation time 1517141169 ps
CPU time 10.13 seconds
Started Aug 27 06:55:27 AM UTC 24
Finished Aug 27 06:55:39 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271075246 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1271075246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2774895795
Short name T356
Test name
Test status
Simulation time 28790892 ps
CPU time 1.62 seconds
Started Aug 27 06:55:24 AM UTC 24
Finished Aug 27 06:55:27 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774895795 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2774895795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.495424096
Short name T402
Test name
Test status
Simulation time 249257897 ps
CPU time 32.72 seconds
Started Aug 27 06:55:26 AM UTC 24
Finished Aug 27 06:56:00 AM UTC 24
Peak memory 262696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495424096 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.495424096
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1944359415
Short name T371
Test name
Test status
Simulation time 86177760 ps
CPU time 7.97 seconds
Started Aug 27 06:55:26 AM UTC 24
Finished Aug 27 06:55:35 AM UTC 24
Peak memory 260880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944359415 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1944359415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.4248442479
Short name T569
Test name
Test status
Simulation time 4025267049 ps
CPU time 115.88 seconds
Started Aug 27 06:55:29 AM UTC 24
Finished Aug 27 06:57:27 AM UTC 24
Peak memory 285588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4248442479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 10.lc_ctrl_stress_all.4248442479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2896723698
Short name T354
Test name
Test status
Simulation time 13755124 ps
CPU time 1.47 seconds
Started Aug 27 06:55:24 AM UTC 24
Finished Aug 27 06:55:27 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896723698 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_volatile_unlock_smoke.2896723698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.3488037210
Short name T379
Test name
Test status
Simulation time 93326254 ps
CPU time 1.36 seconds
Started Aug 27 06:55:38 AM UTC 24
Finished Aug 27 06:55:40 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488037210 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3488037210
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.449691391
Short name T390
Test name
Test status
Simulation time 263170104 ps
CPU time 11.7 seconds
Started Aug 27 06:55:33 AM UTC 24
Finished Aug 27 06:55:45 AM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449691391 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.449691391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4292376738
Short name T39
Test name
Test status
Simulation time 2219821035 ps
CPU time 9.25 seconds
Started Aug 27 06:55:35 AM UTC 24
Finished Aug 27 06:55:45 AM UTC 24
Peak memory 229984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292376738 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_acce
ss.4292376738
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.3445193145
Short name T422
Test name
Test status
Simulation time 7142414562 ps
CPU time 30.26 seconds
Started Aug 27 06:55:35 AM UTC 24
Finished Aug 27 06:56:07 AM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445193145
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_errors.3445193145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.3949800401
Short name T377
Test name
Test status
Simulation time 415832139 ps
CPU time 2.65 seconds
Started Aug 27 06:55:35 AM UTC 24
Finished Aug 27 06:55:39 AM UTC 24
Peak memory 232132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949800401
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_jtag_prog_failure.3949800401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.697631204
Short name T383
Test name
Test status
Simulation time 226001693 ps
CPU time 8.33 seconds
Started Aug 27 06:55:33 AM UTC 24
Finished Aug 27 06:55:42 AM UTC 24
Peak memory 229788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697631204
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_smoke.697631204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2225446676
Short name T421
Test name
Test status
Simulation time 4787893216 ps
CPU time 31.32 seconds
Started Aug 27 06:55:34 AM UTC 24
Finished Aug 27 06:56:06 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225446676
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_
ctrl_jtag_state_failure.2225446676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.424807102
Short name T175
Test name
Test status
Simulation time 2951598370 ps
CPU time 20.61 seconds
Started Aug 27 06:55:34 AM UTC 24
Finished Aug 27 06:55:56 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424807102
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.l
c_ctrl_jtag_state_post_trans.424807102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.1595776464
Short name T374
Test name
Test status
Simulation time 100941700 ps
CPU time 3.3 seconds
Started Aug 27 06:55:33 AM UTC 24
Finished Aug 27 06:55:37 AM UTC 24
Peak memory 236356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595776464 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1595776464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.819030097
Short name T172
Test name
Test status
Simulation time 1947585162 ps
CPU time 16.72 seconds
Started Aug 27 06:55:36 AM UTC 24
Finished Aug 27 06:55:54 AM UTC 24
Peak memory 238156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819030097 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.819030097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3823957570
Short name T393
Test name
Test status
Simulation time 842366074 ps
CPU time 11.35 seconds
Started Aug 27 06:55:36 AM UTC 24
Finished Aug 27 06:55:49 AM UTC 24
Peak memory 237664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823957570 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_
token_digest.3823957570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.2141694866
Short name T392
Test name
Test status
Simulation time 1518094670 ps
CPU time 8.65 seconds
Started Aug 27 06:55:36 AM UTC 24
Finished Aug 27 06:55:46 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141694866 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok
en_mux.2141694866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.701628676
Short name T388
Test name
Test status
Simulation time 441821136 ps
CPU time 11.12 seconds
Started Aug 27 06:55:33 AM UTC 24
Finished Aug 27 06:55:45 AM UTC 24
Peak memory 237912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=701628676 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.701628676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3239960389
Short name T370
Test name
Test status
Simulation time 23058152 ps
CPU time 2.3 seconds
Started Aug 27 06:55:31 AM UTC 24
Finished Aug 27 06:55:34 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3239960389 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3239960389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.388741322
Short name T173
Test name
Test status
Simulation time 1412440126 ps
CPU time 21.96 seconds
Started Aug 27 06:55:31 AM UTC 24
Finished Aug 27 06:55:54 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388741322 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.388741322
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2479439752
Short name T385
Test name
Test status
Simulation time 102589495 ps
CPU time 11.14 seconds
Started Aug 27 06:55:31 AM UTC 24
Finished Aug 27 06:55:43 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479439752 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2479439752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.4175427278
Short name T448
Test name
Test status
Simulation time 2150526096 ps
CPU time 49.98 seconds
Started Aug 27 06:55:36 AM UTC 24
Finished Aug 27 06:56:28 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4175427278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 11.lc_ctrl_stress_all.4175427278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3805345954
Short name T367
Test name
Test status
Simulation time 35025634 ps
CPU time 1.27 seconds
Started Aug 27 06:55:31 AM UTC 24
Finished Aug 27 06:55:33 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3805345954 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_volatile_unlock_smoke.3805345954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2079739907
Short name T395
Test name
Test status
Simulation time 16829326 ps
CPU time 1.36 seconds
Started Aug 27 06:55:48 AM UTC 24
Finished Aug 27 06:55:51 AM UTC 24
Peak memory 218992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2079739907 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2079739907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.2674339276
Short name T391
Test name
Test status
Simulation time 216532027 ps
CPU time 10.53 seconds
Started Aug 27 06:55:42 AM UTC 24
Finished Aug 27 06:55:53 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674339276 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2674339276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2780894750
Short name T398
Test name
Test status
Simulation time 378211166 ps
CPU time 6.63 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:55:53 AM UTC 24
Peak memory 229640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780894750 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_acce
ss.2780894750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.2368607027
Short name T440
Test name
Test status
Simulation time 1359750941 ps
CPU time 38.46 seconds
Started Aug 27 06:55:44 AM UTC 24
Finished Aug 27 06:56:24 AM UTC 24
Peak memory 237916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2368607027
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_errors.2368607027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2061090357
Short name T401
Test name
Test status
Simulation time 1471609439 ps
CPU time 14.21 seconds
Started Aug 27 06:55:44 AM UTC 24
Finished Aug 27 06:56:00 AM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061090357
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_jtag_prog_failure.2061090357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.3962052476
Short name T90
Test name
Test status
Simulation time 421218659 ps
CPU time 14.35 seconds
Started Aug 27 06:55:42 AM UTC 24
Finished Aug 27 06:55:57 AM UTC 24
Peak memory 229784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962052476
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_smoke.3962052476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.1728149824
Short name T478
Test name
Test status
Simulation time 27926605354 ps
CPU time 58.77 seconds
Started Aug 27 06:55:42 AM UTC 24
Finished Aug 27 06:56:42 AM UTC 24
Peak memory 287404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728149824
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_
ctrl_jtag_state_failure.1728149824
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.631656525
Short name T403
Test name
Test status
Simulation time 424242661 ps
CPU time 14.61 seconds
Started Aug 27 06:55:44 AM UTC 24
Finished Aug 27 06:56:00 AM UTC 24
Peak memory 262852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631656525
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.l
c_ctrl_jtag_state_post_trans.631656525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.253166111
Short name T387
Test name
Test status
Simulation time 262174003 ps
CPU time 3.27 seconds
Started Aug 27 06:55:40 AM UTC 24
Finished Aug 27 06:55:45 AM UTC 24
Peak memory 236532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253166111 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.253166111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2471657669
Short name T56
Test name
Test status
Simulation time 181122571 ps
CPU time 8.52 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:55:55 AM UTC 24
Peak memory 237768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471657669 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2471657669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3197140778
Short name T412
Test name
Test status
Simulation time 1281307893 ps
CPU time 16.72 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:56:04 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197140778 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_
token_digest.3197140778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.57447386
Short name T406
Test name
Test status
Simulation time 2672297745 ps
CPU time 13.52 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:56:01 AM UTC 24
Peak memory 238180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=57447386 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token
_mux.57447386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3581694737
Short name T420
Test name
Test status
Simulation time 342569273 ps
CPU time 24.65 seconds
Started Aug 27 06:55:40 AM UTC 24
Finished Aug 27 06:56:06 AM UTC 24
Peak memory 262952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581694737 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3581694737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.425940856
Short name T394
Test name
Test status
Simulation time 50223802 ps
CPU time 9.29 seconds
Started Aug 27 06:55:40 AM UTC 24
Finished Aug 27 06:55:51 AM UTC 24
Peak memory 258648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425940856 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.425940856
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.2802563899
Short name T474
Test name
Test status
Simulation time 8049017873 ps
CPU time 53.21 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:56:41 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2802563899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 12.lc_ctrl_stress_all.2802563899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.990304277
Short name T163
Test name
Test status
Simulation time 2799679733 ps
CPU time 23.08 seconds
Started Aug 27 06:55:46 AM UTC 24
Finished Aug 27 06:56:10 AM UTC 24
Peak memory 238352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990304277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.990304277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.404673196
Short name T382
Test name
Test status
Simulation time 58623058 ps
CPU time 1.19 seconds
Started Aug 27 06:55:39 AM UTC 24
Finished Aug 27 06:55:41 AM UTC 24
Peak memory 229036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404673196 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.lc_ctrl_volatile_unlock_smoke.404673196
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2783243622
Short name T400
Test name
Test status
Simulation time 110766354 ps
CPU time 1.68 seconds
Started Aug 27 06:55:57 AM UTC 24
Finished Aug 27 06:55:59 AM UTC 24
Peak memory 218756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783243622 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2783243622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1231035385
Short name T419
Test name
Test status
Simulation time 2527145802 ps
CPU time 11.89 seconds
Started Aug 27 06:55:53 AM UTC 24
Finished Aug 27 06:56:06 AM UTC 24
Peak memory 232320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231035385 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1231035385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.1595202308
Short name T424
Test name
Test status
Simulation time 446302551 ps
CPU time 11.47 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:08 AM UTC 24
Peak memory 230076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595202308 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_acce
ss.1595202308
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.2439833395
Short name T459
Test name
Test status
Simulation time 9867403535 ps
CPU time 38.38 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:35 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439833395
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_errors.2439833395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.73404877
Short name T407
Test name
Test status
Simulation time 152125819 ps
CPU time 4.7 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:01 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73404877 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_jtag_prog_failure.73404877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.1017245109
Short name T418
Test name
Test status
Simulation time 823569357 ps
CPU time 9.9 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:06 AM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017245109
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_smoke.1017245109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.786644557
Short name T506
Test name
Test status
Simulation time 3468990970 ps
CPU time 59.6 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:56 AM UTC 24
Peak memory 285412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786644557
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_jtag_state_failure.786644557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1639371938
Short name T208
Test name
Test status
Simulation time 665827280 ps
CPU time 15.41 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:12 AM UTC 24
Peak memory 262620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639371938
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.
lc_ctrl_jtag_state_post_trans.1639371938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.3755142475
Short name T176
Test name
Test status
Simulation time 73446350 ps
CPU time 2.56 seconds
Started Aug 27 06:55:53 AM UTC 24
Finished Aug 27 06:55:57 AM UTC 24
Peak memory 236548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755142475 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3755142475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.549085661
Short name T410
Test name
Test status
Simulation time 653207274 ps
CPU time 6.87 seconds
Started Aug 27 06:55:55 AM UTC 24
Finished Aug 27 06:56:03 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549085661 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.549085661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.2042440687
Short name T423
Test name
Test status
Simulation time 431073068 ps
CPU time 9.2 seconds
Started Aug 27 06:55:57 AM UTC 24
Finished Aug 27 06:56:07 AM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042440687 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_
token_digest.2042440687
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.2834408522
Short name T206
Test name
Test status
Simulation time 299738863 ps
CPU time 12.09 seconds
Started Aug 27 06:55:57 AM UTC 24
Finished Aug 27 06:56:10 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834408522 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_tok
en_mux.2834408522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.343321348
Short name T408
Test name
Test status
Simulation time 605879904 ps
CPU time 8.1 seconds
Started Aug 27 06:55:53 AM UTC 24
Finished Aug 27 06:56:02 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343321348 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.343321348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.2120878073
Short name T76
Test name
Test status
Simulation time 39404020 ps
CPU time 3.6 seconds
Started Aug 27 06:55:48 AM UTC 24
Finished Aug 27 06:55:53 AM UTC 24
Peak memory 225840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120878073 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2120878073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.3092853610
Short name T207
Test name
Test status
Simulation time 515382887 ps
CPU time 20.68 seconds
Started Aug 27 06:55:49 AM UTC 24
Finished Aug 27 06:56:10 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092853610 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3092853610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3999749576
Short name T409
Test name
Test status
Simulation time 719726307 ps
CPU time 10.4 seconds
Started Aug 27 06:55:51 AM UTC 24
Finished Aug 27 06:56:02 AM UTC 24
Peak memory 262664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999749576 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3999749576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1837522423
Short name T552
Test name
Test status
Simulation time 12925907050 ps
CPU time 81.77 seconds
Started Aug 27 06:55:57 AM UTC 24
Finished Aug 27 06:57:20 AM UTC 24
Peak memory 262800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1837522423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 13.lc_ctrl_stress_all.1837522423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.3074872278
Short name T165
Test name
Test status
Simulation time 2684254269 ps
CPU time 81.72 seconds
Started Aug 27 06:55:57 AM UTC 24
Finished Aug 27 06:57:20 AM UTC 24
Peak memory 278864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074872278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.3074872278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1740541204
Short name T396
Test name
Test status
Simulation time 46995571 ps
CPU time 1.43 seconds
Started Aug 27 06:55:49 AM UTC 24
Finished Aug 27 06:55:51 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740541204 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_volatile_unlock_smoke.1740541204
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.883278130
Short name T425
Test name
Test status
Simulation time 39649300 ps
CPU time 1.19 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:09 AM UTC 24
Peak memory 217428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883278130 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.883278130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.580196965
Short name T52
Test name
Test status
Simulation time 686200347 ps
CPU time 16 seconds
Started Aug 27 06:56:00 AM UTC 24
Finished Aug 27 06:56:17 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580196965 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.580196965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.3371827434
Short name T204
Test name
Test status
Simulation time 993430029 ps
CPU time 6.25 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:09 AM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371827434 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_acce
ss.3371827434
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.4182218049
Short name T471
Test name
Test status
Simulation time 3955859275 ps
CPU time 35.72 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182218049
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_errors.4182218049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.2149618153
Short name T417
Test name
Test status
Simulation time 203765642 ps
CPU time 2.25 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:05 AM UTC 24
Peak memory 232396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149618153
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_jtag_prog_failure.2149618153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.2663177400
Short name T416
Test name
Test status
Simulation time 349580845 ps
CPU time 2.2 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:05 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663177400
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_smoke.2663177400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.2835055795
Short name T501
Test name
Test status
Simulation time 1919316325 ps
CPU time 50.98 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:54 AM UTC 24
Peak memory 287252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835055795
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_
ctrl_jtag_state_failure.2835055795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3852973694
Short name T434
Test name
Test status
Simulation time 1725025582 ps
CPU time 16.55 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:20 AM UTC 24
Peak memory 262684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852973694
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.
lc_ctrl_jtag_state_post_trans.3852973694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.3013213288
Short name T415
Test name
Test status
Simulation time 451338646 ps
CPU time 3.19 seconds
Started Aug 27 06:56:00 AM UTC 24
Finished Aug 27 06:56:04 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013213288 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3013213288
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2531814099
Short name T445
Test name
Test status
Simulation time 1712532132 ps
CPU time 21.67 seconds
Started Aug 27 06:56:03 AM UTC 24
Finished Aug 27 06:56:26 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531814099 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2531814099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.4055015329
Short name T437
Test name
Test status
Simulation time 414529236 ps
CPU time 16.33 seconds
Started Aug 27 06:56:05 AM UTC 24
Finished Aug 27 06:56:22 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055015329 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_
token_digest.4055015329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.4145326954
Short name T428
Test name
Test status
Simulation time 332835512 ps
CPU time 11.14 seconds
Started Aug 27 06:56:03 AM UTC 24
Finished Aug 27 06:56:15 AM UTC 24
Peak memory 230212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145326954 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_tok
en_mux.4145326954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.3385484560
Short name T433
Test name
Test status
Simulation time 2160238060 ps
CPU time 16.47 seconds
Started Aug 27 06:56:02 AM UTC 24
Finished Aug 27 06:56:19 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385484560 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3385484560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.3306857384
Short name T78
Test name
Test status
Simulation time 94896558 ps
CPU time 2.44 seconds
Started Aug 27 06:55:58 AM UTC 24
Finished Aug 27 06:56:01 AM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306857384 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3306857384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.1257826888
Short name T449
Test name
Test status
Simulation time 477358712 ps
CPU time 29.21 seconds
Started Aug 27 06:55:58 AM UTC 24
Finished Aug 27 06:56:28 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257826888 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1257826888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2505639055
Short name T414
Test name
Test status
Simulation time 287145597 ps
CPU time 4.22 seconds
Started Aug 27 06:55:59 AM UTC 24
Finished Aug 27 06:56:04 AM UTC 24
Peak memory 236812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505639055 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2505639055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.4156590045
Short name T520
Test name
Test status
Simulation time 4982519049 ps
CPU time 58.87 seconds
Started Aug 27 06:56:05 AM UTC 24
Finished Aug 27 06:57:05 AM UTC 24
Peak memory 289364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4156590045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 14.lc_ctrl_stress_all.4156590045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3336100105
Short name T254
Test name
Test status
Simulation time 4055394920 ps
CPU time 78.51 seconds
Started Aug 27 06:56:05 AM UTC 24
Finished Aug 27 06:57:25 AM UTC 24
Peak memory 273172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336100105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3336100105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1583043726
Short name T404
Test name
Test status
Simulation time 15282061 ps
CPU time 1.3 seconds
Started Aug 27 06:55:58 AM UTC 24
Finished Aug 27 06:56:00 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583043726 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_volatile_unlock_smoke.1583043726
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2040575356
Short name T210
Test name
Test status
Simulation time 27211748 ps
CPU time 1.5 seconds
Started Aug 27 06:56:11 AM UTC 24
Finished Aug 27 06:56:14 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040575356 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2040575356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.2658880205
Short name T443
Test name
Test status
Simulation time 854194891 ps
CPU time 16.54 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:26 AM UTC 24
Peak memory 237904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658880205 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.2658880205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.1435474226
Short name T236
Test name
Test status
Simulation time 615975037 ps
CPU time 5.89 seconds
Started Aug 27 06:56:09 AM UTC 24
Finished Aug 27 06:56:17 AM UTC 24
Peak memory 229880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1435474226 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_acce
ss.1435474226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.2754684492
Short name T472
Test name
Test status
Simulation time 842834575 ps
CPU time 28.6 seconds
Started Aug 27 06:56:09 AM UTC 24
Finished Aug 27 06:56:40 AM UTC 24
Peak memory 237652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754684492
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_errors.2754684492
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.2384383111
Short name T209
Test name
Test status
Simulation time 268281291 ps
CPU time 3.22 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:12 AM UTC 24
Peak memory 234420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384383111
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_jtag_prog_failure.2384383111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.2310741902
Short name T431
Test name
Test status
Simulation time 1587946289 ps
CPU time 8.2 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:17 AM UTC 24
Peak memory 230040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310741902
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_smoke.2310741902
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.3789745140
Short name T500
Test name
Test status
Simulation time 1846402237 ps
CPU time 44.62 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:54 AM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789745140
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_
ctrl_jtag_state_failure.3789745140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3414252843
Short name T464
Test name
Test status
Simulation time 846984507 ps
CPU time 27.43 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:37 AM UTC 24
Peak memory 262780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414252843
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.
lc_ctrl_jtag_state_post_trans.3414252843
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.3846013693
Short name T205
Test name
Test status
Simulation time 130510018 ps
CPU time 2.23 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:10 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846013693 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.3846013693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.1729535763
Short name T439
Test name
Test status
Simulation time 303784658 ps
CPU time 11.48 seconds
Started Aug 27 06:56:09 AM UTC 24
Finished Aug 27 06:56:23 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729535763 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1729535763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.1936713746
Short name T454
Test name
Test status
Simulation time 1464629094 ps
CPU time 19.75 seconds
Started Aug 27 06:56:11 AM UTC 24
Finished Aug 27 06:56:32 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936713746 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_
token_digest.1936713746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.635607682
Short name T436
Test name
Test status
Simulation time 475609576 ps
CPU time 9.22 seconds
Started Aug 27 06:56:11 AM UTC 24
Finished Aug 27 06:56:21 AM UTC 24
Peak memory 232364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635607682 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_toke
n_mux.635607682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.2689789229
Short name T261
Test name
Test status
Simulation time 2831370336 ps
CPU time 9.57 seconds
Started Aug 27 06:56:08 AM UTC 24
Finished Aug 27 06:56:19 AM UTC 24
Peak memory 232220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689789229 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2689789229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.4263880329
Short name T427
Test name
Test status
Simulation time 75193324 ps
CPU time 1.66 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:09 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263880329 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4263880329
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.574380815
Short name T455
Test name
Test status
Simulation time 908739523 ps
CPU time 25.55 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:33 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574380815 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.574380815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.491101091
Short name T430
Test name
Test status
Simulation time 447567496 ps
CPU time 9.75 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:17 AM UTC 24
Peak memory 262756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491101091 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.491101091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.2994104544
Short name T836
Test name
Test status
Simulation time 43254481486 ps
CPU time 215.64 seconds
Started Aug 27 06:56:11 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 281344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2994104544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 15.lc_ctrl_stress_all.2994104544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3678324257
Short name T426
Test name
Test status
Simulation time 11147676 ps
CPU time 1.36 seconds
Started Aug 27 06:56:06 AM UTC 24
Finished Aug 27 06:56:09 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678324257 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_volatile_unlock_smoke.3678324257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1359648257
Short name T442
Test name
Test status
Simulation time 93018036 ps
CPU time 1.44 seconds
Started Aug 27 06:56:22 AM UTC 24
Finished Aug 27 06:56:25 AM UTC 24
Peak memory 218756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359648257 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1359648257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1572066473
Short name T453
Test name
Test status
Simulation time 362489006 ps
CPU time 13.36 seconds
Started Aug 27 06:56:15 AM UTC 24
Finished Aug 27 06:56:30 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572066473 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1572066473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1149298155
Short name T413
Test name
Test status
Simulation time 509981529 ps
CPU time 4.26 seconds
Started Aug 27 06:56:19 AM UTC 24
Finished Aug 27 06:56:24 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149298155 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_acce
ss.1149298155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.956285140
Short name T536
Test name
Test status
Simulation time 7070700676 ps
CPU time 51.03 seconds
Started Aug 27 06:56:19 AM UTC 24
Finished Aug 27 06:57:12 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956285140
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_errors.956285140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2969097369
Short name T446
Test name
Test status
Simulation time 177955332 ps
CPU time 8.02 seconds
Started Aug 27 06:56:18 AM UTC 24
Finished Aug 27 06:56:27 AM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969097369
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_jtag_prog_failure.2969097369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.3766447033
Short name T438
Test name
Test status
Simulation time 226774409 ps
CPU time 4.52 seconds
Started Aug 27 06:56:17 AM UTC 24
Finished Aug 27 06:56:22 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766447033
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_smoke.3766447033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2946678244
Short name T523
Test name
Test status
Simulation time 3705116877 ps
CPU time 46.52 seconds
Started Aug 27 06:56:18 AM UTC 24
Finished Aug 27 06:57:06 AM UTC 24
Peak memory 281244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946678244
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_
ctrl_jtag_state_failure.2946678244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.1219009275
Short name T451
Test name
Test status
Simulation time 1065570037 ps
CPU time 10.37 seconds
Started Aug 27 06:56:18 AM UTC 24
Finished Aug 27 06:56:29 AM UTC 24
Peak memory 234456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219009275
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.
lc_ctrl_jtag_state_post_trans.1219009275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.4191434587
Short name T432
Test name
Test status
Simulation time 53510913 ps
CPU time 2.09 seconds
Started Aug 27 06:56:14 AM UTC 24
Finished Aug 27 06:56:18 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191434587 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.4191434587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2761333256
Short name T75
Test name
Test status
Simulation time 1466189540 ps
CPU time 12.91 seconds
Started Aug 27 06:56:19 AM UTC 24
Finished Aug 27 06:56:33 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761333256 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2761333256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2359671166
Short name T456
Test name
Test status
Simulation time 828750862 ps
CPU time 11.39 seconds
Started Aug 27 06:56:20 AM UTC 24
Finished Aug 27 06:56:33 AM UTC 24
Peak memory 231976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359671166 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_
token_digest.2359671166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.4069377503
Short name T475
Test name
Test status
Simulation time 597833365 ps
CPU time 18.95 seconds
Started Aug 27 06:56:20 AM UTC 24
Finished Aug 27 06:56:41 AM UTC 24
Peak memory 232072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069377503 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_tok
en_mux.4069377503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2016497780
Short name T262
Test name
Test status
Simulation time 1135757740 ps
CPU time 8.6 seconds
Started Aug 27 06:56:17 AM UTC 24
Finished Aug 27 06:56:26 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016497780 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2016497780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2634532223
Short name T429
Test name
Test status
Simulation time 135678467 ps
CPU time 2.71 seconds
Started Aug 27 06:56:12 AM UTC 24
Finished Aug 27 06:56:16 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634532223 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.2634532223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.3622590573
Short name T461
Test name
Test status
Simulation time 172585301 ps
CPU time 22.35 seconds
Started Aug 27 06:56:12 AM UTC 24
Finished Aug 27 06:56:36 AM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622590573 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.3622590573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1232452033
Short name T441
Test name
Test status
Simulation time 1100588408 ps
CPU time 9.95 seconds
Started Aug 27 06:56:13 AM UTC 24
Finished Aug 27 06:56:24 AM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232452033 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1232452033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.3325855165
Short name T878
Test name
Test status
Simulation time 75431681378 ps
CPU time 1133.02 seconds
Started Aug 27 06:56:22 AM UTC 24
Finished Aug 27 07:15:27 AM UTC 24
Peak memory 363316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3325855165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 16.lc_ctrl_stress_all.3325855165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1173370696
Short name T166
Test name
Test status
Simulation time 2602418229 ps
CPU time 81.85 seconds
Started Aug 27 06:56:22 AM UTC 24
Finished Aug 27 06:57:46 AM UTC 24
Peak memory 287416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173370696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1173370696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.212721771
Short name T211
Test name
Test status
Simulation time 126486046 ps
CPU time 1.31 seconds
Started Aug 27 06:56:12 AM UTC 24
Finished Aug 27 06:56:14 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212721771 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.lc_ctrl_volatile_unlock_smoke.212721771
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1401924455
Short name T457
Test name
Test status
Simulation time 58079876 ps
CPU time 1.53 seconds
Started Aug 27 06:56:31 AM UTC 24
Finished Aug 27 06:56:34 AM UTC 24
Peak memory 218444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401924455 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1401924455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.4135786756
Short name T466
Test name
Test status
Simulation time 1609545506 ps
CPU time 11.7 seconds
Started Aug 27 06:56:26 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 237976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135786756 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.4135786756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.681803447
Short name T469
Test name
Test status
Simulation time 1030368099 ps
CPU time 9.04 seconds
Started Aug 27 06:56:29 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681803447 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.681803447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.4195154128
Short name T510
Test name
Test status
Simulation time 6642891978 ps
CPU time 29.21 seconds
Started Aug 27 06:56:27 AM UTC 24
Finished Aug 27 06:56:58 AM UTC 24
Peak memory 237904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195154128
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_errors.4195154128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.2353645638
Short name T462
Test name
Test status
Simulation time 253041029 ps
CPU time 7.45 seconds
Started Aug 27 06:56:27 AM UTC 24
Finished Aug 27 06:56:36 AM UTC 24
Peak memory 232108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353645638
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_jtag_prog_failure.2353645638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.1682445934
Short name T91
Test name
Test status
Simulation time 1828267687 ps
CPU time 8.71 seconds
Started Aug 27 06:56:27 AM UTC 24
Finished Aug 27 06:56:37 AM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682445934
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_smoke.1682445934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.1320911949
Short name T532
Test name
Test status
Simulation time 6913895278 ps
CPU time 40.45 seconds
Started Aug 27 06:56:27 AM UTC 24
Finished Aug 27 06:57:09 AM UTC 24
Peak memory 287312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320911949
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_
ctrl_jtag_state_failure.1320911949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.4203647746
Short name T497
Test name
Test status
Simulation time 920715143 ps
CPU time 24.52 seconds
Started Aug 27 06:56:27 AM UTC 24
Finished Aug 27 06:56:53 AM UTC 24
Peak memory 262700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4203647746
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.
lc_ctrl_jtag_state_post_trans.4203647746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.3430975595
Short name T452
Test name
Test status
Simulation time 38602795 ps
CPU time 2.45 seconds
Started Aug 27 06:56:26 AM UTC 24
Finished Aug 27 06:56:29 AM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430975595 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3430975595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.1156210084
Short name T481
Test name
Test status
Simulation time 402992623 ps
CPU time 12.71 seconds
Started Aug 27 06:56:29 AM UTC 24
Finished Aug 27 06:56:43 AM UTC 24
Peak memory 238144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156210084 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1156210084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.311213954
Short name T479
Test name
Test status
Simulation time 354750790 ps
CPU time 11.87 seconds
Started Aug 27 06:56:29 AM UTC 24
Finished Aug 27 06:56:42 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311213954 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_t
oken_digest.311213954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1812332911
Short name T470
Test name
Test status
Simulation time 1254724773 ps
CPU time 9.03 seconds
Started Aug 27 06:56:29 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812332911 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_tok
en_mux.1812332911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.707158123
Short name T463
Test name
Test status
Simulation time 535441029 ps
CPU time 9.53 seconds
Started Aug 27 06:56:26 AM UTC 24
Finished Aug 27 06:56:36 AM UTC 24
Peak memory 232508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707158123 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.707158123
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.1407216303
Short name T447
Test name
Test status
Simulation time 297216973 ps
CPU time 3.1 seconds
Started Aug 27 06:56:23 AM UTC 24
Finished Aug 27 06:56:28 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407216303 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1407216303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2123459134
Short name T495
Test name
Test status
Simulation time 333836439 ps
CPU time 27.53 seconds
Started Aug 27 06:56:23 AM UTC 24
Finished Aug 27 06:56:52 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123459134 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2123459134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.1393837350
Short name T458
Test name
Test status
Simulation time 233201688 ps
CPU time 7.79 seconds
Started Aug 27 06:56:26 AM UTC 24
Finished Aug 27 06:56:35 AM UTC 24
Peak memory 260684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393837350 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.1393837350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.798432103
Short name T202
Test name
Test status
Simulation time 17350165693 ps
CPU time 133.85 seconds
Started Aug 27 06:56:30 AM UTC 24
Finished Aug 27 06:58:46 AM UTC 24
Peak memory 264928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=798432103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 17.lc_ctrl_stress_all.798432103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.4206051350
Short name T168
Test name
Test status
Simulation time 5931384897 ps
CPU time 104.39 seconds
Started Aug 27 06:56:30 AM UTC 24
Finished Aug 27 06:58:16 AM UTC 24
Peak memory 293652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206051350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.4206051350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2296305397
Short name T444
Test name
Test status
Simulation time 47625462 ps
CPU time 1.28 seconds
Started Aug 27 06:56:23 AM UTC 24
Finished Aug 27 06:56:26 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296305397 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_volatile_unlock_smoke.2296305397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1943100034
Short name T480
Test name
Test status
Simulation time 41019134 ps
CPU time 1.41 seconds
Started Aug 27 06:56:41 AM UTC 24
Finished Aug 27 06:56:43 AM UTC 24
Peak memory 218876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943100034 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1943100034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.149417715
Short name T484
Test name
Test status
Simulation time 1246701019 ps
CPU time 9.88 seconds
Started Aug 27 06:56:35 AM UTC 24
Finished Aug 27 06:56:46 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149417715 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.149417715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.3025111623
Short name T477
Test name
Test status
Simulation time 672080451 ps
CPU time 2.81 seconds
Started Aug 27 06:56:38 AM UTC 24
Finished Aug 27 06:56:42 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025111623 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_acce
ss.3025111623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3840649185
Short name T476
Test name
Test status
Simulation time 51990643 ps
CPU time 2.67 seconds
Started Aug 27 06:56:38 AM UTC 24
Finished Aug 27 06:56:41 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840649185
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_jtag_prog_failure.3840649185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.1248708279
Short name T473
Test name
Test status
Simulation time 93712951 ps
CPU time 3.32 seconds
Started Aug 27 06:56:36 AM UTC 24
Finished Aug 27 06:56:40 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248708279
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_smoke.1248708279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.12058109
Short name T565
Test name
Test status
Simulation time 5416833972 ps
CPU time 49.28 seconds
Started Aug 27 06:56:36 AM UTC 24
Finished Aug 27 06:57:27 AM UTC 24
Peak memory 281156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12058109 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_jtag_state_failure.12058109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3679941407
Short name T494
Test name
Test status
Simulation time 1916318235 ps
CPU time 13.62 seconds
Started Aug 27 06:56:38 AM UTC 24
Finished Aug 27 06:56:52 AM UTC 24
Peak memory 258540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679941407
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.
lc_ctrl_jtag_state_post_trans.3679941407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1560760
Short name T467
Test name
Test status
Simulation time 25465505 ps
CPU time 2.82 seconds
Started Aug 27 06:56:35 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 234500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560760 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1560760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1498802858
Short name T524
Test name
Test status
Simulation time 1508099605 ps
CPU time 26.49 seconds
Started Aug 27 06:56:39 AM UTC 24
Finished Aug 27 06:57:07 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1498802858 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1498802858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1330191648
Short name T493
Test name
Test status
Simulation time 277091917 ps
CPU time 11.37 seconds
Started Aug 27 06:56:39 AM UTC 24
Finished Aug 27 06:56:51 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330191648 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_
token_digest.1330191648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.2759768092
Short name T490
Test name
Test status
Simulation time 2404802854 ps
CPU time 8.15 seconds
Started Aug 27 06:56:39 AM UTC 24
Finished Aug 27 06:56:48 AM UTC 24
Peak memory 230444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759768092 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_tok
en_mux.2759768092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.900967623
Short name T488
Test name
Test status
Simulation time 566496998 ps
CPU time 9.99 seconds
Started Aug 27 06:56:36 AM UTC 24
Finished Aug 27 06:56:47 AM UTC 24
Peak memory 232508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=900967623 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.900967623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1319644005
Short name T468
Test name
Test status
Simulation time 87114616 ps
CPU time 6.76 seconds
Started Aug 27 06:56:31 AM UTC 24
Finished Aug 27 06:56:39 AM UTC 24
Peak memory 229956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319644005 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1319644005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.2337026069
Short name T535
Test name
Test status
Simulation time 2931332842 ps
CPU time 35.94 seconds
Started Aug 27 06:56:34 AM UTC 24
Finished Aug 27 06:57:11 AM UTC 24
Peak memory 260752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337026069 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2337026069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.2242782722
Short name T486
Test name
Test status
Simulation time 225158422 ps
CPU time 10.67 seconds
Started Aug 27 06:56:35 AM UTC 24
Finished Aug 27 06:56:47 AM UTC 24
Peak memory 263076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242782722 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2242782722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.2389804124
Short name T628
Test name
Test status
Simulation time 8112616281 ps
CPU time 78.63 seconds
Started Aug 27 06:56:40 AM UTC 24
Finished Aug 27 06:58:01 AM UTC 24
Peak memory 264952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2389804124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 18.lc_ctrl_stress_all.2389804124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2095334225
Short name T460
Test name
Test status
Simulation time 31732097 ps
CPU time 1.09 seconds
Started Aug 27 06:56:34 AM UTC 24
Finished Aug 27 06:56:36 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095334225 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_volatile_unlock_smoke.2095334225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.2601104152
Short name T491
Test name
Test status
Simulation time 62845821 ps
CPU time 1.53 seconds
Started Aug 27 06:56:48 AM UTC 24
Finished Aug 27 06:56:50 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601104152 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2601104152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.49876617
Short name T499
Test name
Test status
Simulation time 760930736 ps
CPU time 10.36 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:56:54 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49876617 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.49876617
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.1425643326
Short name T487
Test name
Test status
Simulation time 40367624 ps
CPU time 1.59 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:56:47 AM UTC 24
Peak memory 228992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425643326 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_acce
ss.1425643326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.467368538
Short name T590
Test name
Test status
Simulation time 2077187709 ps
CPU time 52.78 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:57:38 AM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467368538
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_errors.467368538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.4261380091
Short name T503
Test name
Test status
Simulation time 5762208042 ps
CPU time 9.76 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:56:55 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261380091
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_jtag_prog_failure.4261380091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.3125616292
Short name T489
Test name
Test status
Simulation time 3212991400 ps
CPU time 4.63 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:56:48 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125616292
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_smoke.3125616292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1281250534
Short name T619
Test name
Test status
Simulation time 2305193262 ps
CPU time 70.15 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:57:54 AM UTC 24
Peak memory 283292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281250534
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_
ctrl_jtag_state_failure.1281250534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.3382249274
Short name T521
Test name
Test status
Simulation time 5912765427 ps
CPU time 21.63 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:57:05 AM UTC 24
Peak memory 262840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3382249274
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.
lc_ctrl_jtag_state_post_trans.3382249274
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.1813936710
Short name T485
Test name
Test status
Simulation time 70296934 ps
CPU time 2.99 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:56:46 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813936710 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1813936710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.2084762018
Short name T511
Test name
Test status
Simulation time 5299605210 ps
CPU time 13.04 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:56:58 AM UTC 24
Peak memory 232300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084762018 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2084762018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1708826333
Short name T515
Test name
Test status
Simulation time 1911170543 ps
CPU time 17.36 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:57:03 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708826333 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_
token_digest.1708826333
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.168992239
Short name T505
Test name
Test status
Simulation time 236268446 ps
CPU time 10.25 seconds
Started Aug 27 06:56:44 AM UTC 24
Finished Aug 27 06:56:55 AM UTC 24
Peak memory 230192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168992239 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_toke
n_mux.168992239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3766320167
Short name T498
Test name
Test status
Simulation time 962256370 ps
CPU time 10.32 seconds
Started Aug 27 06:56:42 AM UTC 24
Finished Aug 27 06:56:54 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766320167 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3766320167
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3451948525
Short name T483
Test name
Test status
Simulation time 172848578 ps
CPU time 1.96 seconds
Started Aug 27 06:56:41 AM UTC 24
Finished Aug 27 06:56:44 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451948525 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3451948525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.525531895
Short name T465
Test name
Test status
Simulation time 172237407 ps
CPU time 19.71 seconds
Started Aug 27 06:56:41 AM UTC 24
Finished Aug 27 06:57:02 AM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525531895 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.525531895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.810177834
Short name T496
Test name
Test status
Simulation time 1504610979 ps
CPU time 10.63 seconds
Started Aug 27 06:56:41 AM UTC 24
Finished Aug 27 06:56:53 AM UTC 24
Peak memory 262724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810177834 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.810177834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3234030109
Short name T870
Test name
Test status
Simulation time 56283168741 ps
CPU time 283.72 seconds
Started Aug 27 06:56:45 AM UTC 24
Finished Aug 27 07:01:33 AM UTC 24
Peak memory 322236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3234030109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 19.lc_ctrl_stress_all.3234030109
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2345861718
Short name T170
Test name
Test status
Simulation time 5090588452 ps
CPU time 96.36 seconds
Started Aug 27 06:56:47 AM UTC 24
Finished Aug 27 06:58:25 AM UTC 24
Peak memory 263352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345861718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2345861718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2962375676
Short name T482
Test name
Test status
Simulation time 14796277 ps
CPU time 1.52 seconds
Started Aug 27 06:56:41 AM UTC 24
Finished Aug 27 06:56:43 AM UTC 24
Peak memory 220636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962375676 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_volatile_unlock_smoke.2962375676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.4147551785
Short name T104
Test name
Test status
Simulation time 21312150 ps
CPU time 1.69 seconds
Started Aug 27 06:54:17 AM UTC 24
Finished Aug 27 06:54:20 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147551785 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4147551785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.2507234245
Short name T22
Test name
Test status
Simulation time 246718232 ps
CPU time 9.12 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:17 AM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507234245 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2507234245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.755722663
Short name T102
Test name
Test status
Simulation time 3124148402 ps
CPU time 48.86 seconds
Started Aug 27 06:54:12 AM UTC 24
Finished Aug 27 06:55:02 AM UTC 24
Peak memory 232364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755722663
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_errors.755722663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.2882905729
Short name T80
Test name
Test status
Simulation time 608989816 ps
CPU time 3.64 seconds
Started Aug 27 06:54:13 AM UTC 24
Finished Aug 27 06:54:18 AM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882905729 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_pri
ority.2882905729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.861105751
Short name T270
Test name
Test status
Simulation time 2713888966 ps
CPU time 16.74 seconds
Started Aug 27 06:54:11 AM UTC 24
Finished Aug 27 06:54:28 AM UTC 24
Peak memory 236268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861105751
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctr
l_jtag_prog_failure.861105751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.4116308179
Short name T97
Test name
Test status
Simulation time 4339321840 ps
CPU time 14.42 seconds
Started Aug 27 06:54:13 AM UTC 24
Finished Aug 27 06:54:29 AM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116308179
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l
c_ctrl_jtag_regwen_during_op.4116308179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.2858408657
Short name T30
Test name
Test status
Simulation time 402806002 ps
CPU time 5.94 seconds
Started Aug 27 06:54:10 AM UTC 24
Finished Aug 27 06:54:17 AM UTC 24
Peak memory 229340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858408657
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_smoke.2858408657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.3002009744
Short name T44
Test name
Test status
Simulation time 1276451917 ps
CPU time 15.06 seconds
Started Aug 27 06:54:11 AM UTC 24
Finished Aug 27 06:54:27 AM UTC 24
Peak memory 260712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002009744
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l
c_ctrl_jtag_state_post_trans.3002009744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.1118746640
Short name T135
Test name
Test status
Simulation time 90123078 ps
CPU time 3.15 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:11 AM UTC 24
Peak memory 234412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118746640 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1118746640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3912300388
Short name T79
Test name
Test status
Simulation time 196105768 ps
CPU time 7.16 seconds
Started Aug 27 06:54:09 AM UTC 24
Finished Aug 27 06:54:18 AM UTC 24
Peak memory 229812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912300388 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3912300388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.3886620127
Short name T118
Test name
Test status
Simulation time 431565703 ps
CPU time 34.6 seconds
Started Aug 27 06:54:16 AM UTC 24
Finished Aug 27 06:54:52 AM UTC 24
Peak memory 298092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886620127 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3886620127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.18182516
Short name T47
Test name
Test status
Simulation time 926273367 ps
CPU time 13.42 seconds
Started Aug 27 06:54:13 AM UTC 24
Finished Aug 27 06:54:28 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18182516 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.18182516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1935438585
Short name T41
Test name
Test status
Simulation time 869511241 ps
CPU time 9.84 seconds
Started Aug 27 06:54:14 AM UTC 24
Finished Aug 27 06:54:25 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935438585 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_t
oken_digest.1935438585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.1504103375
Short name T18
Test name
Test status
Simulation time 392307602 ps
CPU time 12.76 seconds
Started Aug 27 06:54:14 AM UTC 24
Finished Aug 27 06:54:28 AM UTC 24
Peak memory 237972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504103375 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_toke
n_mux.1504103375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.2563387403
Short name T68
Test name
Test status
Simulation time 819999585 ps
CPU time 8.78 seconds
Started Aug 27 06:54:08 AM UTC 24
Finished Aug 27 06:54:18 AM UTC 24
Peak memory 232448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563387403 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2563387403
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.543128284
Short name T269
Test name
Test status
Simulation time 20064835 ps
CPU time 2.08 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:10 AM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543128284 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.543128284
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.3352250552
Short name T288
Test name
Test status
Simulation time 5777359172 ps
CPU time 33.42 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:42 AM UTC 24
Peak memory 260912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352250552 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3352250552
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.865452774
Short name T99
Test name
Test status
Simulation time 69493264 ps
CPU time 10.29 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:18 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865452774 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.865452774
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.3822240496
Short name T282
Test name
Test status
Simulation time 640129188 ps
CPU time 23.06 seconds
Started Aug 27 06:54:16 AM UTC 24
Finished Aug 27 06:54:40 AM UTC 24
Peak memory 238168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3822240496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_stress_all.3822240496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2479700261
Short name T256
Test name
Test status
Simulation time 14228239 ps
CPU time 1.36 seconds
Started Aug 27 06:54:07 AM UTC 24
Finished Aug 27 06:54:09 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479700261 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_volatile_unlock_smoke.2479700261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.4066906912
Short name T508
Test name
Test status
Simulation time 130621192 ps
CPU time 1.17 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:56:58 AM UTC 24
Peak memory 216932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066906912 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.4066906912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.231546374
Short name T526
Test name
Test status
Simulation time 568211581 ps
CPU time 14.74 seconds
Started Aug 27 06:56:51 AM UTC 24
Finished Aug 27 06:57:07 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=231546374 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.231546374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.2007977787
Short name T507
Test name
Test status
Simulation time 672004511 ps
CPU time 5.31 seconds
Started Aug 27 06:56:51 AM UTC 24
Finished Aug 27 06:56:58 AM UTC 24
Peak memory 230104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007977787 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_acce
ss.2007977787
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.3578746227
Short name T502
Test name
Test status
Simulation time 544006622 ps
CPU time 4.16 seconds
Started Aug 27 06:56:49 AM UTC 24
Finished Aug 27 06:56:54 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578746227 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3578746227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1043341399
Short name T529
Test name
Test status
Simulation time 750073536 ps
CPU time 14.77 seconds
Started Aug 27 06:56:53 AM UTC 24
Finished Aug 27 06:57:08 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043341399 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1043341399
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.1876044724
Short name T530
Test name
Test status
Simulation time 398900016 ps
CPU time 13.87 seconds
Started Aug 27 06:56:54 AM UTC 24
Finished Aug 27 06:57:09 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876044724 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_
token_digest.1876044724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.4279425606
Short name T522
Test name
Test status
Simulation time 1137857074 ps
CPU time 10.7 seconds
Started Aug 27 06:56:54 AM UTC 24
Finished Aug 27 06:57:06 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279425606 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_tok
en_mux.4279425606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.3037443910
Short name T527
Test name
Test status
Simulation time 420774702 ps
CPU time 14.95 seconds
Started Aug 27 06:56:51 AM UTC 24
Finished Aug 27 06:57:07 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037443910 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3037443910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1380430455
Short name T92
Test name
Test status
Simulation time 42453484 ps
CPU time 1.77 seconds
Started Aug 27 06:56:48 AM UTC 24
Finished Aug 27 06:56:51 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380430455 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1380430455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.3771691029
Short name T540
Test name
Test status
Simulation time 875086468 ps
CPU time 24.08 seconds
Started Aug 27 06:56:48 AM UTC 24
Finished Aug 27 06:57:13 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771691029 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3771691029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.669614709
Short name T514
Test name
Test status
Simulation time 439979703 ps
CPU time 10.98 seconds
Started Aug 27 06:56:49 AM UTC 24
Finished Aug 27 06:57:01 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669614709 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.669614709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3317348276
Short name T864
Test name
Test status
Simulation time 18989944434 ps
CPU time 230.35 seconds
Started Aug 27 06:56:54 AM UTC 24
Finished Aug 27 07:00:47 AM UTC 24
Peak memory 279292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3317348276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 20.lc_ctrl_stress_all.3317348276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.3950569682
Short name T191
Test name
Test status
Simulation time 9970428410 ps
CPU time 106.88 seconds
Started Aug 27 06:56:54 AM UTC 24
Finished Aug 27 06:58:43 AM UTC 24
Peak memory 281444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950569682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.3950569682
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.410938281
Short name T492
Test name
Test status
Simulation time 26121566 ps
CPU time 1.66 seconds
Started Aug 27 06:56:48 AM UTC 24
Finished Aug 27 06:56:51 AM UTC 24
Peak memory 229036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410938281 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.lc_ctrl_volatile_unlock_smoke.410938281
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2478922967
Short name T450
Test name
Test status
Simulation time 23939586 ps
CPU time 1.2 seconds
Started Aug 27 06:57:00 AM UTC 24
Finished Aug 27 06:57:02 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478922967 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2478922967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.4023908358
Short name T541
Test name
Test status
Simulation time 739508982 ps
CPU time 14.89 seconds
Started Aug 27 06:56:57 AM UTC 24
Finished Aug 27 06:57:13 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023908358 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.4023908358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.3181070269
Short name T519
Test name
Test status
Simulation time 235260637 ps
CPU time 6.52 seconds
Started Aug 27 06:56:57 AM UTC 24
Finished Aug 27 06:57:05 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181070269 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_acce
ss.3181070269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2959091571
Short name T512
Test name
Test status
Simulation time 28863801 ps
CPU time 2.17 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:56:59 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959091571 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2959091571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1687478663
Short name T542
Test name
Test status
Simulation time 972621920 ps
CPU time 14.81 seconds
Started Aug 27 06:56:58 AM UTC 24
Finished Aug 27 06:57:14 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687478663 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1687478663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.539167485
Short name T558
Test name
Test status
Simulation time 700106027 ps
CPU time 23.52 seconds
Started Aug 27 06:56:58 AM UTC 24
Finished Aug 27 06:57:23 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539167485 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_t
oken_digest.539167485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3997585075
Short name T544
Test name
Test status
Simulation time 436148731 ps
CPU time 15.44 seconds
Started Aug 27 06:56:58 AM UTC 24
Finished Aug 27 06:57:15 AM UTC 24
Peak memory 230188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997585075 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_tok
en_mux.3997585075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.3856334820
Short name T533
Test name
Test status
Simulation time 307378230 ps
CPU time 11.66 seconds
Started Aug 27 06:56:57 AM UTC 24
Finished Aug 27 06:57:10 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856334820 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3856334820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.3069877420
Short name T513
Test name
Test status
Simulation time 409292094 ps
CPU time 4.13 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:57:01 AM UTC 24
Peak memory 230128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069877420 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3069877420
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2490679985
Short name T551
Test name
Test status
Simulation time 1022132870 ps
CPU time 22.2 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:57:19 AM UTC 24
Peak memory 258644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490679985 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2490679985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.4274859318
Short name T516
Test name
Test status
Simulation time 155649268 ps
CPU time 7.2 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:57:04 AM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274859318 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.4274859318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.1240122487
Short name T640
Test name
Test status
Simulation time 5480725034 ps
CPU time 64.19 seconds
Started Aug 27 06:57:00 AM UTC 24
Finished Aug 27 06:58:06 AM UTC 24
Peak memory 238028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1240122487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 21.lc_ctrl_stress_all.1240122487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.831420490
Short name T509
Test name
Test status
Simulation time 24992468 ps
CPU time 1.26 seconds
Started Aug 27 06:56:56 AM UTC 24
Finished Aug 27 06:56:58 AM UTC 24
Peak memory 229036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831420490 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
1.lc_ctrl_volatile_unlock_smoke.831420490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.3339033095
Short name T531
Test name
Test status
Simulation time 18608013 ps
CPU time 1.37 seconds
Started Aug 27 06:57:07 AM UTC 24
Finished Aug 27 06:57:09 AM UTC 24
Peak memory 217252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339033095 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3339033095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1193288914
Short name T548
Test name
Test status
Simulation time 342107044 ps
CPU time 12.31 seconds
Started Aug 27 06:57:04 AM UTC 24
Finished Aug 27 06:57:17 AM UTC 24
Peak memory 232452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193288914 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1193288914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.2521718018
Short name T577
Test name
Test status
Simulation time 4913505693 ps
CPU time 25.9 seconds
Started Aug 27 06:57:05 AM UTC 24
Finished Aug 27 06:57:32 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521718018 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_acce
ss.2521718018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.1905474642
Short name T528
Test name
Test status
Simulation time 63640472 ps
CPU time 2.91 seconds
Started Aug 27 06:57:04 AM UTC 24
Finished Aug 27 06:57:08 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905474642 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1905474642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.3894404835
Short name T549
Test name
Test status
Simulation time 270043318 ps
CPU time 10.74 seconds
Started Aug 27 06:57:07 AM UTC 24
Finished Aug 27 06:57:18 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894404835 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3894404835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1973134943
Short name T578
Test name
Test status
Simulation time 1175143259 ps
CPU time 24.8 seconds
Started Aug 27 06:57:07 AM UTC 24
Finished Aug 27 06:57:33 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973134943 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_
token_digest.1973134943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.1520826521
Short name T547
Test name
Test status
Simulation time 799388243 ps
CPU time 9.25 seconds
Started Aug 27 06:57:07 AM UTC 24
Finished Aug 27 06:57:17 AM UTC 24
Peak memory 237944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520826521 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_tok
en_mux.1520826521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.796265538
Short name T543
Test name
Test status
Simulation time 663418115 ps
CPU time 8.64 seconds
Started Aug 27 06:57:05 AM UTC 24
Finished Aug 27 06:57:14 AM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796265538 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.796265538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.379662665
Short name T525
Test name
Test status
Simulation time 56986928 ps
CPU time 3.95 seconds
Started Aug 27 06:57:02 AM UTC 24
Finished Aug 27 06:57:07 AM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379662665 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.379662665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.2026496982
Short name T568
Test name
Test status
Simulation time 160181157 ps
CPU time 22.49 seconds
Started Aug 27 06:57:04 AM UTC 24
Finished Aug 27 06:57:27 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026496982 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2026496982
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1455085740
Short name T537
Test name
Test status
Simulation time 369679111 ps
CPU time 7.28 seconds
Started Aug 27 06:57:04 AM UTC 24
Finished Aug 27 06:57:12 AM UTC 24
Peak memory 260544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455085740 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1455085740
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.3554957795
Short name T654
Test name
Test status
Simulation time 11741684010 ps
CPU time 69.15 seconds
Started Aug 27 06:57:07 AM UTC 24
Finished Aug 27 06:58:18 AM UTC 24
Peak memory 283496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3554957795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 22.lc_ctrl_stress_all.3554957795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1006483056
Short name T517
Test name
Test status
Simulation time 42187757 ps
CPU time 1.04 seconds
Started Aug 27 06:57:02 AM UTC 24
Finished Aug 27 06:57:04 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006483056 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_volatile_unlock_smoke.1006483056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.3552204598
Short name T85
Test name
Test status
Simulation time 28705239 ps
CPU time 1.37 seconds
Started Aug 27 06:57:13 AM UTC 24
Finished Aug 27 06:57:15 AM UTC 24
Peak memory 218992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552204598 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3552204598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.3113657046
Short name T556
Test name
Test status
Simulation time 958687382 ps
CPU time 11.49 seconds
Started Aug 27 06:57:10 AM UTC 24
Finished Aug 27 06:57:22 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113657046 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3113657046
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.3445886480
Short name T562
Test name
Test status
Simulation time 2445785508 ps
CPU time 14.94 seconds
Started Aug 27 06:57:10 AM UTC 24
Finished Aug 27 06:57:26 AM UTC 24
Peak memory 229952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445886480 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_acce
ss.3445886480
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.713761066
Short name T539
Test name
Test status
Simulation time 82604078 ps
CPU time 3.37 seconds
Started Aug 27 06:57:08 AM UTC 24
Finished Aug 27 06:57:13 AM UTC 24
Peak memory 234484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713761066 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.713761066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.3178297314
Short name T567
Test name
Test status
Simulation time 350968985 ps
CPU time 14.89 seconds
Started Aug 27 06:57:11 AM UTC 24
Finished Aug 27 06:57:27 AM UTC 24
Peak memory 238152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178297314 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3178297314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.3959929135
Short name T563
Test name
Test status
Simulation time 310189198 ps
CPU time 13.91 seconds
Started Aug 27 06:57:11 AM UTC 24
Finished Aug 27 06:57:26 AM UTC 24
Peak memory 230124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959929135 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_
token_digest.3959929135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1587319731
Short name T557
Test name
Test status
Simulation time 396225320 ps
CPU time 10.55 seconds
Started Aug 27 06:57:11 AM UTC 24
Finished Aug 27 06:57:23 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587319731 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_tok
en_mux.1587319731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.960075976
Short name T555
Test name
Test status
Simulation time 2715792948 ps
CPU time 11.25 seconds
Started Aug 27 06:57:10 AM UTC 24
Finished Aug 27 06:57:22 AM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960075976 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.960075976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.1277097511
Short name T538
Test name
Test status
Simulation time 47950617 ps
CPU time 2.95 seconds
Started Aug 27 06:57:08 AM UTC 24
Finished Aug 27 06:57:12 AM UTC 24
Peak memory 225840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277097511 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1277097511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.338105924
Short name T564
Test name
Test status
Simulation time 338657068 ps
CPU time 16.75 seconds
Started Aug 27 06:57:08 AM UTC 24
Finished Aug 27 06:57:26 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338105924 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.338105924
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.4292779515
Short name T550
Test name
Test status
Simulation time 935048200 ps
CPU time 8.92 seconds
Started Aug 27 06:57:08 AM UTC 24
Finished Aug 27 06:57:18 AM UTC 24
Peak memory 260612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292779515 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4292779515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2247062739
Short name T660
Test name
Test status
Simulation time 2895907362 ps
CPU time 66.29 seconds
Started Aug 27 06:57:13 AM UTC 24
Finished Aug 27 06:58:21 AM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2247062739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 23.lc_ctrl_stress_all.2247062739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3932796127
Short name T534
Test name
Test status
Simulation time 15193813 ps
CPU time 1.34 seconds
Started Aug 27 06:57:08 AM UTC 24
Finished Aug 27 06:57:11 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932796127 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_volatile_unlock_smoke.3932796127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.3823907814
Short name T554
Test name
Test status
Simulation time 32184370 ps
CPU time 1.52 seconds
Started Aug 27 06:57:19 AM UTC 24
Finished Aug 27 06:57:22 AM UTC 24
Peak memory 218756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3823907814 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3823907814
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.1821511482
Short name T566
Test name
Test status
Simulation time 241364102 ps
CPU time 10.51 seconds
Started Aug 27 06:57:15 AM UTC 24
Finished Aug 27 06:57:27 AM UTC 24
Peak memory 232120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821511482 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1821511482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.2190967697
Short name T560
Test name
Test status
Simulation time 532976731 ps
CPU time 6.42 seconds
Started Aug 27 06:57:17 AM UTC 24
Finished Aug 27 06:57:24 AM UTC 24
Peak memory 230116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190967697 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_acce
ss.2190967697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.867614694
Short name T553
Test name
Test status
Simulation time 196378273 ps
CPU time 3.92 seconds
Started Aug 27 06:57:15 AM UTC 24
Finished Aug 27 06:57:20 AM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867614694 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.867614694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.4275038978
Short name T571
Test name
Test status
Simulation time 1030890461 ps
CPU time 10.69 seconds
Started Aug 27 06:57:17 AM UTC 24
Finished Aug 27 06:57:28 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275038978 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.4275038978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.185784966
Short name T570
Test name
Test status
Simulation time 191542408 ps
CPU time 8.65 seconds
Started Aug 27 06:57:18 AM UTC 24
Finished Aug 27 06:57:28 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185784966 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_t
oken_digest.185784966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.274008636
Short name T588
Test name
Test status
Simulation time 4365893793 ps
CPU time 17.78 seconds
Started Aug 27 06:57:18 AM UTC 24
Finished Aug 27 06:57:37 AM UTC 24
Peak memory 232496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274008636 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_toke
n_mux.274008636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.2432082599
Short name T574
Test name
Test status
Simulation time 300579443 ps
CPU time 12.12 seconds
Started Aug 27 06:57:17 AM UTC 24
Finished Aug 27 06:57:30 AM UTC 24
Peak memory 238156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432082599 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2432082599
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3965123018
Short name T545
Test name
Test status
Simulation time 43805094 ps
CPU time 2.49 seconds
Started Aug 27 06:57:13 AM UTC 24
Finished Aug 27 06:57:16 AM UTC 24
Peak memory 225908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965123018 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3965123018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2587322128
Short name T599
Test name
Test status
Simulation time 1195891570 ps
CPU time 26.35 seconds
Started Aug 27 06:57:14 AM UTC 24
Finished Aug 27 06:57:42 AM UTC 24
Peak memory 260964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587322128 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2587322128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.467729355
Short name T573
Test name
Test status
Simulation time 618489688 ps
CPU time 14.02 seconds
Started Aug 27 06:57:14 AM UTC 24
Finished Aug 27 06:57:29 AM UTC 24
Peak memory 262812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467729355 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.467729355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.790665945
Short name T871
Test name
Test status
Simulation time 9135049451 ps
CPU time 263.91 seconds
Started Aug 27 06:57:18 AM UTC 24
Finished Aug 27 07:01:46 AM UTC 24
Peak memory 262872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=790665945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 24.lc_ctrl_stress_all.790665945
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1237212569
Short name T546
Test name
Test status
Simulation time 14277716 ps
CPU time 1.5 seconds
Started Aug 27 06:57:14 AM UTC 24
Finished Aug 27 06:57:16 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237212569 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_volatile_unlock_smoke.1237212569
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.579814640
Short name T576
Test name
Test status
Simulation time 35471638 ps
CPU time 1.66 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:31 AM UTC 24
Peak memory 218640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579814640 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.579814640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1815414728
Short name T580
Test name
Test status
Simulation time 888631810 ps
CPU time 8.33 seconds
Started Aug 27 06:57:23 AM UTC 24
Finished Aug 27 06:57:33 AM UTC 24
Peak memory 230400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815414728 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1815414728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.4231761247
Short name T581
Test name
Test status
Simulation time 1079782920 ps
CPU time 8.62 seconds
Started Aug 27 06:57:23 AM UTC 24
Finished Aug 27 06:57:33 AM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231761247 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_acce
ss.4231761247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.463911061
Short name T572
Test name
Test status
Simulation time 63390757 ps
CPU time 4.71 seconds
Started Aug 27 06:57:23 AM UTC 24
Finished Aug 27 06:57:29 AM UTC 24
Peak memory 236168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463911061 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.463911061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1586287138
Short name T604
Test name
Test status
Simulation time 370650364 ps
CPU time 19.06 seconds
Started Aug 27 06:57:25 AM UTC 24
Finished Aug 27 06:57:45 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586287138 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1586287138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1899245850
Short name T579
Test name
Test status
Simulation time 875725561 ps
CPU time 6.93 seconds
Started Aug 27 06:57:25 AM UTC 24
Finished Aug 27 06:57:33 AM UTC 24
Peak memory 232512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899245850 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_
token_digest.1899245850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1218974611
Short name T585
Test name
Test status
Simulation time 512123801 ps
CPU time 8.88 seconds
Started Aug 27 06:57:25 AM UTC 24
Finished Aug 27 06:57:35 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218974611 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_tok
en_mux.1218974611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.1173321968
Short name T589
Test name
Test status
Simulation time 1126037860 ps
CPU time 12.43 seconds
Started Aug 27 06:57:23 AM UTC 24
Finished Aug 27 06:57:37 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173321968 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1173321968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.4137637868
Short name T559
Test name
Test status
Simulation time 26599268 ps
CPU time 2.3 seconds
Started Aug 27 06:57:20 AM UTC 24
Finished Aug 27 06:57:24 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137637868 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4137637868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.2754567064
Short name T226
Test name
Test status
Simulation time 247359288 ps
CPU time 24.12 seconds
Started Aug 27 06:57:22 AM UTC 24
Finished Aug 27 06:57:47 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754567064 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2754567064
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.2027323237
Short name T593
Test name
Test status
Simulation time 192419322 ps
CPU time 15.71 seconds
Started Aug 27 06:57:22 AM UTC 24
Finished Aug 27 06:57:39 AM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2027323237 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2027323237
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.1255956586
Short name T861
Test name
Test status
Simulation time 12452695518 ps
CPU time 187.38 seconds
Started Aug 27 06:57:25 AM UTC 24
Finished Aug 27 07:00:35 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1255956586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 25.lc_ctrl_stress_all.1255956586
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.823821698
Short name T801
Test name
Test status
Simulation time 13538805078 ps
CPU time 123.75 seconds
Started Aug 27 06:57:26 AM UTC 24
Finished Aug 27 06:59:32 AM UTC 24
Peak memory 289636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823821698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.823821698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4229587384
Short name T561
Test name
Test status
Simulation time 14659900 ps
CPU time 1.54 seconds
Started Aug 27 06:57:22 AM UTC 24
Finished Aug 27 06:57:24 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229587384 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_volatile_unlock_smoke.4229587384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.3524472212
Short name T583
Test name
Test status
Simulation time 77939536 ps
CPU time 1.21 seconds
Started Aug 27 06:57:31 AM UTC 24
Finished Aug 27 06:57:34 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524472212 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3524472212
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1147712615
Short name T61
Test name
Test status
Simulation time 7287715775 ps
CPU time 12.84 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:44 AM UTC 24
Peak memory 237916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147712615 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1147712615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1961655411
Short name T594
Test name
Test status
Simulation time 844386026 ps
CPU time 9.35 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:40 AM UTC 24
Peak memory 229808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961655411 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_acce
ss.1961655411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.3886092876
Short name T582
Test name
Test status
Simulation time 144038206 ps
CPU time 4.05 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:33 AM UTC 24
Peak memory 236356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886092876 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3886092876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2874750660
Short name T222
Test name
Test status
Simulation time 444577512 ps
CPU time 15.01 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:46 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874750660 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2874750660
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.1102213026
Short name T227
Test name
Test status
Simulation time 2090021255 ps
CPU time 16.12 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:47 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102213026 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_
token_digest.1102213026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.2057987207
Short name T611
Test name
Test status
Simulation time 3060969952 ps
CPU time 19.36 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:50 AM UTC 24
Peak memory 237948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057987207 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_tok
en_mux.2057987207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1848971895
Short name T595
Test name
Test status
Simulation time 304229279 ps
CPU time 10.14 seconds
Started Aug 27 06:57:30 AM UTC 24
Finished Aug 27 06:57:41 AM UTC 24
Peak memory 232224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848971895 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1848971895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.80575699
Short name T584
Test name
Test status
Simulation time 91700082 ps
CPU time 5.36 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:34 AM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80575699 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.80575699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.4160702456
Short name T608
Test name
Test status
Simulation time 155237943 ps
CPU time 19.37 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:49 AM UTC 24
Peak memory 260772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160702456 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4160702456
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.1675446685
Short name T592
Test name
Test status
Simulation time 187965535 ps
CPU time 9.37 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:39 AM UTC 24
Peak memory 258568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675446685 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1675446685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3818903247
Short name T95
Test name
Test status
Simulation time 37418230459 ps
CPU time 109.66 seconds
Started Aug 27 06:57:31 AM UTC 24
Finished Aug 27 06:59:23 AM UTC 24
Peak memory 287376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3818903247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 26.lc_ctrl_stress_all.3818903247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.660936359
Short name T575
Test name
Test status
Simulation time 39666722 ps
CPU time 1.21 seconds
Started Aug 27 06:57:28 AM UTC 24
Finished Aug 27 06:57:30 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660936359 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2
6.lc_ctrl_volatile_unlock_smoke.660936359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1000926684
Short name T596
Test name
Test status
Simulation time 154028780 ps
CPU time 1.2 seconds
Started Aug 27 06:57:39 AM UTC 24
Finished Aug 27 06:57:41 AM UTC 24
Peak memory 218944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000926684 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1000926684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.1490117338
Short name T601
Test name
Test status
Simulation time 395683365 ps
CPU time 9.05 seconds
Started Aug 27 06:57:34 AM UTC 24
Finished Aug 27 06:57:44 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490117338 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1490117338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3718341360
Short name T223
Test name
Test status
Simulation time 705174876 ps
CPU time 10.38 seconds
Started Aug 27 06:57:35 AM UTC 24
Finished Aug 27 06:57:47 AM UTC 24
Peak memory 230088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718341360 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_acce
ss.3718341360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.3329257675
Short name T591
Test name
Test status
Simulation time 120127712 ps
CPU time 3.16 seconds
Started Aug 27 06:57:34 AM UTC 24
Finished Aug 27 06:57:38 AM UTC 24
Peak memory 232196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329257675 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3329257675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.899010338
Short name T621
Test name
Test status
Simulation time 2595290817 ps
CPU time 19.38 seconds
Started Aug 27 06:57:35 AM UTC 24
Finished Aug 27 06:57:56 AM UTC 24
Peak memory 237948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899010338 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.899010338
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.1582587416
Short name T610
Test name
Test status
Simulation time 366263200 ps
CPU time 11.24 seconds
Started Aug 27 06:57:38 AM UTC 24
Finished Aug 27 06:57:50 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582587416 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_
token_digest.1582587416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.2526944180
Short name T605
Test name
Test status
Simulation time 168061147 ps
CPU time 8.01 seconds
Started Aug 27 06:57:36 AM UTC 24
Finished Aug 27 06:57:45 AM UTC 24
Peak memory 232300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526944180 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_tok
en_mux.2526944180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2048934576
Short name T600
Test name
Test status
Simulation time 372732453 ps
CPU time 7.32 seconds
Started Aug 27 06:57:35 AM UTC 24
Finished Aug 27 06:57:43 AM UTC 24
Peak memory 237144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048934576 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2048934576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3426571386
Short name T586
Test name
Test status
Simulation time 22721733 ps
CPU time 2.09 seconds
Started Aug 27 06:57:32 AM UTC 24
Finished Aug 27 06:57:36 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426571386 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3426571386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.1040392331
Short name T623
Test name
Test status
Simulation time 354616818 ps
CPU time 22.2 seconds
Started Aug 27 06:57:34 AM UTC 24
Finished Aug 27 06:57:57 AM UTC 24
Peak memory 262748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040392331 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1040392331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3512462987
Short name T224
Test name
Test status
Simulation time 868803056 ps
CPU time 11.66 seconds
Started Aug 27 06:57:34 AM UTC 24
Finished Aug 27 06:57:47 AM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512462987 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3512462987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.3376253474
Short name T680
Test name
Test status
Simulation time 19842941451 ps
CPU time 161.59 seconds
Started Aug 27 06:57:38 AM UTC 24
Finished Aug 27 07:00:22 AM UTC 24
Peak memory 295580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3376253474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 27.lc_ctrl_stress_all.3376253474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4251202026
Short name T587
Test name
Test status
Simulation time 14812978 ps
CPU time 1.35 seconds
Started Aug 27 06:57:34 AM UTC 24
Finished Aug 27 06:57:36 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251202026 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_volatile_unlock_smoke.4251202026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.4125598596
Short name T228
Test name
Test status
Simulation time 68979533 ps
CPU time 1.02 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:57:48 AM UTC 24
Peak memory 218756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125598596 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.4125598596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.703522736
Short name T616
Test name
Test status
Simulation time 418048638 ps
CPU time 9.98 seconds
Started Aug 27 06:57:43 AM UTC 24
Finished Aug 27 06:57:54 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703522736 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.703522736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3982069625
Short name T639
Test name
Test status
Simulation time 700513856 ps
CPU time 20.6 seconds
Started Aug 27 06:57:43 AM UTC 24
Finished Aug 27 06:58:05 AM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982069625 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_acce
ss.3982069625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1451658894
Short name T225
Test name
Test status
Simulation time 232358276 ps
CPU time 3.15 seconds
Started Aug 27 06:57:43 AM UTC 24
Finished Aug 27 06:57:47 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451658894 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1451658894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.1635979162
Short name T631
Test name
Test status
Simulation time 2923332598 ps
CPU time 17.86 seconds
Started Aug 27 06:57:43 AM UTC 24
Finished Aug 27 06:58:02 AM UTC 24
Peak memory 237948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635979162 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1635979162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.1975555829
Short name T626
Test name
Test status
Simulation time 1617511625 ps
CPU time 13.56 seconds
Started Aug 27 06:57:44 AM UTC 24
Finished Aug 27 06:57:59 AM UTC 24
Peak memory 238220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975555829 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_
token_digest.1975555829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.1441983882
Short name T615
Test name
Test status
Simulation time 1495110117 ps
CPU time 7.97 seconds
Started Aug 27 06:57:44 AM UTC 24
Finished Aug 27 06:57:53 AM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441983882 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_tok
en_mux.1441983882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1034946626
Short name T620
Test name
Test status
Simulation time 521990224 ps
CPU time 10.79 seconds
Started Aug 27 06:57:43 AM UTC 24
Finished Aug 27 06:57:55 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034946626 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1034946626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.552721470
Short name T93
Test name
Test status
Simulation time 36172096 ps
CPU time 2.78 seconds
Started Aug 27 06:57:39 AM UTC 24
Finished Aug 27 06:57:43 AM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552721470 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.552721470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1144492753
Short name T216
Test name
Test status
Simulation time 289064286 ps
CPU time 25.07 seconds
Started Aug 27 06:57:40 AM UTC 24
Finished Aug 27 06:58:07 AM UTC 24
Peak memory 258804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144492753 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.1144492753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.4235255491
Short name T220
Test name
Test status
Simulation time 70154386 ps
CPU time 3.4 seconds
Started Aug 27 06:57:41 AM UTC 24
Finished Aug 27 06:57:46 AM UTC 24
Peak memory 234764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235255491 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4235255491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.3883984896
Short name T816
Test name
Test status
Simulation time 4165358026 ps
CPU time 114.82 seconds
Started Aug 27 06:57:44 AM UTC 24
Finished Aug 27 06:59:41 AM UTC 24
Peak memory 283392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3883984896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 28.lc_ctrl_stress_all.3883984896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3711003863
Short name T730
Test name
Test status
Simulation time 25256750264 ps
CPU time 64.98 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:58:53 AM UTC 24
Peak memory 281444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711003863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3711003863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3324345414
Short name T598
Test name
Test status
Simulation time 66400118 ps
CPU time 1.26 seconds
Started Aug 27 06:57:39 AM UTC 24
Finished Aug 27 06:57:41 AM UTC 24
Peak memory 229032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324345414 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_volatile_unlock_smoke.3324345414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3502283038
Short name T612
Test name
Test status
Simulation time 75489930 ps
CPU time 1.3 seconds
Started Aug 27 06:57:49 AM UTC 24
Finished Aug 27 06:57:51 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502283038 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3502283038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3890486143
Short name T629
Test name
Test status
Simulation time 309257375 ps
CPU time 11.77 seconds
Started Aug 27 06:57:48 AM UTC 24
Finished Aug 27 06:58:02 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890486143 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3890486143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.1519076245
Short name T214
Test name
Test status
Simulation time 1173990797 ps
CPU time 16.33 seconds
Started Aug 27 06:57:48 AM UTC 24
Finished Aug 27 06:58:06 AM UTC 24
Peak memory 229892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519076245 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_acce
ss.1519076245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1761416773
Short name T618
Test name
Test status
Simulation time 59895065 ps
CPU time 4.16 seconds
Started Aug 27 06:57:48 AM UTC 24
Finished Aug 27 06:57:54 AM UTC 24
Peak memory 231944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761416773 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1761416773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.1105052791
Short name T217
Test name
Test status
Simulation time 546175506 ps
CPU time 17.02 seconds
Started Aug 27 06:57:48 AM UTC 24
Finished Aug 27 06:58:07 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105052791 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1105052791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.2572622766
Short name T633
Test name
Test status
Simulation time 272405612 ps
CPU time 12.96 seconds
Started Aug 27 06:57:49 AM UTC 24
Finished Aug 27 06:58:03 AM UTC 24
Peak memory 237760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572622766 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_
token_digest.2572622766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.2471034122
Short name T637
Test name
Test status
Simulation time 633803032 ps
CPU time 13.83 seconds
Started Aug 27 06:57:49 AM UTC 24
Finished Aug 27 06:58:04 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471034122 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_tok
en_mux.2471034122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.83723949
Short name T625
Test name
Test status
Simulation time 2511175935 ps
CPU time 8.96 seconds
Started Aug 27 06:57:48 AM UTC 24
Finished Aug 27 06:57:59 AM UTC 24
Peak memory 232400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83723949 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.83723949
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.2648160708
Short name T609
Test name
Test status
Simulation time 46589362 ps
CPU time 2.68 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:57:50 AM UTC 24
Peak memory 225456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648160708 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2648160708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.396031970
Short name T649
Test name
Test status
Simulation time 1133853419 ps
CPU time 25.13 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:58:12 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396031970 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.396031970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3580583953
Short name T617
Test name
Test status
Simulation time 207219811 ps
CPU time 6.61 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:57:54 AM UTC 24
Peak memory 262656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580583953 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.3580583953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.1994059439
Short name T761
Test name
Test status
Simulation time 2832964931 ps
CPU time 76.36 seconds
Started Aug 27 06:57:49 AM UTC 24
Finished Aug 27 06:59:07 AM UTC 24
Peak memory 285364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1994059439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 29.lc_ctrl_stress_all.1994059439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.4283421916
Short name T167
Test name
Test status
Simulation time 12655666545 ps
CPU time 57.25 seconds
Started Aug 27 06:57:49 AM UTC 24
Finished Aug 27 06:58:48 AM UTC 24
Peak memory 281700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283421916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.4283421916
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.2360734290
Short name T607
Test name
Test status
Simulation time 14909282 ps
CPU time 1.35 seconds
Started Aug 27 06:57:46 AM UTC 24
Finished Aug 27 06:57:48 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360734290 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_volatile_unlock_smoke.2360734290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1751795559
Short name T271
Test name
Test status
Simulation time 20053250 ps
CPU time 1.48 seconds
Started Aug 27 06:54:28 AM UTC 24
Finished Aug 27 06:54:31 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751795559 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1751795559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3425180089
Short name T232
Test name
Test status
Simulation time 13939223 ps
CPU time 1.25 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:21 AM UTC 24
Peak memory 217236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425180089 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3425180089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.2434159019
Short name T277
Test name
Test status
Simulation time 818165842 ps
CPU time 16.68 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:37 AM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2434159019 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.2434159019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.426956194
Short name T11
Test name
Test status
Simulation time 1392954727 ps
CPU time 6.97 seconds
Started Aug 27 06:54:22 AM UTC 24
Finished Aug 27 06:54:31 AM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426956194 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.426956194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.3149838600
Short name T317
Test name
Test status
Simulation time 11357355079 ps
CPU time 43.62 seconds
Started Aug 27 06:54:21 AM UTC 24
Finished Aug 27 06:55:06 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149838600
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_errors.3149838600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.2718920980
Short name T81
Test name
Test status
Simulation time 804041446 ps
CPU time 11.97 seconds
Started Aug 27 06:54:23 AM UTC 24
Finished Aug 27 06:54:36 AM UTC 24
Peak memory 229916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718920980 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_pri
ority.2718920980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.1676355881
Short name T42
Test name
Test status
Simulation time 102817403 ps
CPU time 4.38 seconds
Started Aug 27 06:54:20 AM UTC 24
Finished Aug 27 06:54:26 AM UTC 24
Peak memory 234164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676355881
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_jtag_prog_failure.1676355881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2120006908
Short name T83
Test name
Test status
Simulation time 529260015 ps
CPU time 10.84 seconds
Started Aug 27 06:54:24 AM UTC 24
Finished Aug 27 06:54:36 AM UTC 24
Peak memory 229872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120006908
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l
c_ctrl_jtag_regwen_during_op.2120006908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.4095374380
Short name T98
Test name
Test status
Simulation time 479480567 ps
CPU time 8.03 seconds
Started Aug 27 06:54:20 AM UTC 24
Finished Aug 27 06:54:29 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095374380
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_smoke.4095374380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.3127652697
Short name T343
Test name
Test status
Simulation time 4878928431 ps
CPU time 62.85 seconds
Started Aug 27 06:54:20 AM UTC 24
Finished Aug 27 06:55:25 AM UTC 24
Peak memory 289444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127652697
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_c
trl_jtag_state_failure.3127652697
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1518688397
Short name T266
Test name
Test status
Simulation time 533240520 ps
CPU time 18.49 seconds
Started Aug 27 06:54:20 AM UTC 24
Finished Aug 27 06:54:40 AM UTC 24
Peak memory 262952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518688397
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l
c_ctrl_jtag_state_post_trans.1518688397
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.2737728717
Short name T40
Test name
Test status
Simulation time 68899574 ps
CPU time 4.46 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:24 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737728717 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2737728717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.1399147365
Short name T233
Test name
Test status
Simulation time 567290400 ps
CPU time 18.12 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:38 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399147365 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1399147365
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.107504529
Short name T119
Test name
Test status
Simulation time 444833873 ps
CPU time 35.04 seconds
Started Aug 27 06:54:27 AM UTC 24
Finished Aug 27 06:55:04 AM UTC 24
Peak memory 289856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=107504529 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.107504529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.1794792688
Short name T73
Test name
Test status
Simulation time 1530501672 ps
CPU time 9.32 seconds
Started Aug 27 06:54:25 AM UTC 24
Finished Aug 27 06:54:35 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794792688 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1794792688
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.254273246
Short name T278
Test name
Test status
Simulation time 923481601 ps
CPU time 9.94 seconds
Started Aug 27 06:54:26 AM UTC 24
Finished Aug 27 06:54:37 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254273246 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_to
ken_digest.254273246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.4024304269
Short name T279
Test name
Test status
Simulation time 3501521688 ps
CPU time 10.4 seconds
Started Aug 27 06:54:26 AM UTC 24
Finished Aug 27 06:54:38 AM UTC 24
Peak memory 232316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024304269 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_toke
n_mux.4024304269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.3627254161
Short name T65
Test name
Test status
Simulation time 981879841 ps
CPU time 9.38 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:29 AM UTC 24
Peak memory 236916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627254161 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3627254161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.438358211
Short name T231
Test name
Test status
Simulation time 29031403 ps
CPU time 2.65 seconds
Started Aug 27 06:54:17 AM UTC 24
Finished Aug 27 06:54:21 AM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438358211 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.438358211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.3326844030
Short name T45
Test name
Test status
Simulation time 101146891 ps
CPU time 7.62 seconds
Started Aug 27 06:54:19 AM UTC 24
Finished Aug 27 06:54:27 AM UTC 24
Peak memory 260604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326844030 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3326844030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2564731784
Short name T107
Test name
Test status
Simulation time 4151595459 ps
CPU time 27.14 seconds
Started Aug 27 06:54:27 AM UTC 24
Finished Aug 27 06:54:56 AM UTC 24
Peak memory 238232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2564731784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_stress_all.2564731784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.488923829
Short name T230
Test name
Test status
Simulation time 19290243 ps
CPU time 1.44 seconds
Started Aug 27 06:54:17 AM UTC 24
Finished Aug 27 06:54:20 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488923829 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
.lc_ctrl_volatile_unlock_smoke.488923829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2904765564
Short name T622
Test name
Test status
Simulation time 34971065 ps
CPU time 0.9 seconds
Started Aug 27 06:57:55 AM UTC 24
Finished Aug 27 06:57:57 AM UTC 24
Peak memory 218660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904765564 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2904765564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.2095985445
Short name T212
Test name
Test status
Simulation time 337086622 ps
CPU time 12.84 seconds
Started Aug 27 06:57:52 AM UTC 24
Finished Aug 27 06:58:06 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095985445 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2095985445
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.2650914714
Short name T638
Test name
Test status
Simulation time 633985834 ps
CPU time 9.07 seconds
Started Aug 27 06:57:54 AM UTC 24
Finished Aug 27 06:58:05 AM UTC 24
Peak memory 229908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650914714 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_acce
ss.2650914714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.927290936
Short name T624
Test name
Test status
Simulation time 102526427 ps
CPU time 5.13 seconds
Started Aug 27 06:57:51 AM UTC 24
Finished Aug 27 06:57:58 AM UTC 24
Peak memory 236268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927290936 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.927290936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1431121221
Short name T653
Test name
Test status
Simulation time 1489519045 ps
CPU time 21.38 seconds
Started Aug 27 06:57:54 AM UTC 24
Finished Aug 27 06:58:17 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431121221 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1431121221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.747926743
Short name T219
Test name
Test status
Simulation time 304206687 ps
CPU time 12.08 seconds
Started Aug 27 06:57:55 AM UTC 24
Finished Aug 27 06:58:09 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747926743 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_t
oken_digest.747926743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2308957706
Short name T213
Test name
Test status
Simulation time 3033748741 ps
CPU time 9.34 seconds
Started Aug 27 06:57:55 AM UTC 24
Finished Aug 27 06:58:06 AM UTC 24
Peak memory 232228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308957706 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_tok
en_mux.2308957706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.1856309144
Short name T635
Test name
Test status
Simulation time 354150667 ps
CPU time 9.43 seconds
Started Aug 27 06:57:53 AM UTC 24
Finished Aug 27 06:58:04 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856309144 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1856309144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.3837895428
Short name T614
Test name
Test status
Simulation time 196364112 ps
CPU time 1.59 seconds
Started Aug 27 06:57:50 AM UTC 24
Finished Aug 27 06:57:53 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837895428 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3837895428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.3349518565
Short name T643
Test name
Test status
Simulation time 427023663 ps
CPU time 19.53 seconds
Started Aug 27 06:57:50 AM UTC 24
Finished Aug 27 06:58:11 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349518565 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3349518565
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.3338611117
Short name T634
Test name
Test status
Simulation time 198989616 ps
CPU time 10.29 seconds
Started Aug 27 06:57:51 AM UTC 24
Finished Aug 27 06:58:03 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338611117 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3338611117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.569006367
Short name T807
Test name
Test status
Simulation time 6176751625 ps
CPU time 99.07 seconds
Started Aug 27 06:57:55 AM UTC 24
Finished Aug 27 06:59:36 AM UTC 24
Peak memory 262804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=569006367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 30.lc_ctrl_stress_all.569006367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.603051396
Short name T855
Test name
Test status
Simulation time 5854348758 ps
CPU time 126.45 seconds
Started Aug 27 06:57:55 AM UTC 24
Finished Aug 27 07:00:04 AM UTC 24
Peak memory 295704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603051396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.603051396
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.2979994999
Short name T613
Test name
Test status
Simulation time 54872485 ps
CPU time 1.44 seconds
Started Aug 27 06:57:50 AM UTC 24
Finished Aug 27 06:57:53 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979994999 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_volatile_unlock_smoke.2979994999
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.3428619439
Short name T215
Test name
Test status
Simulation time 23791538 ps
CPU time 1.38 seconds
Started Aug 27 06:58:04 AM UTC 24
Finished Aug 27 06:58:06 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428619439 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3428619439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.3571882249
Short name T648
Test name
Test status
Simulation time 356636129 ps
CPU time 10.59 seconds
Started Aug 27 06:58:00 AM UTC 24
Finished Aug 27 06:58:12 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571882249 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3571882249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1501631234
Short name T641
Test name
Test status
Simulation time 3026706544 ps
CPU time 7.38 seconds
Started Aug 27 06:58:00 AM UTC 24
Finished Aug 27 06:58:09 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501631234 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_acce
ss.1501631234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3054702042
Short name T632
Test name
Test status
Simulation time 31954592 ps
CPU time 2.61 seconds
Started Aug 27 06:57:59 AM UTC 24
Finished Aug 27 06:58:03 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054702042 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3054702042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.2542037408
Short name T647
Test name
Test status
Simulation time 328813440 ps
CPU time 9.08 seconds
Started Aug 27 06:58:01 AM UTC 24
Finished Aug 27 06:58:12 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542037408 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2542037408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1144774053
Short name T603
Test name
Test status
Simulation time 264808206 ps
CPU time 10.53 seconds
Started Aug 27 06:58:03 AM UTC 24
Finished Aug 27 06:58:14 AM UTC 24
Peak memory 232368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144774053 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_
token_digest.1144774053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.275205691
Short name T644
Test name
Test status
Simulation time 3003324134 ps
CPU time 7.13 seconds
Started Aug 27 06:58:03 AM UTC 24
Finished Aug 27 06:58:11 AM UTC 24
Peak memory 232156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275205691 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_toke
n_mux.275205691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.303505725
Short name T606
Test name
Test status
Simulation time 294290567 ps
CPU time 12.68 seconds
Started Aug 27 06:58:00 AM UTC 24
Finished Aug 27 06:58:14 AM UTC 24
Peak memory 237972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303505725 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.303505725
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.4188325962
Short name T630
Test name
Test status
Simulation time 422847962 ps
CPU time 3.68 seconds
Started Aug 27 06:57:57 AM UTC 24
Finished Aug 27 06:58:02 AM UTC 24
Peak memory 230192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188325962 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.4188325962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1087096000
Short name T668
Test name
Test status
Simulation time 853330652 ps
CPU time 24.61 seconds
Started Aug 27 06:57:58 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 258644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087096000 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1087096000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1793049440
Short name T636
Test name
Test status
Simulation time 105143657 ps
CPU time 3.94 seconds
Started Aug 27 06:57:59 AM UTC 24
Finished Aug 27 06:58:04 AM UTC 24
Peak memory 234496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793049440 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1793049440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.507009339
Short name T875
Test name
Test status
Simulation time 46359732892 ps
CPU time 312 seconds
Started Aug 27 06:58:03 AM UTC 24
Finished Aug 27 07:03:19 AM UTC 24
Peak memory 262916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=507009339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 31.lc_ctrl_stress_all.507009339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3156638795
Short name T627
Test name
Test status
Simulation time 51913061 ps
CPU time 1.06 seconds
Started Aug 27 06:57:57 AM UTC 24
Finished Aug 27 06:57:59 AM UTC 24
Peak memory 229032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3156638795 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_volatile_unlock_smoke.3156638795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.3568182997
Short name T645
Test name
Test status
Simulation time 106579584 ps
CPU time 1.38 seconds
Started Aug 27 06:58:09 AM UTC 24
Finished Aug 27 06:58:11 AM UTC 24
Peak memory 219052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568182997 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3568182997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1593299947
Short name T664
Test name
Test status
Simulation time 2126773388 ps
CPU time 13.93 seconds
Started Aug 27 06:58:06 AM UTC 24
Finished Aug 27 06:58:21 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593299947 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1593299947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.1864636663
Short name T652
Test name
Test status
Simulation time 3031707358 ps
CPU time 7.96 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:58:17 AM UTC 24
Peak memory 229920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1864636663 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_acce
ss.1864636663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.180384124
Short name T642
Test name
Test status
Simulation time 98313675 ps
CPU time 3.45 seconds
Started Aug 27 06:58:06 AM UTC 24
Finished Aug 27 06:58:10 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180384124 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.180384124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.718658423
Short name T657
Test name
Test status
Simulation time 1215532228 ps
CPU time 9.09 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:58:18 AM UTC 24
Peak memory 227332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718658423 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.718658423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2192995709
Short name T679
Test name
Test status
Simulation time 478381912 ps
CPU time 17.78 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:58:27 AM UTC 24
Peak memory 237788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192995709 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_
token_digest.2192995709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.4229105423
Short name T675
Test name
Test status
Simulation time 3729522736 ps
CPU time 16.27 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:58:25 AM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229105423 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_tok
en_mux.4229105423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3444611225
Short name T650
Test name
Test status
Simulation time 791748833 ps
CPU time 6.5 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:58:15 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3444611225 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3444611225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.2251467826
Short name T94
Test name
Test status
Simulation time 39833805 ps
CPU time 1.8 seconds
Started Aug 27 06:58:04 AM UTC 24
Finished Aug 27 06:58:07 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251467826 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2251467826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3300435198
Short name T692
Test name
Test status
Simulation time 1058867461 ps
CPU time 26.05 seconds
Started Aug 27 06:58:05 AM UTC 24
Finished Aug 27 06:58:33 AM UTC 24
Peak memory 262992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300435198 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3300435198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.2845327597
Short name T651
Test name
Test status
Simulation time 43658913 ps
CPU time 8.57 seconds
Started Aug 27 06:58:06 AM UTC 24
Finished Aug 27 06:58:16 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845327597 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2845327597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.1800399947
Short name T745
Test name
Test status
Simulation time 4355412563 ps
CPU time 50.11 seconds
Started Aug 27 06:58:07 AM UTC 24
Finished Aug 27 06:59:00 AM UTC 24
Peak memory 258740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1800399947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 32.lc_ctrl_stress_all.1800399947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1790907582
Short name T169
Test name
Test status
Simulation time 1847553875 ps
CPU time 14.43 seconds
Started Aug 27 06:58:08 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 240604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790907582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1790907582
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.4071521227
Short name T218
Test name
Test status
Simulation time 50354972 ps
CPU time 1.22 seconds
Started Aug 27 06:58:05 AM UTC 24
Finished Aug 27 06:58:08 AM UTC 24
Peak memory 220648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071521227 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_volatile_unlock_smoke.4071521227
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2696788421
Short name T659
Test name
Test status
Simulation time 92225877 ps
CPU time 1.29 seconds
Started Aug 27 06:58:16 AM UTC 24
Finished Aug 27 06:58:18 AM UTC 24
Peak memory 218816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696788421 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2696788421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3656243407
Short name T673
Test name
Test status
Simulation time 1185420779 ps
CPU time 11.34 seconds
Started Aug 27 06:58:13 AM UTC 24
Finished Aug 27 06:58:25 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656243407 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3656243407
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3083209822
Short name T674
Test name
Test status
Simulation time 368463033 ps
CPU time 11.2 seconds
Started Aug 27 06:58:13 AM UTC 24
Finished Aug 27 06:58:25 AM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083209822 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_acce
ss.3083209822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.838513722
Short name T656
Test name
Test status
Simulation time 86094224 ps
CPU time 4.07 seconds
Started Aug 27 06:58:12 AM UTC 24
Finished Aug 27 06:58:18 AM UTC 24
Peak memory 232440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838513722 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.838513722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1095987610
Short name T666
Test name
Test status
Simulation time 200261094 ps
CPU time 9.16 seconds
Started Aug 27 06:58:13 AM UTC 24
Finished Aug 27 06:58:23 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095987610 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1095987610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.2734691561
Short name T677
Test name
Test status
Simulation time 626349696 ps
CPU time 10.75 seconds
Started Aug 27 06:58:14 AM UTC 24
Finished Aug 27 06:58:26 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734691561 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_
token_digest.2734691561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.390096951
Short name T681
Test name
Test status
Simulation time 313116187 ps
CPU time 12.41 seconds
Started Aug 27 06:58:14 AM UTC 24
Finished Aug 27 06:58:28 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390096951 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_toke
n_mux.390096951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.768192528
Short name T661
Test name
Test status
Simulation time 531421713 ps
CPU time 6.87 seconds
Started Aug 27 06:58:13 AM UTC 24
Finished Aug 27 06:58:21 AM UTC 24
Peak memory 232400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768192528 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.768192528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.1953707232
Short name T646
Test name
Test status
Simulation time 27499927 ps
CPU time 1.65 seconds
Started Aug 27 06:58:09 AM UTC 24
Finished Aug 27 06:58:12 AM UTC 24
Peak memory 224780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953707232 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1953707232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.3373427156
Short name T678
Test name
Test status
Simulation time 190788219 ps
CPU time 14.77 seconds
Started Aug 27 06:58:10 AM UTC 24
Finished Aug 27 06:58:26 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373427156 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3373427156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1085780019
Short name T665
Test name
Test status
Simulation time 74347296 ps
CPU time 9.16 seconds
Started Aug 27 06:58:11 AM UTC 24
Finished Aug 27 06:58:22 AM UTC 24
Peak memory 262752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085780019 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1085780019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.856084765
Short name T876
Test name
Test status
Simulation time 36416590134 ps
CPU time 404.77 seconds
Started Aug 27 06:58:14 AM UTC 24
Finished Aug 27 07:05:04 AM UTC 24
Peak memory 265040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=856084765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 33.lc_ctrl_stress_all.856084765
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.887469503
Short name T178
Test name
Test status
Simulation time 2254940047 ps
CPU time 47.94 seconds
Started Aug 27 06:58:14 AM UTC 24
Finished Aug 27 06:59:04 AM UTC 24
Peak memory 281636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887469503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.887469503
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2127395137
Short name T221
Test name
Test status
Simulation time 51076573 ps
CPU time 1.21 seconds
Started Aug 27 06:58:10 AM UTC 24
Finished Aug 27 06:58:13 AM UTC 24
Peak memory 222908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127395137 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_volatile_unlock_smoke.2127395137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3505384243
Short name T671
Test name
Test status
Simulation time 17689195 ps
CPU time 1.57 seconds
Started Aug 27 06:58:22 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 218884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505384243 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3505384243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.2631857223
Short name T683
Test name
Test status
Simulation time 470959012 ps
CPU time 9.45 seconds
Started Aug 27 06:58:18 AM UTC 24
Finished Aug 27 06:58:28 AM UTC 24
Peak memory 237900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631857223 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2631857223
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.1430285285
Short name T676
Test name
Test status
Simulation time 1712679909 ps
CPU time 5.77 seconds
Started Aug 27 06:58:19 AM UTC 24
Finished Aug 27 06:58:26 AM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430285285 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_acce
ss.1430285285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3491794287
Short name T669
Test name
Test status
Simulation time 80813510 ps
CPU time 5.35 seconds
Started Aug 27 06:58:17 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491794287 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3491794287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.226628000
Short name T697
Test name
Test status
Simulation time 1183455873 ps
CPU time 13.96 seconds
Started Aug 27 06:58:19 AM UTC 24
Finished Aug 27 06:58:34 AM UTC 24
Peak memory 237768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226628000 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.226628000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3622922402
Short name T700
Test name
Test status
Simulation time 390230626 ps
CPU time 14.41 seconds
Started Aug 27 06:58:19 AM UTC 24
Finished Aug 27 06:58:35 AM UTC 24
Peak memory 230200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622922402 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_
token_digest.3622922402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.1664185391
Short name T689
Test name
Test status
Simulation time 1167447486 ps
CPU time 11.07 seconds
Started Aug 27 06:58:19 AM UTC 24
Finished Aug 27 06:58:31 AM UTC 24
Peak memory 232428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664185391 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_tok
en_mux.1664185391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3695064172
Short name T690
Test name
Test status
Simulation time 365450431 ps
CPU time 13.31 seconds
Started Aug 27 06:58:18 AM UTC 24
Finished Aug 27 06:58:32 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695064172 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3695064172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.4229148300
Short name T662
Test name
Test status
Simulation time 186564216 ps
CPU time 3.94 seconds
Started Aug 27 06:58:16 AM UTC 24
Finished Aug 27 06:58:21 AM UTC 24
Peak memory 236000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229148300 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4229148300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1825746559
Short name T199
Test name
Test status
Simulation time 487747682 ps
CPU time 27.12 seconds
Started Aug 27 06:58:16 AM UTC 24
Finished Aug 27 06:58:44 AM UTC 24
Peak memory 263076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825746559 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1825746559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.2982727273
Short name T667
Test name
Test status
Simulation time 969724187 ps
CPU time 5.04 seconds
Started Aug 27 06:58:17 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 234496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2982727273 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2982727273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.2924590218
Short name T867
Test name
Test status
Simulation time 17201692078 ps
CPU time 158.99 seconds
Started Aug 27 06:58:19 AM UTC 24
Finished Aug 27 07:01:01 AM UTC 24
Peak memory 432884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2924590218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 34.lc_ctrl_stress_all.2924590218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1113663684
Short name T658
Test name
Test status
Simulation time 22388609 ps
CPU time 1.2 seconds
Started Aug 27 06:58:16 AM UTC 24
Finished Aug 27 06:58:18 AM UTC 24
Peak memory 217724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113663684 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_volatile_unlock_smoke.1113663684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3826730235
Short name T684
Test name
Test status
Simulation time 77322070 ps
CPU time 1.34 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:58:29 AM UTC 24
Peak memory 218756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826730235 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3826730235
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.907542198
Short name T197
Test name
Test status
Simulation time 2451719715 ps
CPU time 17.64 seconds
Started Aug 27 06:58:24 AM UTC 24
Finished Aug 27 06:58:43 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907542198 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.907542198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.2952754473
Short name T686
Test name
Test status
Simulation time 3660205705 ps
CPU time 3.85 seconds
Started Aug 27 06:58:25 AM UTC 24
Finished Aug 27 06:58:30 AM UTC 24
Peak memory 230184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952754473 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_acce
ss.2952754473
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1932501679
Short name T685
Test name
Test status
Simulation time 61820552 ps
CPU time 3.18 seconds
Started Aug 27 06:58:24 AM UTC 24
Finished Aug 27 06:58:29 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932501679 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1932501679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2571855234
Short name T707
Test name
Test status
Simulation time 1518300285 ps
CPU time 11.83 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:58:39 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571855234 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2571855234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2663545431
Short name T710
Test name
Test status
Simulation time 748426543 ps
CPU time 12.35 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:58:40 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663545431 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_
token_digest.2663545431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.19572798
Short name T701
Test name
Test status
Simulation time 262003874 ps
CPU time 8.87 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:58:36 AM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19572798 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token
_mux.19572798
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.3905276715
Short name T699
Test name
Test status
Simulation time 246733522 ps
CPU time 8.97 seconds
Started Aug 27 06:58:24 AM UTC 24
Finished Aug 27 06:58:35 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905276715 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3905276715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.422795921
Short name T672
Test name
Test status
Simulation time 41429330 ps
CPU time 1.9 seconds
Started Aug 27 06:58:22 AM UTC 24
Finished Aug 27 06:58:25 AM UTC 24
Peak memory 224772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422795921 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.422795921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2029696276
Short name T720
Test name
Test status
Simulation time 1203014127 ps
CPU time 26.17 seconds
Started Aug 27 06:58:23 AM UTC 24
Finished Aug 27 06:58:50 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029696276 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2029696276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.3168561066
Short name T695
Test name
Test status
Simulation time 165947187 ps
CPU time 8.12 seconds
Started Aug 27 06:58:24 AM UTC 24
Finished Aug 27 06:58:34 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168561066 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3168561066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1739561803
Short name T774
Test name
Test status
Simulation time 1757405736 ps
CPU time 46.55 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:59:14 AM UTC 24
Peak memory 238100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739561803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1739561803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.571736746
Short name T670
Test name
Test status
Simulation time 15465439 ps
CPU time 1.32 seconds
Started Aug 27 06:58:22 AM UTC 24
Finished Aug 27 06:58:24 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571736746 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
5.lc_ctrl_volatile_unlock_smoke.571736746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.1480819156
Short name T694
Test name
Test status
Simulation time 41514383 ps
CPU time 1.59 seconds
Started Aug 27 06:58:31 AM UTC 24
Finished Aug 27 06:58:34 AM UTC 24
Peak memory 218636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1480819156 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1480819156
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3821841702
Short name T703
Test name
Test status
Simulation time 478210149 ps
CPU time 17.25 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:46 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821841702 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3821841702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.834019942
Short name T693
Test name
Test status
Simulation time 107734981 ps
CPU time 2.58 seconds
Started Aug 27 06:58:30 AM UTC 24
Finished Aug 27 06:58:33 AM UTC 24
Peak memory 229688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834019942 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.834019942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.469159455
Short name T691
Test name
Test status
Simulation time 207207834 ps
CPU time 3.12 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:32 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469159455 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.469159455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1022349500
Short name T713
Test name
Test status
Simulation time 313436358 ps
CPU time 12.04 seconds
Started Aug 27 06:58:30 AM UTC 24
Finished Aug 27 06:58:43 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022349500 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1022349500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3972103894
Short name T714
Test name
Test status
Simulation time 786051938 ps
CPU time 12.12 seconds
Started Aug 27 06:58:30 AM UTC 24
Finished Aug 27 06:58:43 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972103894 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_
token_digest.3972103894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.821683051
Short name T712
Test name
Test status
Simulation time 295459002 ps
CPU time 10.52 seconds
Started Aug 27 06:58:30 AM UTC 24
Finished Aug 27 06:58:41 AM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821683051 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_toke
n_mux.821683051
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.1621607835
Short name T708
Test name
Test status
Simulation time 1028900888 ps
CPU time 9.98 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:39 AM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621607835 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1621607835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1631129674
Short name T688
Test name
Test status
Simulation time 264043314 ps
CPU time 2.97 seconds
Started Aug 27 06:58:26 AM UTC 24
Finished Aug 27 06:58:30 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631129674 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1631129674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2376923166
Short name T721
Test name
Test status
Simulation time 213911262 ps
CPU time 21.75 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:51 AM UTC 24
Peak memory 262648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376923166 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2376923166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.1000500166
Short name T709
Test name
Test status
Simulation time 71771512 ps
CPU time 10.26 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:39 AM UTC 24
Peak memory 262956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000500166 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1000500166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.1095207681
Short name T859
Test name
Test status
Simulation time 13202281486 ps
CPU time 115.11 seconds
Started Aug 27 06:58:30 AM UTC 24
Finished Aug 27 07:00:27 AM UTC 24
Peak memory 326580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1095207681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 36.lc_ctrl_stress_all.1095207681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.886175144
Short name T687
Test name
Test status
Simulation time 19688895 ps
CPU time 1.33 seconds
Started Aug 27 06:58:28 AM UTC 24
Finished Aug 27 06:58:30 AM UTC 24
Peak memory 222812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886175144 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_volatile_unlock_smoke.886175144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.2493957177
Short name T706
Test name
Test status
Simulation time 30812385 ps
CPU time 1.44 seconds
Started Aug 27 06:58:36 AM UTC 24
Finished Aug 27 06:58:39 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493957177 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2493957177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.532082736
Short name T718
Test name
Test status
Simulation time 548250787 ps
CPU time 13.49 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:49 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532082736 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.532082736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.94209061
Short name T702
Test name
Test status
Simulation time 1174696461 ps
CPU time 9.19 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:45 AM UTC 24
Peak memory 229904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94209061 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.94209061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.375166026
Short name T705
Test name
Test status
Simulation time 59718513 ps
CPU time 2.3 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:38 AM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375166026 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.375166026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.726193066
Short name T200
Test name
Test status
Simulation time 650739172 ps
CPU time 8.71 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:45 AM UTC 24
Peak memory 229692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726193066 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.726193066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.4032178112
Short name T198
Test name
Test status
Simulation time 572014136 ps
CPU time 10.83 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:47 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4032178112 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_
token_digest.4032178112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1616164789
Short name T655
Test name
Test status
Simulation time 261359936 ps
CPU time 11.33 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:47 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616164789 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_tok
en_mux.1616164789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.582572647
Short name T715
Test name
Test status
Simulation time 3432146373 ps
CPU time 11.99 seconds
Started Aug 27 06:58:35 AM UTC 24
Finished Aug 27 06:58:48 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582572647 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.582572647
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1733975389
Short name T696
Test name
Test status
Simulation time 25989565 ps
CPU time 1.98 seconds
Started Aug 27 06:58:31 AM UTC 24
Finished Aug 27 06:58:34 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733975389 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1733975389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2743024297
Short name T727
Test name
Test status
Simulation time 1584240434 ps
CPU time 17.56 seconds
Started Aug 27 06:58:33 AM UTC 24
Finished Aug 27 06:58:52 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2743024297 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2743024297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.2313960823
Short name T704
Test name
Test status
Simulation time 241590697 ps
CPU time 3.59 seconds
Started Aug 27 06:58:33 AM UTC 24
Finished Aug 27 06:58:38 AM UTC 24
Peak memory 236620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313960823 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2313960823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2001243672
Short name T123
Test name
Test status
Simulation time 57422317602 ps
CPU time 244.37 seconds
Started Aug 27 06:58:36 AM UTC 24
Finished Aug 27 07:02:44 AM UTC 24
Peak memory 262912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2001243672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 37.lc_ctrl_stress_all.2001243672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.188660234
Short name T866
Test name
Test status
Simulation time 6083772754 ps
CPU time 139.46 seconds
Started Aug 27 06:58:36 AM UTC 24
Finished Aug 27 07:00:58 AM UTC 24
Peak memory 285536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188660234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_
SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_u
nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.188660234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.163735628
Short name T698
Test name
Test status
Simulation time 12573532 ps
CPU time 1.11 seconds
Started Aug 27 06:58:32 AM UTC 24
Finished Aug 27 06:58:34 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163735628 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
7.lc_ctrl_volatile_unlock_smoke.163735628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1656165321
Short name T195
Test name
Test status
Simulation time 24454868 ps
CPU time 1.15 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:58:47 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656165321 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1656165321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1039445562
Short name T738
Test name
Test status
Simulation time 2164775308 ps
CPU time 15.72 seconds
Started Aug 27 06:58:41 AM UTC 24
Finished Aug 27 06:58:57 AM UTC 24
Peak memory 230272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039445562 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1039445562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.2456545640
Short name T722
Test name
Test status
Simulation time 3138952784 ps
CPU time 9.24 seconds
Started Aug 27 06:58:41 AM UTC 24
Finished Aug 27 06:58:51 AM UTC 24
Peak memory 229928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456545640 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_acce
ss.2456545640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3278658255
Short name T201
Test name
Test status
Simulation time 1313900244 ps
CPU time 3.51 seconds
Started Aug 27 06:58:40 AM UTC 24
Finished Aug 27 06:58:45 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278658255 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3278658255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.291535208
Short name T723
Test name
Test status
Simulation time 2341342768 ps
CPU time 9.47 seconds
Started Aug 27 06:58:41 AM UTC 24
Finished Aug 27 06:58:51 AM UTC 24
Peak memory 238212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291535208 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.291535208
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3991556762
Short name T744
Test name
Test status
Simulation time 510339876 ps
CPU time 16.35 seconds
Started Aug 27 06:58:42 AM UTC 24
Finished Aug 27 06:58:59 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991556762 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_
token_digest.3991556762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3151955089
Short name T731
Test name
Test status
Simulation time 426414890 ps
CPU time 10.12 seconds
Started Aug 27 06:58:42 AM UTC 24
Finished Aug 27 06:58:53 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151955089 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_tok
en_mux.3151955089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.3507783789
Short name T732
Test name
Test status
Simulation time 5261699735 ps
CPU time 13.09 seconds
Started Aug 27 06:58:41 AM UTC 24
Finished Aug 27 06:58:55 AM UTC 24
Peak memory 238032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507783789 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3507783789
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.609429416
Short name T196
Test name
Test status
Simulation time 355819215 ps
CPU time 3.46 seconds
Started Aug 27 06:58:39 AM UTC 24
Finished Aug 27 06:58:43 AM UTC 24
Peak memory 225756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609429416 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.609429416
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.3489482645
Short name T747
Test name
Test status
Simulation time 1823309014 ps
CPU time 21.22 seconds
Started Aug 27 06:58:39 AM UTC 24
Finished Aug 27 06:59:01 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489482645 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3489482645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3922633957
Short name T717
Test name
Test status
Simulation time 330316471 ps
CPU time 8.34 seconds
Started Aug 27 06:58:39 AM UTC 24
Finished Aug 27 06:58:48 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922633957 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3922633957
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.515732899
Short name T852
Test name
Test status
Simulation time 1800211172 ps
CPU time 74.38 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 07:00:01 AM UTC 24
Peak memory 281176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=515732899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 38.lc_ctrl_stress_all.515732899
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.4142384360
Short name T820
Test name
Test status
Simulation time 11006759932 ps
CPU time 91.78 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 07:00:19 AM UTC 24
Peak memory 281632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142384360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.4142384360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.234818213
Short name T711
Test name
Test status
Simulation time 16396248 ps
CPU time 1.28 seconds
Started Aug 27 06:58:39 AM UTC 24
Finished Aug 27 06:58:41 AM UTC 24
Peak memory 229168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234818213 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
8.lc_ctrl_volatile_unlock_smoke.234818213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1765977222
Short name T725
Test name
Test status
Simulation time 70518248 ps
CPU time 1.56 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:58:52 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765977222 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1765977222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.245719915
Short name T746
Test name
Test status
Simulation time 277994243 ps
CPU time 13.55 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:59:00 AM UTC 24
Peak memory 230204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245719915 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.245719915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.3911184315
Short name T735
Test name
Test status
Simulation time 444581499 ps
CPU time 7.57 seconds
Started Aug 27 06:58:47 AM UTC 24
Finished Aug 27 06:58:56 AM UTC 24
Peak memory 229904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911184315 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_acce
ss.3911184315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.2689668130
Short name T719
Test name
Test status
Simulation time 117972984 ps
CPU time 3.43 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:58:50 AM UTC 24
Peak memory 236360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689668130 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2689668130
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.3771212028
Short name T741
Test name
Test status
Simulation time 511667186 ps
CPU time 9.69 seconds
Started Aug 27 06:58:47 AM UTC 24
Finished Aug 27 06:58:58 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771212028 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3771212028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.500453059
Short name T740
Test name
Test status
Simulation time 2178593354 ps
CPU time 7.89 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:58:58 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500453059 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_t
oken_digest.500453059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.1022015548
Short name T751
Test name
Test status
Simulation time 649662477 ps
CPU time 15.95 seconds
Started Aug 27 06:58:47 AM UTC 24
Finished Aug 27 06:59:04 AM UTC 24
Peak memory 238024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022015548 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_tok
en_mux.1022015548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.4131528702
Short name T739
Test name
Test status
Simulation time 269402916 ps
CPU time 9.22 seconds
Started Aug 27 06:58:47 AM UTC 24
Finished Aug 27 06:58:57 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131528702 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.4131528702
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.1493255296
Short name T716
Test name
Test status
Simulation time 24440065 ps
CPU time 1.94 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:58:48 AM UTC 24
Peak memory 229056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493255296 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1493255296
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.971530398
Short name T776
Test name
Test status
Simulation time 536668786 ps
CPU time 28.14 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:59:15 AM UTC 24
Peak memory 262816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971530398 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.971530398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.710555112
Short name T729
Test name
Test status
Simulation time 75191054 ps
CPU time 6.17 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:58:53 AM UTC 24
Peak memory 262820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710555112 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.710555112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2657178585
Short name T863
Test name
Test status
Simulation time 13385729345 ps
CPU time 106.75 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 07:00:38 AM UTC 24
Peak memory 295568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2657178585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 39.lc_ctrl_stress_all.2657178585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.274740632
Short name T203
Test name
Test status
Simulation time 37272683 ps
CPU time 1.19 seconds
Started Aug 27 06:58:45 AM UTC 24
Finished Aug 27 06:58:48 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274740632 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3
9.lc_ctrl_volatile_unlock_smoke.274740632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.2006523461
Short name T286
Test name
Test status
Simulation time 23666072 ps
CPU time 1.71 seconds
Started Aug 27 06:54:38 AM UTC 24
Finished Aug 27 06:54:41 AM UTC 24
Peak memory 218628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006523461 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2006523461
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2852285126
Short name T272
Test name
Test status
Simulation time 27344853 ps
CPU time 1.18 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:33 AM UTC 24
Peak memory 219200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852285126 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2852285126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.63258377
Short name T283
Test name
Test status
Simulation time 376373972 ps
CPU time 8.95 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:40 AM UTC 24
Peak memory 232508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63258377 -assert nopostproc +UVM_TESTNAME=lc_ct
rl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.63258377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.552158873
Short name T12
Test name
Test status
Simulation time 1860119064 ps
CPU time 9.9 seconds
Started Aug 27 06:54:34 AM UTC 24
Finished Aug 27 06:54:45 AM UTC 24
Peak memory 229860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552158873 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.552158873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.1252835306
Short name T55
Test name
Test status
Simulation time 2150945657 ps
CPU time 33.88 seconds
Started Aug 27 06:54:34 AM UTC 24
Finished Aug 27 06:55:09 AM UTC 24
Peak memory 237848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252835306
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_errors.1252835306
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.449482469
Short name T280
Test name
Test status
Simulation time 191439690 ps
CPU time 3.98 seconds
Started Aug 27 06:54:34 AM UTC 24
Finished Aug 27 06:54:39 AM UTC 24
Peak memory 229980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449482469 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prio
rity.449482469
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.3422074069
Short name T284
Test name
Test status
Simulation time 292013615 ps
CPU time 7.16 seconds
Started Aug 27 06:54:32 AM UTC 24
Finished Aug 27 06:54:40 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422074069
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_jtag_prog_failure.3422074069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.655904153
Short name T316
Test name
Test status
Simulation time 4071320751 ps
CPU time 29.01 seconds
Started Aug 27 06:54:35 AM UTC 24
Finished Aug 27 06:55:06 AM UTC 24
Peak memory 229844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655904153
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc
_ctrl_jtag_regwen_during_op.655904153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.2146620973
Short name T88
Test name
Test status
Simulation time 1116564803 ps
CPU time 13.12 seconds
Started Aug 27 06:54:32 AM UTC 24
Finished Aug 27 06:54:46 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146620973
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_smoke.2146620973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.2750469926
Short name T360
Test name
Test status
Simulation time 4267573043 ps
CPU time 56.23 seconds
Started Aug 27 06:54:32 AM UTC 24
Finished Aug 27 06:55:30 AM UTC 24
Peak memory 260768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750469926
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_c
trl_jtag_state_failure.2750469926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.697936550
Short name T296
Test name
Test status
Simulation time 488925789 ps
CPU time 16.17 seconds
Started Aug 27 06:54:32 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 236480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697936550
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc
_ctrl_jtag_state_post_trans.697936550
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.499684585
Short name T275
Test name
Test status
Simulation time 44183180 ps
CPU time 2.83 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:34 AM UTC 24
Peak memory 232028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499684585 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.499684585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.4131006173
Short name T234
Test name
Test status
Simulation time 212142028 ps
CPU time 13.86 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:46 AM UTC 24
Peak memory 229932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131006173 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4131006173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.548673524
Short name T268
Test name
Test status
Simulation time 347079188 ps
CPU time 11.7 seconds
Started Aug 27 06:54:35 AM UTC 24
Finished Aug 27 06:54:48 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548673524 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.548673524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.347389979
Short name T293
Test name
Test status
Simulation time 864940864 ps
CPU time 7.7 seconds
Started Aug 27 06:54:36 AM UTC 24
Finished Aug 27 06:54:45 AM UTC 24
Peak memory 237804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347389979 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_to
ken_digest.347389979
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.1074379727
Short name T292
Test name
Test status
Simulation time 861362922 ps
CPU time 6.98 seconds
Started Aug 27 06:54:36 AM UTC 24
Finished Aug 27 06:54:45 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074379727 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_toke
n_mux.1074379727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3540067438
Short name T70
Test name
Test status
Simulation time 609837611 ps
CPU time 6.78 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:38 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540067438 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3540067438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.349824207
Short name T273
Test name
Test status
Simulation time 48600349 ps
CPU time 2.79 seconds
Started Aug 27 06:54:28 AM UTC 24
Finished Aug 27 06:54:33 AM UTC 24
Peak memory 229852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349824207 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.349824207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.888325763
Short name T310
Test name
Test status
Simulation time 337912256 ps
CPU time 28.73 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:55:00 AM UTC 24
Peak memory 262740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888325763 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.888325763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1929926632
Short name T276
Test name
Test status
Simulation time 92875607 ps
CPU time 4.45 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:36 AM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929926632 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1929926632
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3656702270
Short name T397
Test name
Test status
Simulation time 6456802131 ps
CPU time 74.81 seconds
Started Aug 27 06:54:36 AM UTC 24
Finished Aug 27 06:55:53 AM UTC 24
Peak memory 289504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3656702270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 4.lc_ctrl_stress_all.3656702270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2762503077
Short name T274
Test name
Test status
Simulation time 36906132 ps
CPU time 1.49 seconds
Started Aug 27 06:54:30 AM UTC 24
Finished Aug 27 06:54:33 AM UTC 24
Peak memory 223044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762503077 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_volatile_unlock_smoke.2762503077
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1510362078
Short name T734
Test name
Test status
Simulation time 23541915 ps
CPU time 1.15 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 06:58:56 AM UTC 24
Peak memory 216932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510362078 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1510362078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.105088088
Short name T760
Test name
Test status
Simulation time 1909897333 ps
CPU time 14.57 seconds
Started Aug 27 06:58:51 AM UTC 24
Finished Aug 27 06:59:06 AM UTC 24
Peak memory 232516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105088088 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.105088088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.3616555408
Short name T778
Test name
Test status
Simulation time 814693231 ps
CPU time 22.36 seconds
Started Aug 27 06:58:52 AM UTC 24
Finished Aug 27 06:59:16 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616555408 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_acce
ss.3616555408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2395657906
Short name T733
Test name
Test status
Simulation time 74050849 ps
CPU time 4.05 seconds
Started Aug 27 06:58:50 AM UTC 24
Finished Aug 27 06:58:56 AM UTC 24
Peak memory 236432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395657906 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2395657906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.3641130490
Short name T759
Test name
Test status
Simulation time 326096949 ps
CPU time 12.97 seconds
Started Aug 27 06:58:52 AM UTC 24
Finished Aug 27 06:59:06 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641130490 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3641130490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2063919746
Short name T766
Test name
Test status
Simulation time 349303572 ps
CPU time 15.47 seconds
Started Aug 27 06:58:53 AM UTC 24
Finished Aug 27 06:59:10 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063919746 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_
token_digest.2063919746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.956051251
Short name T754
Test name
Test status
Simulation time 249430076 ps
CPU time 11.54 seconds
Started Aug 27 06:58:52 AM UTC 24
Finished Aug 27 06:59:05 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956051251 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_toke
n_mux.956051251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3923643231
Short name T763
Test name
Test status
Simulation time 302183497 ps
CPU time 15.84 seconds
Started Aug 27 06:58:52 AM UTC 24
Finished Aug 27 06:59:09 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923643231 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3923643231
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.3931692848
Short name T726
Test name
Test status
Simulation time 18039227 ps
CPU time 1.73 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:58:52 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931692848 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3931692848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.911542095
Short name T770
Test name
Test status
Simulation time 634114702 ps
CPU time 21.7 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:59:12 AM UTC 24
Peak memory 262768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911542095 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.911542095
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.3523311978
Short name T742
Test name
Test status
Simulation time 67967481 ps
CPU time 7.93 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:58:58 AM UTC 24
Peak memory 260680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3523311978 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3523311978
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.358945670
Short name T872
Test name
Test status
Simulation time 6173532414 ps
CPU time 204.09 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 07:02:21 AM UTC 24
Peak memory 297972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=358945670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 40.lc_ctrl_stress_all.358945670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1995771527
Short name T724
Test name
Test status
Simulation time 19274759 ps
CPU time 1.4 seconds
Started Aug 27 06:58:49 AM UTC 24
Finished Aug 27 06:58:52 AM UTC 24
Peak memory 222860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995771527 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_volatile_unlock_smoke.1995771527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1477631928
Short name T748
Test name
Test status
Simulation time 33386647 ps
CPU time 1.35 seconds
Started Aug 27 06:58:59 AM UTC 24
Finished Aug 27 06:59:01 AM UTC 24
Peak memory 218992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477631928 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1477631928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3829729705
Short name T112
Test name
Test status
Simulation time 1651366232 ps
CPU time 22.83 seconds
Started Aug 27 06:58:56 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829729705 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3829729705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.563402089
Short name T755
Test name
Test status
Simulation time 1921295570 ps
CPU time 6.46 seconds
Started Aug 27 06:58:57 AM UTC 24
Finished Aug 27 06:59:05 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563402089 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.563402089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.3077193834
Short name T743
Test name
Test status
Simulation time 81501931 ps
CPU time 1.98 seconds
Started Aug 27 06:58:56 AM UTC 24
Finished Aug 27 06:58:59 AM UTC 24
Peak memory 230260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077193834 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.3077193834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3098089215
Short name T768
Test name
Test status
Simulation time 4041671775 ps
CPU time 12.91 seconds
Started Aug 27 06:58:57 AM UTC 24
Finished Aug 27 06:59:11 AM UTC 24
Peak memory 232492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098089215 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3098089215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.2189508893
Short name T764
Test name
Test status
Simulation time 410531421 ps
CPU time 9.17 seconds
Started Aug 27 06:58:59 AM UTC 24
Finished Aug 27 06:59:09 AM UTC 24
Peak memory 232244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189508893 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_
token_digest.2189508893
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.156880936
Short name T757
Test name
Test status
Simulation time 196479538 ps
CPU time 6.96 seconds
Started Aug 27 06:58:57 AM UTC 24
Finished Aug 27 06:59:05 AM UTC 24
Peak memory 232240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156880936 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_toke
n_mux.156880936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.622443271
Short name T749
Test name
Test status
Simulation time 759142400 ps
CPU time 5.47 seconds
Started Aug 27 06:58:56 AM UTC 24
Finished Aug 27 06:59:03 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622443271 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.622443271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.210782739
Short name T737
Test name
Test status
Simulation time 18559750 ps
CPU time 1.84 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 06:58:56 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210782739 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.210782739
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2965931539
Short name T753
Test name
Test status
Simulation time 296874579 ps
CPU time 27.91 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 06:59:23 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965931539 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2965931539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.634402539
Short name T752
Test name
Test status
Simulation time 82781857 ps
CPU time 9.56 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 06:59:04 AM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634402539 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.634402539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2424280040
Short name T868
Test name
Test status
Simulation time 8188238271 ps
CPU time 132.9 seconds
Started Aug 27 06:58:59 AM UTC 24
Finished Aug 27 07:01:14 AM UTC 24
Peak memory 295572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2424280040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 41.lc_ctrl_stress_all.2424280040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3954012065
Short name T255
Test name
Test status
Simulation time 10532697940 ps
CPU time 39.18 seconds
Started Aug 27 06:58:59 AM UTC 24
Finished Aug 27 06:59:39 AM UTC 24
Peak memory 273252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954012065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3954012065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.4148905022
Short name T736
Test name
Test status
Simulation time 15687920 ps
CPU time 1.32 seconds
Started Aug 27 06:58:54 AM UTC 24
Finished Aug 27 06:58:56 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4148905022 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_volatile_unlock_smoke.4148905022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3744580224
Short name T762
Test name
Test status
Simulation time 37266406 ps
CPU time 1.92 seconds
Started Aug 27 06:59:06 AM UTC 24
Finished Aug 27 06:59:08 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744580224 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3744580224
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.233751206
Short name T772
Test name
Test status
Simulation time 1199952037 ps
CPU time 10.25 seconds
Started Aug 27 06:59:02 AM UTC 24
Finished Aug 27 06:59:13 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233751206 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.233751206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.2493626705
Short name T769
Test name
Test status
Simulation time 393407300 ps
CPU time 6.22 seconds
Started Aug 27 06:59:04 AM UTC 24
Finished Aug 27 06:59:11 AM UTC 24
Peak memory 229900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493626705 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_acce
ss.2493626705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.206486176
Short name T756
Test name
Test status
Simulation time 244158492 ps
CPU time 2.17 seconds
Started Aug 27 06:59:02 AM UTC 24
Finished Aug 27 06:59:05 AM UTC 24
Peak memory 234388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206486176 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.206486176
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.2506972863
Short name T111
Test name
Test status
Simulation time 405626447 ps
CPU time 14.73 seconds
Started Aug 27 06:59:04 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506972863 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2506972863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.276867571
Short name T777
Test name
Test status
Simulation time 694054355 ps
CPU time 8.33 seconds
Started Aug 27 06:59:05 AM UTC 24
Finished Aug 27 06:59:15 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276867571 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_t
oken_digest.276867571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1918815628
Short name T784
Test name
Test status
Simulation time 369349857 ps
CPU time 12.86 seconds
Started Aug 27 06:59:05 AM UTC 24
Finished Aug 27 06:59:19 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918815628 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok
en_mux.1918815628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3318917665
Short name T783
Test name
Test status
Simulation time 694488972 ps
CPU time 12.88 seconds
Started Aug 27 06:59:03 AM UTC 24
Finished Aug 27 06:59:17 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318917665 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3318917665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.1801051330
Short name T758
Test name
Test status
Simulation time 139111424 ps
CPU time 5.49 seconds
Started Aug 27 06:58:59 AM UTC 24
Finished Aug 27 06:59:06 AM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801051330 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1801051330
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.3628956303
Short name T798
Test name
Test status
Simulation time 507583257 ps
CPU time 29.65 seconds
Started Aug 27 06:59:00 AM UTC 24
Finished Aug 27 06:59:31 AM UTC 24
Peak memory 258916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628956303 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3628956303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2929561238
Short name T767
Test name
Test status
Simulation time 72382793 ps
CPU time 8.72 seconds
Started Aug 27 06:59:00 AM UTC 24
Finished Aug 27 06:59:10 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929561238 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2929561238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.1920339990
Short name T865
Test name
Test status
Simulation time 11483922409 ps
CPU time 102.94 seconds
Started Aug 27 06:59:05 AM UTC 24
Finished Aug 27 07:00:50 AM UTC 24
Peak memory 295564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1920339990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 42.lc_ctrl_stress_all.1920339990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2333174475
Short name T750
Test name
Test status
Simulation time 157636571 ps
CPU time 1.29 seconds
Started Aug 27 06:59:00 AM UTC 24
Finished Aug 27 06:59:03 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2333174475 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_volatile_unlock_smoke.2333174475
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2520758201
Short name T775
Test name
Test status
Simulation time 28932084 ps
CPU time 1.32 seconds
Started Aug 27 06:59:12 AM UTC 24
Finished Aug 27 06:59:15 AM UTC 24
Peak memory 216932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520758201 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2520758201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3814640633
Short name T110
Test name
Test status
Simulation time 1069750474 ps
CPU time 10.42 seconds
Started Aug 27 06:59:08 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 230132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814640633 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3814640633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.3867470643
Short name T782
Test name
Test status
Simulation time 1397043178 ps
CPU time 10.77 seconds
Started Aug 27 06:59:10 AM UTC 24
Finished Aug 27 06:59:22 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867470643 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_acce
ss.3867470643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.3355968366
Short name T773
Test name
Test status
Simulation time 117055233 ps
CPU time 5.4 seconds
Started Aug 27 06:59:07 AM UTC 24
Finished Aug 27 06:59:14 AM UTC 24
Peak memory 232328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355968366 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3355968366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.1161485758
Short name T787
Test name
Test status
Simulation time 1638135254 ps
CPU time 13.55 seconds
Started Aug 27 06:59:10 AM UTC 24
Finished Aug 27 06:59:25 AM UTC 24
Peak memory 237884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161485758 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1161485758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.2248429112
Short name T116
Test name
Test status
Simulation time 1226510331 ps
CPU time 11.07 seconds
Started Aug 27 06:59:11 AM UTC 24
Finished Aug 27 06:59:23 AM UTC 24
Peak memory 237728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248429112 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_
token_digest.2248429112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1300631258
Short name T785
Test name
Test status
Simulation time 469458676 ps
CPU time 10.03 seconds
Started Aug 27 06:59:11 AM UTC 24
Finished Aug 27 06:59:22 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300631258 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_tok
en_mux.1300631258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1211635840
Short name T728
Test name
Test status
Simulation time 3673584512 ps
CPU time 10.34 seconds
Started Aug 27 06:59:10 AM UTC 24
Finished Aug 27 06:59:21 AM UTC 24
Peak memory 232500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211635840 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1211635840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.2621696757
Short name T771
Test name
Test status
Simulation time 128959843 ps
CPU time 5.69 seconds
Started Aug 27 06:59:06 AM UTC 24
Finished Aug 27 06:59:12 AM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621696757 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2621696757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.566102335
Short name T800
Test name
Test status
Simulation time 703006002 ps
CPU time 23.44 seconds
Started Aug 27 06:59:07 AM UTC 24
Finished Aug 27 06:59:32 AM UTC 24
Peak memory 263008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566102335 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.566102335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1257664630
Short name T781
Test name
Test status
Simulation time 61009926 ps
CPU time 8.67 seconds
Started Aug 27 06:59:07 AM UTC 24
Finished Aug 27 06:59:17 AM UTC 24
Peak memory 260620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257664630 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1257664630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1828121500
Short name T873
Test name
Test status
Simulation time 42896907919 ps
CPU time 201.67 seconds
Started Aug 27 06:59:11 AM UTC 24
Finished Aug 27 07:02:36 AM UTC 24
Peak memory 289376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1828121500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 43.lc_ctrl_stress_all.1828121500
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.309451971
Short name T765
Test name
Test status
Simulation time 13557500 ps
CPU time 1.36 seconds
Started Aug 27 06:59:07 AM UTC 24
Finished Aug 27 06:59:09 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309451971 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.lc_ctrl_volatile_unlock_smoke.309451971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.110680756
Short name T114
Test name
Test status
Simulation time 58051968 ps
CPU time 1.63 seconds
Started Aug 27 06:59:18 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 218700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110680756 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.110680756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.2014477640
Short name T793
Test name
Test status
Simulation time 1601216304 ps
CPU time 11.12 seconds
Started Aug 27 06:59:16 AM UTC 24
Finished Aug 27 06:59:28 AM UTC 24
Peak memory 232152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014477640 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2014477640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1383354827
Short name T663
Test name
Test status
Simulation time 704316898 ps
CPU time 5.69 seconds
Started Aug 27 06:59:16 AM UTC 24
Finished Aug 27 06:59:23 AM UTC 24
Peak memory 229828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383354827 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_acce
ss.1383354827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.4051778289
Short name T113
Test name
Test status
Simulation time 765966583 ps
CPU time 4.51 seconds
Started Aug 27 06:59:15 AM UTC 24
Finished Aug 27 06:59:20 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051778289 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.4051778289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.2906382755
Short name T813
Test name
Test status
Simulation time 3772114054 ps
CPU time 22.23 seconds
Started Aug 27 06:59:16 AM UTC 24
Finished Aug 27 06:59:40 AM UTC 24
Peak memory 237948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906382755 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2906382755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.1943194851
Short name T792
Test name
Test status
Simulation time 229087893 ps
CPU time 9.17 seconds
Started Aug 27 06:59:18 AM UTC 24
Finished Aug 27 06:59:28 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943194851 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_
token_digest.1943194851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1374739216
Short name T789
Test name
Test status
Simulation time 2757960308 ps
CPU time 9.81 seconds
Started Aug 27 06:59:16 AM UTC 24
Finished Aug 27 06:59:27 AM UTC 24
Peak memory 232492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374739216 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_tok
en_mux.1374739216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.4268443827
Short name T786
Test name
Test status
Simulation time 246886928 ps
CPU time 7.22 seconds
Started Aug 27 06:59:16 AM UTC 24
Finished Aug 27 06:59:24 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268443827 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.4268443827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.2993432324
Short name T780
Test name
Test status
Simulation time 143122870 ps
CPU time 1.76 seconds
Started Aug 27 06:59:14 AM UTC 24
Finished Aug 27 06:59:16 AM UTC 24
Peak memory 224780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993432324 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2993432324
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.3592829443
Short name T825
Test name
Test status
Simulation time 375618464 ps
CPU time 30.5 seconds
Started Aug 27 06:59:14 AM UTC 24
Finished Aug 27 06:59:45 AM UTC 24
Peak memory 261028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3592829443 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3592829443
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.1034514211
Short name T115
Test name
Test status
Simulation time 271039735 ps
CPU time 7.19 seconds
Started Aug 27 06:59:15 AM UTC 24
Finished Aug 27 06:59:23 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034514211 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1034514211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.4071417766
Short name T860
Test name
Test status
Simulation time 3086370174 ps
CPU time 72.76 seconds
Started Aug 27 06:59:18 AM UTC 24
Finished Aug 27 07:00:32 AM UTC 24
Peak memory 262904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4071417766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 44.lc_ctrl_stress_all.4071417766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1514721756
Short name T779
Test name
Test status
Simulation time 20905570 ps
CPU time 1 seconds
Started Aug 27 06:59:14 AM UTC 24
Finished Aug 27 06:59:16 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514721756 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_volatile_unlock_smoke.1514721756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.4028636539
Short name T790
Test name
Test status
Simulation time 15714521 ps
CPU time 1.32 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:27 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028636539 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4028636539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.2039685515
Short name T799
Test name
Test status
Simulation time 1177671595 ps
CPU time 8.37 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:31 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039685515 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2039685515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.182256858
Short name T796
Test name
Test status
Simulation time 437252292 ps
CPU time 7.99 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:31 AM UTC 24
Peak memory 230168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182256858 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.182256858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.3922467336
Short name T788
Test name
Test status
Simulation time 353728555 ps
CPU time 3.88 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:27 AM UTC 24
Peak memory 232192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922467336 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3922467336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.488992712
Short name T797
Test name
Test status
Simulation time 2215433675 ps
CPU time 8.1 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:31 AM UTC 24
Peak memory 237940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488992712 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.488992712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1676142777
Short name T818
Test name
Test status
Simulation time 2072342640 ps
CPU time 17.38 seconds
Started Aug 27 06:59:23 AM UTC 24
Finished Aug 27 06:59:42 AM UTC 24
Peak memory 238156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676142777 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_
token_digest.1676142777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3545596889
Short name T803
Test name
Test status
Simulation time 184030166 ps
CPU time 8.01 seconds
Started Aug 27 06:59:23 AM UTC 24
Finished Aug 27 06:59:32 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3545596889 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_tok
en_mux.3545596889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2170872215
Short name T805
Test name
Test status
Simulation time 716514632 ps
CPU time 12.44 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:36 AM UTC 24
Peak memory 232160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170872215 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2170872215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1086370222
Short name T96
Test name
Test status
Simulation time 205594474 ps
CPU time 3.24 seconds
Started Aug 27 06:59:20 AM UTC 24
Finished Aug 27 06:59:24 AM UTC 24
Peak memory 225852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086370222 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1086370222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1101748715
Short name T841
Test name
Test status
Simulation time 977529629 ps
CPU time 28.97 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:52 AM UTC 24
Peak memory 258656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1101748715 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1101748715
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.3924574557
Short name T802
Test name
Test status
Simulation time 55344048 ps
CPU time 9.28 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:32 AM UTC 24
Peak memory 263012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924574557 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3924574557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3146775705
Short name T814
Test name
Test status
Simulation time 1307279400 ps
CPU time 49.94 seconds
Started Aug 27 06:59:23 AM UTC 24
Finished Aug 27 07:00:15 AM UTC 24
Peak memory 256620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3146775705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 45.lc_ctrl_stress_all.3146775705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3529926716
Short name T117
Test name
Test status
Simulation time 13305265 ps
CPU time 1.41 seconds
Started Aug 27 06:59:22 AM UTC 24
Finished Aug 27 06:59:24 AM UTC 24
Peak memory 220680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529926716 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_volatile_unlock_smoke.3529926716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.318785703
Short name T86
Test name
Test status
Simulation time 63492153 ps
CPU time 1.57 seconds
Started Aug 27 06:59:30 AM UTC 24
Finished Aug 27 06:59:33 AM UTC 24
Peak memory 218760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318785703 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.318785703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.1451153093
Short name T811
Test name
Test status
Simulation time 908971371 ps
CPU time 10.53 seconds
Started Aug 27 06:59:27 AM UTC 24
Finished Aug 27 06:59:39 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451153093 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.1451153093
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.3640384796
Short name T834
Test name
Test status
Simulation time 8324501475 ps
CPU time 20.61 seconds
Started Aug 27 06:59:28 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 230260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640384796 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_acce
ss.3640384796
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.2212608701
Short name T795
Test name
Test status
Simulation time 37893324 ps
CPU time 2.9 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:29 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212608701 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2212608701
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1086203290
Short name T826
Test name
Test status
Simulation time 824534729 ps
CPU time 15.53 seconds
Started Aug 27 06:59:29 AM UTC 24
Finished Aug 27 06:59:46 AM UTC 24
Peak memory 237880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086203290 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1086203290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1039280667
Short name T821
Test name
Test status
Simulation time 372146769 ps
CPU time 12.81 seconds
Started Aug 27 06:59:29 AM UTC 24
Finished Aug 27 06:59:43 AM UTC 24
Peak memory 237892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039280667 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_
token_digest.1039280667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.2240948001
Short name T810
Test name
Test status
Simulation time 219279879 ps
CPU time 8.31 seconds
Started Aug 27 06:59:29 AM UTC 24
Finished Aug 27 06:59:39 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240948001 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_tok
en_mux.2240948001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.1258729499
Short name T808
Test name
Test status
Simulation time 175068104 ps
CPU time 7.98 seconds
Started Aug 27 06:59:28 AM UTC 24
Finished Aug 27 06:59:37 AM UTC 24
Peak memory 232168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258729499 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1258729499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1330294374
Short name T794
Test name
Test status
Simulation time 82117812 ps
CPU time 2.36 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:29 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330294374 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1330294374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2707824112
Short name T843
Test name
Test status
Simulation time 338856468 ps
CPU time 26.08 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:53 AM UTC 24
Peak memory 263016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707824112 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2707824112
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.1507877044
Short name T804
Test name
Test status
Simulation time 252076420 ps
CPU time 6.11 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:33 AM UTC 24
Peak memory 234572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507877044 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1507877044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.2857039293
Short name T125
Test name
Test status
Simulation time 16201797189 ps
CPU time 82.25 seconds
Started Aug 27 06:59:29 AM UTC 24
Finished Aug 27 07:00:53 AM UTC 24
Peak memory 260784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2857039293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 46.lc_ctrl_stress_all.2857039293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3297060118
Short name T862
Test name
Test status
Simulation time 3745684484 ps
CPU time 64.88 seconds
Started Aug 27 06:59:29 AM UTC 24
Finished Aug 27 07:00:36 AM UTC 24
Peak memory 283412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297060118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3297060118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2403402993
Short name T791
Test name
Test status
Simulation time 12734102 ps
CPU time 1.39 seconds
Started Aug 27 06:59:25 AM UTC 24
Finished Aug 27 06:59:28 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403402993 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_volatile_unlock_smoke.2403402993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.137277207
Short name T812
Test name
Test status
Simulation time 18301047 ps
CPU time 0.98 seconds
Started Aug 27 06:59:37 AM UTC 24
Finished Aug 27 06:59:39 AM UTC 24
Peak memory 216936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137277207 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.137277207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.4284920533
Short name T823
Test name
Test status
Simulation time 391735548 ps
CPU time 9.89 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:45 AM UTC 24
Peak memory 231992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284920533 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.4284920533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.720113842
Short name T830
Test name
Test status
Simulation time 1835359776 ps
CPU time 12.12 seconds
Started Aug 27 06:59:35 AM UTC 24
Finished Aug 27 06:59:48 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=720113842 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.720113842
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.3482170735
Short name T809
Test name
Test status
Simulation time 54184347 ps
CPU time 2.93 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:37 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482170735 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3482170735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.3088008747
Short name T831
Test name
Test status
Simulation time 220787917 ps
CPU time 12.78 seconds
Started Aug 27 06:59:35 AM UTC 24
Finished Aug 27 06:59:49 AM UTC 24
Peak memory 227148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088008747 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3088008747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.1315727754
Short name T832
Test name
Test status
Simulation time 357374322 ps
CPU time 11.85 seconds
Started Aug 27 06:59:36 AM UTC 24
Finished Aug 27 06:59:49 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315727754 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_
token_digest.1315727754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1174830331
Short name T822
Test name
Test status
Simulation time 466966627 ps
CPU time 8.23 seconds
Started Aug 27 06:59:35 AM UTC 24
Finished Aug 27 06:59:44 AM UTC 24
Peak memory 232164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174830331 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok
en_mux.1174830331
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.818998238
Short name T827
Test name
Test status
Simulation time 1211947302 ps
CPU time 11.82 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:46 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818998238 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.818998238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.507749807
Short name T87
Test name
Test status
Simulation time 156101977 ps
CPU time 2.16 seconds
Started Aug 27 06:59:31 AM UTC 24
Finished Aug 27 06:59:35 AM UTC 24
Peak memory 229924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507749807 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.507749807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.605264152
Short name T124
Test name
Test status
Simulation time 420777743 ps
CPU time 19.39 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:54 AM UTC 24
Peak memory 262788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605264152 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.605264152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3514807904
Short name T819
Test name
Test status
Simulation time 336962593 ps
CPU time 8.18 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:43 AM UTC 24
Peak memory 262968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514807904 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3514807904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.101243120
Short name T874
Test name
Test status
Simulation time 11011704718 ps
CPU time 191.76 seconds
Started Aug 27 06:59:37 AM UTC 24
Finished Aug 27 07:02:52 AM UTC 24
Peak memory 262976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=101243120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 47.lc_ctrl_stress_all.101243120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.828455005
Short name T806
Test name
Test status
Simulation time 14155499 ps
CPU time 1.25 seconds
Started Aug 27 06:59:33 AM UTC 24
Finished Aug 27 06:59:36 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828455005 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
7.lc_ctrl_volatile_unlock_smoke.828455005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.3926843382
Short name T828
Test name
Test status
Simulation time 14237818 ps
CPU time 1.49 seconds
Started Aug 27 06:59:44 AM UTC 24
Finished Aug 27 06:59:47 AM UTC 24
Peak memory 218992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926843382 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3926843382
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.3295787309
Short name T838
Test name
Test status
Simulation time 220352442 ps
CPU time 8.01 seconds
Started Aug 27 06:59:41 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 232260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295787309 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3295787309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2801360295
Short name T837
Test name
Test status
Simulation time 1887301111 ps
CPU time 7.4 seconds
Started Aug 27 06:59:41 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801360295 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_acce
ss.2801360295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3162581028
Short name T824
Test name
Test status
Simulation time 266636974 ps
CPU time 4.2 seconds
Started Aug 27 06:59:40 AM UTC 24
Finished Aug 27 06:59:45 AM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162581028 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3162581028
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.3152438451
Short name T845
Test name
Test status
Simulation time 427801922 ps
CPU time 11.75 seconds
Started Aug 27 06:59:41 AM UTC 24
Finished Aug 27 06:59:54 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152438451 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3152438451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4116738344
Short name T851
Test name
Test status
Simulation time 692835741 ps
CPU time 16.74 seconds
Started Aug 27 06:59:43 AM UTC 24
Finished Aug 27 07:00:01 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116738344 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_
token_digest.4116738344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2872945849
Short name T844
Test name
Test status
Simulation time 822524706 ps
CPU time 9.41 seconds
Started Aug 27 06:59:43 AM UTC 24
Finished Aug 27 06:59:54 AM UTC 24
Peak memory 232236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872945849 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_tok
en_mux.2872945849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.422220922
Short name T833
Test name
Test status
Simulation time 170711993 ps
CPU time 6.57 seconds
Started Aug 27 06:59:41 AM UTC 24
Finished Aug 27 06:59:49 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422220922 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.422220922
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.3317387608
Short name T817
Test name
Test status
Simulation time 61841021 ps
CPU time 3.07 seconds
Started Aug 27 06:59:37 AM UTC 24
Finished Aug 27 06:59:41 AM UTC 24
Peak memory 229936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317387608 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3317387608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.1929729890
Short name T853
Test name
Test status
Simulation time 849376298 ps
CPU time 20.87 seconds
Started Aug 27 06:59:40 AM UTC 24
Finished Aug 27 07:00:02 AM UTC 24
Peak memory 258472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929729890 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1929729890
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2204119520
Short name T839
Test name
Test status
Simulation time 272210114 ps
CPU time 9.49 seconds
Started Aug 27 06:59:40 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 262436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204119520 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2204119520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.581969393
Short name T877
Test name
Test status
Simulation time 63017700146 ps
CPU time 496.91 seconds
Started Aug 27 06:59:43 AM UTC 24
Finished Aug 27 07:08:07 AM UTC 24
Peak memory 283404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=581969393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c
m_name 48.lc_ctrl_stress_all.581969393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3710039935
Short name T858
Test name
Test status
Simulation time 7416427566 ps
CPU time 35.98 seconds
Started Aug 27 06:59:43 AM UTC 24
Finished Aug 27 07:00:21 AM UTC 24
Peak memory 281592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710039935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3710039935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1411132458
Short name T815
Test name
Test status
Simulation time 18766651 ps
CPU time 1.29 seconds
Started Aug 27 06:59:39 AM UTC 24
Finished Aug 27 06:59:41 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411132458 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_volatile_unlock_smoke.1411132458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.1924741516
Short name T842
Test name
Test status
Simulation time 48648538 ps
CPU time 1.33 seconds
Started Aug 27 06:59:50 AM UTC 24
Finished Aug 27 06:59:52 AM UTC 24
Peak memory 218932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924741516 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1924741516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.3967350027
Short name T850
Test name
Test status
Simulation time 903515469 ps
CPU time 10.24 seconds
Started Aug 27 06:59:47 AM UTC 24
Finished Aug 27 06:59:59 AM UTC 24
Peak memory 232252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967350027 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3967350027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.882534364
Short name T847
Test name
Test status
Simulation time 730718312 ps
CPU time 9.08 seconds
Started Aug 27 06:59:47 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 230064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882534364 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.882534364
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.173220489
Short name T835
Test name
Test status
Simulation time 35642127 ps
CPU time 2.76 seconds
Started Aug 27 06:59:46 AM UTC 24
Finished Aug 27 06:59:50 AM UTC 24
Peak memory 232256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173220489 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.173220489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1412425872
Short name T854
Test name
Test status
Simulation time 348037934 ps
CPU time 13.8 seconds
Started Aug 27 06:59:48 AM UTC 24
Finished Aug 27 07:00:03 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1412425872 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1412425872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.1081540705
Short name T856
Test name
Test status
Simulation time 413389677 ps
CPU time 14.45 seconds
Started Aug 27 06:59:48 AM UTC 24
Finished Aug 27 07:00:04 AM UTC 24
Peak memory 238224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081540705 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_
token_digest.1081540705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.1872514452
Short name T849
Test name
Test status
Simulation time 563969237 ps
CPU time 8.63 seconds
Started Aug 27 06:59:48 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872514452 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_tok
en_mux.1872514452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.2800454259
Short name T848
Test name
Test status
Simulation time 276829796 ps
CPU time 9.57 seconds
Started Aug 27 06:59:47 AM UTC 24
Finished Aug 27 06:59:58 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800454259 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2800454259
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2504416092
Short name T840
Test name
Test status
Simulation time 94361216 ps
CPU time 5.53 seconds
Started Aug 27 06:59:44 AM UTC 24
Finished Aug 27 06:59:51 AM UTC 24
Peak memory 230132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2504416092 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2504416092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.3191794720
Short name T857
Test name
Test status
Simulation time 541660308 ps
CPU time 20.53 seconds
Started Aug 27 06:59:46 AM UTC 24
Finished Aug 27 07:00:08 AM UTC 24
Peak memory 262800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191794720 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3191794720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.3548493452
Short name T846
Test name
Test status
Simulation time 55228258 ps
CPU time 8.12 seconds
Started Aug 27 06:59:46 AM UTC 24
Finished Aug 27 06:59:55 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548493452 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3548493452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.1860962257
Short name T869
Test name
Test status
Simulation time 12115614293 ps
CPU time 87.18 seconds
Started Aug 27 06:59:50 AM UTC 24
Finished Aug 27 07:01:19 AM UTC 24
Peak memory 262884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1860962257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 49.lc_ctrl_stress_all.1860962257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.415323316
Short name T829
Test name
Test status
Simulation time 20239229 ps
CPU time 1.48 seconds
Started Aug 27 06:59:44 AM UTC 24
Finished Aug 27 06:59:47 AM UTC 24
Peak memory 222912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415323316 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
9.lc_ctrl_volatile_unlock_smoke.415323316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.325058658
Short name T297
Test name
Test status
Simulation time 18591800 ps
CPU time 1.59 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325058658 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.325058658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2155336165
Short name T289
Test name
Test status
Simulation time 20432778 ps
CPU time 1.27 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:54:43 AM UTC 24
Peak memory 217304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155336165 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2155336165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.1509956102
Short name T301
Test name
Test status
Simulation time 1710740758 ps
CPU time 11.48 seconds
Started Aug 27 06:54:40 AM UTC 24
Finished Aug 27 06:54:52 AM UTC 24
Peak memory 232436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509956102 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1509956102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.772154184
Short name T33
Test name
Test status
Simulation time 964931253 ps
CPU time 6.58 seconds
Started Aug 27 06:54:42 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 230100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772154184 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.772154184
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.3695948621
Short name T349
Test name
Test status
Simulation time 12872695813 ps
CPU time 42.47 seconds
Started Aug 27 06:54:42 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 238216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695948621
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_errors.3695948621
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3020969326
Short name T328
Test name
Test status
Simulation time 4374715023 ps
CPU time 26.19 seconds
Started Aug 27 06:54:44 AM UTC 24
Finished Aug 27 06:55:11 AM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020969326 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_pri
ority.3020969326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.333205150
Short name T294
Test name
Test status
Simulation time 71481444 ps
CPU time 3.07 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:54:45 AM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333205150
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_jtag_prog_failure.333205150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1528968076
Short name T311
Test name
Test status
Simulation time 922803620 ps
CPU time 15.56 seconds
Started Aug 27 06:54:44 AM UTC 24
Finished Aug 27 06:55:01 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528968076
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l
c_ctrl_jtag_regwen_during_op.1528968076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.2934222478
Short name T290
Test name
Test status
Simulation time 245671385 ps
CPU time 2.37 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:54:44 AM UTC 24
Peak memory 230052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934222478
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_smoke.2934222478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.4072488426
Short name T362
Test name
Test status
Simulation time 1874031061 ps
CPU time 47.98 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:55:31 AM UTC 24
Peak memory 283164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4072488426
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c
trl_jtag_state_failure.4072488426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.888367794
Short name T188
Test name
Test status
Simulation time 3372149284 ps
CPU time 31.53 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:55:14 AM UTC 24
Peak memory 262836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888367794
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc
_ctrl_jtag_state_post_trans.888367794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.165206253
Short name T291
Test name
Test status
Simulation time 349634305 ps
CPU time 4.04 seconds
Started Aug 27 06:54:40 AM UTC 24
Finished Aug 27 06:54:45 AM UTC 24
Peak memory 232412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165206253 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.165206253
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.2099932498
Short name T302
Test name
Test status
Simulation time 153150324 ps
CPU time 9.98 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:54:52 AM UTC 24
Peak memory 225832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099932498 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2099932498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.314115742
Short name T308
Test name
Test status
Simulation time 1659757962 ps
CPU time 12.29 seconds
Started Aug 27 06:54:45 AM UTC 24
Finished Aug 27 06:54:59 AM UTC 24
Peak memory 237972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314115742 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.314115742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.1334990044
Short name T304
Test name
Test status
Simulation time 749113533 ps
CPU time 8.27 seconds
Started Aug 27 06:54:45 AM UTC 24
Finished Aug 27 06:54:55 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334990044 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_t
oken_digest.1334990044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.2408343645
Short name T305
Test name
Test status
Simulation time 293363494 ps
CPU time 8.51 seconds
Started Aug 27 06:54:45 AM UTC 24
Finished Aug 27 06:54:55 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408343645 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_toke
n_mux.2408343645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2285618514
Short name T121
Test name
Test status
Simulation time 626381756 ps
CPU time 13.64 seconds
Started Aug 27 06:54:41 AM UTC 24
Finished Aug 27 06:54:56 AM UTC 24
Peak memory 237976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285618514 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2285618514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.2236607024
Short name T285
Test name
Test status
Simulation time 21097976 ps
CPU time 1.49 seconds
Started Aug 27 06:54:38 AM UTC 24
Finished Aug 27 06:54:41 AM UTC 24
Peak memory 222728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236607024 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2236607024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2058466722
Short name T295
Test name
Test status
Simulation time 636702009 ps
CPU time 8.76 seconds
Started Aug 27 06:54:39 AM UTC 24
Finished Aug 27 06:54:49 AM UTC 24
Peak memory 262744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058466722 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2058466722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.2733024504
Short name T353
Test name
Test status
Simulation time 825894212 ps
CPU time 39.96 seconds
Started Aug 27 06:54:45 AM UTC 24
Finished Aug 27 06:55:27 AM UTC 24
Peak memory 281184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2733024504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 5.lc_ctrl_stress_all.2733024504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1740269059
Short name T287
Test name
Test status
Simulation time 14363902 ps
CPU time 1.2 seconds
Started Aug 27 06:54:39 AM UTC 24
Finished Aug 27 06:54:42 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740269059 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_volatile_unlock_smoke.1740269059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.2123028393
Short name T306
Test name
Test status
Simulation time 15684912 ps
CPU time 1.06 seconds
Started Aug 27 06:54:56 AM UTC 24
Finished Aug 27 06:54:58 AM UTC 24
Peak memory 217604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123028393 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2123028393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.3867766119
Short name T54
Test name
Test status
Simulation time 2042630397 ps
CPU time 15.29 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:55:04 AM UTC 24
Peak memory 238220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867766119 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3867766119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1876880178
Short name T34
Test name
Test status
Simulation time 2929650913 ps
CPU time 14.73 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:07 AM UTC 24
Peak memory 229668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876880178 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1876880178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.1095074388
Short name T411
Test name
Test status
Simulation time 8725231525 ps
CPU time 70.72 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:56:04 AM UTC 24
Peak memory 237888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095074388
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_errors.1095074388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.2856213645
Short name T321
Test name
Test status
Simulation time 1687111529 ps
CPU time 15.21 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:07 AM UTC 24
Peak memory 229912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856213645 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_pri
ority.2856213645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2736591265
Short name T187
Test name
Test status
Simulation time 5246480929 ps
CPU time 21.63 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:14 AM UTC 24
Peak memory 237940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736591265
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_jtag_prog_failure.2736591265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2247373076
Short name T332
Test name
Test status
Simulation time 647247427 ps
CPU time 24.28 seconds
Started Aug 27 06:54:52 AM UTC 24
Finished Aug 27 06:55:18 AM UTC 24
Peak memory 230068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247373076
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_jtag_regwen_during_op.2247373076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.1211923263
Short name T312
Test name
Test status
Simulation time 1338575188 ps
CPU time 10.52 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:02 AM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211923263
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_smoke.1211923263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.2080883260
Short name T361
Test name
Test status
Simulation time 1934623836 ps
CPU time 37.76 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:30 AM UTC 24
Peak memory 262880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080883260
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_c
trl_jtag_state_failure.2080883260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.3641023457
Short name T322
Test name
Test status
Simulation time 515445201 ps
CPU time 16.71 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:09 AM UTC 24
Peak memory 258592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641023457
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l
c_ctrl_jtag_state_post_trans.3641023457
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.3868617010
Short name T300
Test name
Test status
Simulation time 136352196 ps
CPU time 2.12 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 234228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868617010 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3868617010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.2312864641
Short name T82
Test name
Test status
Simulation time 1868577364 ps
CPU time 22.37 seconds
Started Aug 27 06:54:51 AM UTC 24
Finished Aug 27 06:55:15 AM UTC 24
Peak memory 225760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312864641 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2312864641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.481639178
Short name T315
Test name
Test status
Simulation time 271379985 ps
CPU time 11.33 seconds
Started Aug 27 06:54:52 AM UTC 24
Finished Aug 27 06:55:05 AM UTC 24
Peak memory 238104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481639178 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.481639178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.2557064850
Short name T324
Test name
Test status
Simulation time 318188875 ps
CPU time 15 seconds
Started Aug 27 06:54:54 AM UTC 24
Finished Aug 27 06:55:10 AM UTC 24
Peak memory 237816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2557064850 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_t
oken_digest.2557064850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.4204752119
Short name T184
Test name
Test status
Simulation time 690269742 ps
CPU time 17.19 seconds
Started Aug 27 06:54:54 AM UTC 24
Finished Aug 27 06:55:12 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204752119 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_toke
n_mux.4204752119
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.3220680085
Short name T66
Test name
Test status
Simulation time 2286224153 ps
CPU time 11.37 seconds
Started Aug 27 06:54:49 AM UTC 24
Finished Aug 27 06:55:02 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220680085 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.3220680085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.2549861546
Short name T298
Test name
Test status
Simulation time 71254055 ps
CPU time 1.63 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 229036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549861546 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2549861546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.1559404385
Short name T335
Test name
Test status
Simulation time 1203539091 ps
CPU time 30.04 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:55:18 AM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559404385 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1559404385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.669048170
Short name T303
Test name
Test status
Simulation time 57158418 ps
CPU time 4.33 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:54:53 AM UTC 24
Peak memory 236628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669048170 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.669048170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.3147646183
Short name T597
Test name
Test status
Simulation time 10782043655 ps
CPU time 164.99 seconds
Started Aug 27 06:54:54 AM UTC 24
Finished Aug 27 06:57:41 AM UTC 24
Peak memory 328604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3147646183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 6.lc_ctrl_stress_all.3147646183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1946997926
Short name T299
Test name
Test status
Simulation time 16699827 ps
CPU time 1.65 seconds
Started Aug 27 06:54:47 AM UTC 24
Finished Aug 27 06:54:50 AM UTC 24
Peak memory 222980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946997926 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_volatile_unlock_smoke.1946997926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.3933672497
Short name T325
Test name
Test status
Simulation time 26315946 ps
CPU time 1.57 seconds
Started Aug 27 06:55:08 AM UTC 24
Finished Aug 27 06:55:10 AM UTC 24
Peak memory 218820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933672497 -assert no
postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3933672497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.151459159
Short name T185
Test name
Test status
Simulation time 299234049 ps
CPU time 12.86 seconds
Started Aug 27 06:55:00 AM UTC 24
Finished Aug 27 06:55:14 AM UTC 24
Peak memory 230464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151459159 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.151459159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1343079933
Short name T35
Test name
Test status
Simulation time 7041879013 ps
CPU time 7.68 seconds
Started Aug 27 06:55:04 AM UTC 24
Finished Aug 27 06:55:12 AM UTC 24
Peak memory 230148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343079933 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1343079933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.532489234
Short name T435
Test name
Test status
Simulation time 5419992976 ps
CPU time 75.37 seconds
Started Aug 27 06:55:03 AM UTC 24
Finished Aug 27 06:56:21 AM UTC 24
Peak memory 237960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532489234
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_errors.532489234
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.207510254
Short name T333
Test name
Test status
Simulation time 2226228494 ps
CPU time 13.46 seconds
Started Aug 27 06:55:04 AM UTC 24
Finished Aug 27 06:55:18 AM UTC 24
Peak memory 230040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207510254 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_prio
rity.207510254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.269177126
Short name T320
Test name
Test status
Simulation time 101426020 ps
CPU time 2.59 seconds
Started Aug 27 06:55:03 AM UTC 24
Finished Aug 27 06:55:07 AM UTC 24
Peak memory 232180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269177126
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_jtag_prog_failure.269177126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3767448672
Short name T89
Test name
Test status
Simulation time 3134910138 ps
CPU time 39.82 seconds
Started Aug 27 06:55:05 AM UTC 24
Finished Aug 27 06:55:46 AM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767448672
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l
c_ctrl_jtag_regwen_during_op.3767448672
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.3482205121
Short name T318
Test name
Test status
Simulation time 989186115 ps
CPU time 4.65 seconds
Started Aug 27 06:55:01 AM UTC 24
Finished Aug 27 06:55:07 AM UTC 24
Peak memory 229780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482205121
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_smoke.3482205121
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.3658285976
Short name T174
Test name
Test status
Simulation time 2924835409 ps
CPU time 52.17 seconds
Started Aug 27 06:55:01 AM UTC 24
Finished Aug 27 06:55:55 AM UTC 24
Peak memory 289440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658285976
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c
trl_jtag_state_failure.3658285976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.2120568674
Short name T338
Test name
Test status
Simulation time 392346252 ps
CPU time 15.93 seconds
Started Aug 27 06:55:03 AM UTC 24
Finished Aug 27 06:55:20 AM UTC 24
Peak memory 262952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120568674
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l
c_ctrl_jtag_state_post_trans.2120568674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.1415770997
Short name T313
Test name
Test status
Simulation time 84524924 ps
CPU time 3.58 seconds
Started Aug 27 06:54:58 AM UTC 24
Finished Aug 27 06:55:03 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415770997 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1415770997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.4248990005
Short name T326
Test name
Test status
Simulation time 1664488393 ps
CPU time 9.53 seconds
Started Aug 27 06:55:00 AM UTC 24
Finished Aug 27 06:55:10 AM UTC 24
Peak memory 230272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248990005 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4248990005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.2625390587
Short name T334
Test name
Test status
Simulation time 1588175064 ps
CPU time 11.3 seconds
Started Aug 27 06:55:06 AM UTC 24
Finished Aug 27 06:55:18 AM UTC 24
Peak memory 237968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625390587 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2625390587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.2684714516
Short name T359
Test name
Test status
Simulation time 3180689082 ps
CPU time 22.55 seconds
Started Aug 27 06:55:06 AM UTC 24
Finished Aug 27 06:55:30 AM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684714516 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_t
oken_digest.2684714516
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2166032027
Short name T189
Test name
Test status
Simulation time 2167824271 ps
CPU time 8.84 seconds
Started Aug 27 06:55:06 AM UTC 24
Finished Aug 27 06:55:16 AM UTC 24
Peak memory 232308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166032027 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_toke
n_mux.2166032027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.1171645448
Short name T263
Test name
Test status
Simulation time 278661609 ps
CPU time 8.84 seconds
Started Aug 27 06:55:00 AM UTC 24
Finished Aug 27 06:55:09 AM UTC 24
Peak memory 232176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171645448 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1171645448
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3707049942
Short name T309
Test name
Test status
Simulation time 11591437 ps
CPU time 1.49 seconds
Started Aug 27 06:54:56 AM UTC 24
Finished Aug 27 06:54:59 AM UTC 24
Peak memory 222732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707049942 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3707049942
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.957341657
Short name T341
Test name
Test status
Simulation time 169903030 ps
CPU time 22.98 seconds
Started Aug 27 06:54:58 AM UTC 24
Finished Aug 27 06:55:22 AM UTC 24
Peak memory 258788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957341657 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.957341657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.756805829
Short name T319
Test name
Test status
Simulation time 238686750 ps
CPU time 7.56 seconds
Started Aug 27 06:54:58 AM UTC 24
Finished Aug 27 06:55:07 AM UTC 24
Peak memory 260880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756805829 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.756805829
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.4142313127
Short name T237
Test name
Test status
Simulation time 18273641646 ps
CPU time 89.26 seconds
Started Aug 27 06:55:06 AM UTC 24
Finished Aug 27 06:56:37 AM UTC 24
Peak memory 263140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4142313127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 7.lc_ctrl_stress_all.4142313127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.861639985
Short name T307
Test name
Test status
Simulation time 86217490 ps
CPU time 1.26 seconds
Started Aug 27 06:54:56 AM UTC 24
Finished Aug 27 06:54:59 AM UTC 24
Peak memory 229168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861639985 -a
ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7
.lc_ctrl_volatile_unlock_smoke.861639985
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.874960844
Short name T329
Test name
Test status
Simulation time 17676933 ps
CPU time 1.29 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:17 AM UTC 24
Peak memory 217664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874960844 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.874960844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.2257454630
Short name T84
Test name
Test status
Simulation time 11343493 ps
CPU time 1.2 seconds
Started Aug 27 06:55:11 AM UTC 24
Finished Aug 27 06:55:14 AM UTC 24
Peak memory 217304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257454630 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2257454630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.2853287439
Short name T346
Test name
Test status
Simulation time 962488105 ps
CPU time 14.14 seconds
Started Aug 27 06:55:10 AM UTC 24
Finished Aug 27 06:55:25 AM UTC 24
Peak memory 232172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853287439 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2853287439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.711313301
Short name T36
Test name
Test status
Simulation time 453622136 ps
CPU time 2.38 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:55:16 AM UTC 24
Peak memory 229840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711313301 -assert nopo
stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.711313301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.78647174
Short name T405
Test name
Test status
Simulation time 3315641491 ps
CPU time 45.73 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:56:00 AM UTC 24
Peak memory 232444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78647174 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jt
ag_errors.78647174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.1051662097
Short name T235
Test name
Test status
Simulation time 1387727985 ps
CPU time 9.46 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:55:24 AM UTC 24
Peak memory 229972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051662097 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_pri
ority.1051662097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.521867716
Short name T350
Test name
Test status
Simulation time 1763903765 ps
CPU time 12.37 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 232104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521867716
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_jtag_prog_failure.521867716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1553921646
Short name T380
Test name
Test status
Simulation time 975504834 ps
CPU time 25.93 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:55:40 AM UTC 24
Peak memory 229800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553921646
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l
c_ctrl_jtag_regwen_during_op.1553921646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.4235611681
Short name T337
Test name
Test status
Simulation time 2243514504 ps
CPU time 7.71 seconds
Started Aug 27 06:55:11 AM UTC 24
Finished Aug 27 06:55:20 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235611681
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_smoke.4235611681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1878595959
Short name T399
Test name
Test status
Simulation time 8792563413 ps
CPU time 44.83 seconds
Started Aug 27 06:55:11 AM UTC 24
Finished Aug 27 06:55:58 AM UTC 24
Peak memory 283220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1878595959
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_c
trl_jtag_state_failure.1878595959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.4080539992
Short name T342
Test name
Test status
Simulation time 634172962 ps
CPU time 10.51 seconds
Started Aug 27 06:55:12 AM UTC 24
Finished Aug 27 06:55:23 AM UTC 24
Peak memory 262952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080539992
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l
c_ctrl_jtag_state_post_trans.4080539992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.1875653992
Short name T186
Test name
Test status
Simulation time 38567856 ps
CPU time 2.68 seconds
Started Aug 27 06:55:10 AM UTC 24
Finished Aug 27 06:55:14 AM UTC 24
Peak memory 232184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875653992 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1875653992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.617394001
Short name T345
Test name
Test status
Simulation time 5429376632 ps
CPU time 13.94 seconds
Started Aug 27 06:55:10 AM UTC 24
Finished Aug 27 06:55:25 AM UTC 24
Peak memory 226060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=617394001 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.617394001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.1419652181
Short name T355
Test name
Test status
Simulation time 1317760482 ps
CPU time 12.9 seconds
Started Aug 27 06:55:13 AM UTC 24
Finished Aug 27 06:55:27 AM UTC 24
Peak memory 237896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1419652181 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1419652181
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.3228453526
Short name T357
Test name
Test status
Simulation time 612699661 ps
CPU time 11.59 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:27 AM UTC 24
Peak memory 237880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228453526 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_t
oken_digest.3228453526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.1314132074
Short name T344
Test name
Test status
Simulation time 351397003 ps
CPU time 9 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:25 AM UTC 24
Peak memory 232380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314132074 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_toke
n_mux.1314132074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.222159450
Short name T69
Test name
Test status
Simulation time 1259162667 ps
CPU time 8.55 seconds
Started Aug 27 06:55:10 AM UTC 24
Finished Aug 27 06:55:20 AM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222159450 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.222159450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.372136743
Short name T327
Test name
Test status
Simulation time 110112543 ps
CPU time 1.78 seconds
Started Aug 27 06:55:08 AM UTC 24
Finished Aug 27 06:55:10 AM UTC 24
Peak memory 228852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372136743 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.372136743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.3389649558
Short name T368
Test name
Test status
Simulation time 2071985717 ps
CPU time 24.7 seconds
Started Aug 27 06:55:08 AM UTC 24
Finished Aug 27 06:55:34 AM UTC 24
Peak memory 258724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389649558 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3389649558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.475624845
Short name T336
Test name
Test status
Simulation time 156776440 ps
CPU time 9.89 seconds
Started Aug 27 06:55:09 AM UTC 24
Finished Aug 27 06:55:20 AM UTC 24
Peak memory 262888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475624845 -assert nopostproc +UVM_TESTNAME=lc_c
trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.475624845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.3329387881
Short name T682
Test name
Test status
Simulation time 20613184391 ps
CPU time 190.38 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:58:28 AM UTC 24
Peak memory 295572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3329387881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_stress_all.3329387881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1181700276
Short name T323
Test name
Test status
Simulation time 80415756 ps
CPU time 1.16 seconds
Started Aug 27 06:55:08 AM UTC 24
Finished Aug 27 06:55:10 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181700276 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_volatile_unlock_smoke.1181700276
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.439168853
Short name T347
Test name
Test status
Simulation time 21057030 ps
CPU time 1.48 seconds
Started Aug 27 06:55:23 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 218696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439168853 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.439168853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.1988108877
Short name T364
Test name
Test status
Simulation time 1338090929 ps
CPU time 14.03 seconds
Started Aug 27 06:55:17 AM UTC 24
Finished Aug 27 06:55:32 AM UTC 24
Peak memory 237964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988108877 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1988108877
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.2508048826
Short name T37
Test name
Test status
Simulation time 760398724 ps
CPU time 4.59 seconds
Started Aug 27 06:55:20 AM UTC 24
Finished Aug 27 06:55:25 AM UTC 24
Peak memory 229848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508048826 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2508048826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.4039332170
Short name T53
Test name
Test status
Simulation time 2252644977 ps
CPU time 59.24 seconds
Started Aug 27 06:55:19 AM UTC 24
Finished Aug 27 06:56:20 AM UTC 24
Peak memory 232432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039332170
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_errors.4039332170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.1437530556
Short name T351
Test name
Test status
Simulation time 1254041899 ps
CPU time 4.6 seconds
Started Aug 27 06:55:21 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437530556 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_pri
ority.1437530556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_priority/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4246692577
Short name T376
Test name
Test status
Simulation time 2026479124 ps
CPU time 17.47 seconds
Started Aug 27 06:55:19 AM UTC 24
Finished Aug 27 06:55:38 AM UTC 24
Peak memory 232104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246692577
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_jtag_prog_failure.4246692577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.43967773
Short name T375
Test name
Test status
Simulation time 12874850019 ps
CPU time 15.22 seconds
Started Aug 27 06:55:21 AM UTC 24
Finished Aug 27 06:55:37 AM UTC 24
Peak memory 230180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43967773 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_
ctrl_jtag_regwen_during_op.43967773
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.2011632417
Short name T340
Test name
Test status
Simulation time 313276331 ps
CPU time 2.62 seconds
Started Aug 27 06:55:18 AM UTC 24
Finished Aug 27 06:55:22 AM UTC 24
Peak memory 229940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011632417
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_smoke.2011632417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.3816923148
Short name T504
Test name
Test status
Simulation time 11900714228 ps
CPU time 95.26 seconds
Started Aug 27 06:55:18 AM UTC 24
Finished Aug 27 06:56:55 AM UTC 24
Peak memory 295580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816923148
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_c
trl_jtag_state_failure.3816923148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.1532785587
Short name T372
Test name
Test status
Simulation time 1716052981 ps
CPU time 15.21 seconds
Started Aug 27 06:55:19 AM UTC 24
Finished Aug 27 06:55:36 AM UTC 24
Peak memory 236560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst
rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532785587
-assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.l
c_ctrl_jtag_state_post_trans.1532785587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2989119029
Short name T339
Test name
Test status
Simulation time 122066927 ps
CPU time 3 seconds
Started Aug 27 06:55:17 AM UTC 24
Finished Aug 27 06:55:21 AM UTC 24
Peak memory 234496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989119029 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2989119029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_prog_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.1222129519
Short name T348
Test name
Test status
Simulation time 4034275189 ps
CPU time 7.27 seconds
Started Aug 27 06:55:18 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 229992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222129519 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1222129519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.96779305
Short name T358
Test name
Test status
Simulation time 738827099 ps
CPU time 7.85 seconds
Started Aug 27 06:55:21 AM UTC 24
Finished Aug 27 06:55:30 AM UTC 24
Peak memory 232248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96779305 -assert nopos
tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.96779305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.1142258214
Short name T373
Test name
Test status
Simulation time 971151681 ps
CPU time 12.74 seconds
Started Aug 27 06:55:22 AM UTC 24
Finished Aug 27 06:55:36 AM UTC 24
Peak memory 232376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142258214 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_t
oken_digest.1142258214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.1683709629
Short name T363
Test name
Test status
Simulation time 2368491747 ps
CPU time 9.54 seconds
Started Aug 27 06:55:21 AM UTC 24
Finished Aug 27 06:55:32 AM UTC 24
Peak memory 237956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_
enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683709629 -assert nop
ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces
/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_toke
n_mux.1683709629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1180256832
Short name T264
Test name
Test status
Simulation time 249583835 ps
CPU time 10 seconds
Started Aug 27 06:55:18 AM UTC 24
Finished Aug 27 06:55:29 AM UTC 24
Peak memory 232384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180256832 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1180256832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_security_escalation/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.3854686002
Short name T330
Test name
Test status
Simulation time 23893420 ps
CPU time 1.28 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:17 AM UTC 24
Peak memory 228856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3854686002 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3854686002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.6381056
Short name T386
Test name
Test status
Simulation time 329917745 ps
CPU time 28.14 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:44 AM UTC 24
Peak memory 262736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6381056 -assert nopostproc +UVM_TESTNAME=lc_ctr
l_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.6381056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_failure/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.3780800661
Short name T352
Test name
Test status
Simulation time 56406460 ps
CPU time 8.81 seconds
Started Aug 27 06:55:16 AM UTC 24
Finished Aug 27 06:55:26 AM UTC 24
Peak memory 263096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780800661 -assert nopostproc +UVM_TESTNAME=lc_
ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3780800661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_post_trans/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2683981557
Short name T108
Test name
Test status
Simulation time 982268956 ps
CPU time 23 seconds
Started Aug 27 06:55:22 AM UTC 24
Finished Aug 27 06:55:46 AM UTC 24
Peak memory 262824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000
0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2683981557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_stress_all.2683981557
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2129133282
Short name T164
Test name
Test status
Simulation time 5337069027 ps
CPU time 76.73 seconds
Started Aug 27 06:55:22 AM UTC 24
Finished Aug 27 06:56:41 AM UTC 24
Peak memory 238160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_
rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2129133282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST
_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_
unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.2129133282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2448008247
Short name T331
Test name
Test status
Simulation time 17935012 ps
CPU time 1.22 seconds
Started Aug 27 06:55:15 AM UTC 24
Finished Aug 27 06:55:17 AM UTC 24
Peak memory 220684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448008247 -
assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_volatile_unlock_smoke.2448008247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest
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