| T577 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.569100872 |
|
|
Sep 01 12:40:28 PM UTC 24 |
Sep 01 12:40:31 PM UTC 24 |
36258786 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.4253096477 |
|
|
Sep 01 12:38:25 PM UTC 24 |
Sep 01 12:38:28 PM UTC 24 |
146548026 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2687535872 |
|
|
Sep 01 12:38:27 PM UTC 24 |
Sep 01 12:38:29 PM UTC 24 |
20765700 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.767154146 |
|
|
Sep 01 12:38:26 PM UTC 24 |
Sep 01 12:38:29 PM UTC 24 |
24374044 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.218731502 |
|
|
Sep 01 12:38:13 PM UTC 24 |
Sep 01 12:38:31 PM UTC 24 |
372307562 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.477911369 |
|
|
Sep 01 12:38:20 PM UTC 24 |
Sep 01 12:38:31 PM UTC 24 |
188858354 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.3535860727 |
|
|
Sep 01 12:38:23 PM UTC 24 |
Sep 01 12:38:33 PM UTC 24 |
599303252 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.3459451600 |
|
|
Sep 01 12:38:04 PM UTC 24 |
Sep 01 12:38:33 PM UTC 24 |
753383881 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3538559453 |
|
|
Sep 01 12:38:22 PM UTC 24 |
Sep 01 12:38:33 PM UTC 24 |
1256468623 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3639279790 |
|
|
Sep 01 12:38:29 PM UTC 24 |
Sep 01 12:38:34 PM UTC 24 |
71679324 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2402256471 |
|
|
Sep 01 12:38:19 PM UTC 24 |
Sep 01 12:38:37 PM UTC 24 |
350952450 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.84132326 |
|
|
Sep 01 12:37:03 PM UTC 24 |
Sep 01 12:38:39 PM UTC 24 |
6397012911 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1382363901 |
|
|
Sep 01 12:37:28 PM UTC 24 |
Sep 01 12:38:40 PM UTC 24 |
2559747533 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.690473558 |
|
|
Sep 01 12:38:29 PM UTC 24 |
Sep 01 12:38:40 PM UTC 24 |
157939896 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.1205510652 |
|
|
Sep 01 12:38:38 PM UTC 24 |
Sep 01 12:38:41 PM UTC 24 |
40932103 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.2485716352 |
|
|
Sep 01 12:38:23 PM UTC 24 |
Sep 01 12:38:42 PM UTC 24 |
1755159508 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.2338662798 |
|
|
Sep 01 12:38:40 PM UTC 24 |
Sep 01 12:38:42 PM UTC 24 |
17040628 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3846888090 |
|
|
Sep 01 12:38:41 PM UTC 24 |
Sep 01 12:38:43 PM UTC 24 |
42043888 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.1063047745 |
|
|
Sep 01 12:38:34 PM UTC 24 |
Sep 01 12:38:44 PM UTC 24 |
1173447001 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.134764673 |
|
|
Sep 01 12:38:30 PM UTC 24 |
Sep 01 12:38:46 PM UTC 24 |
1421618299 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1676554626 |
|
|
Sep 01 12:38:30 PM UTC 24 |
Sep 01 12:38:46 PM UTC 24 |
1383522547 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2712917307 |
|
|
Sep 01 12:38:33 PM UTC 24 |
Sep 01 12:38:46 PM UTC 24 |
1220798225 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.274041563 |
|
|
Sep 01 12:38:34 PM UTC 24 |
Sep 01 12:38:46 PM UTC 24 |
297781393 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.3034149541 |
|
|
Sep 01 12:38:33 PM UTC 24 |
Sep 01 12:38:47 PM UTC 24 |
1279414128 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1275826623 |
|
|
Sep 01 12:38:43 PM UTC 24 |
Sep 01 12:38:47 PM UTC 24 |
31744471 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.1907483579 |
|
|
Sep 01 12:38:28 PM UTC 24 |
Sep 01 12:38:47 PM UTC 24 |
809555341 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.3840879886 |
|
|
Sep 01 12:38:16 PM UTC 24 |
Sep 01 12:38:49 PM UTC 24 |
210791568 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2475529728 |
|
|
Sep 01 12:38:48 PM UTC 24 |
Sep 01 12:38:51 PM UTC 24 |
20706674 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.2839534457 |
|
|
Sep 01 12:38:49 PM UTC 24 |
Sep 01 12:38:52 PM UTC 24 |
108564324 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.538298190 |
|
|
Sep 01 12:38:41 PM UTC 24 |
Sep 01 12:38:52 PM UTC 24 |
267430539 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.642393659 |
|
|
Sep 01 12:38:45 PM UTC 24 |
Sep 01 12:38:52 PM UTC 24 |
341362160 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.334587818 |
|
|
Sep 01 12:38:51 PM UTC 24 |
Sep 01 12:38:53 PM UTC 24 |
12200118 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.2592235112 |
|
|
Sep 01 12:38:44 PM UTC 24 |
Sep 01 12:38:54 PM UTC 24 |
731359400 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.1067121669 |
|
|
Sep 01 12:38:22 PM UTC 24 |
Sep 01 12:38:55 PM UTC 24 |
785115725 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.1021948536 |
|
|
Sep 01 12:36:31 PM UTC 24 |
Sep 01 12:38:56 PM UTC 24 |
6734682329 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1318358894 |
|
|
Sep 01 12:38:53 PM UTC 24 |
Sep 01 12:38:58 PM UTC 24 |
61157919 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.4117079770 |
|
|
Sep 01 12:38:48 PM UTC 24 |
Sep 01 12:39:03 PM UTC 24 |
358871499 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.2664256358 |
|
|
Sep 01 12:38:43 PM UTC 24 |
Sep 01 12:39:03 PM UTC 24 |
1086522892 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.803316095 |
|
|
Sep 01 12:33:56 PM UTC 24 |
Sep 01 12:39:05 PM UTC 24 |
49704793788 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.958435106 |
|
|
Sep 01 12:39:15 PM UTC 24 |
Sep 01 12:39:18 PM UTC 24 |
13364725 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.1836096342 |
|
|
Sep 01 12:38:48 PM UTC 24 |
Sep 01 12:39:05 PM UTC 24 |
1839775595 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.3751236445 |
|
|
Sep 01 12:36:50 PM UTC 24 |
Sep 01 12:39:06 PM UTC 24 |
13571989819 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.3009916366 |
|
|
Sep 01 12:38:54 PM UTC 24 |
Sep 01 12:39:06 PM UTC 24 |
1120276393 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2860633997 |
|
|
Sep 01 12:38:53 PM UTC 24 |
Sep 01 12:39:06 PM UTC 24 |
280217625 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.3457562000 |
|
|
Sep 01 12:38:54 PM UTC 24 |
Sep 01 12:39:08 PM UTC 24 |
347432742 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1234426633 |
|
|
Sep 01 12:39:06 PM UTC 24 |
Sep 01 12:39:08 PM UTC 24 |
14026081 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1887614976 |
|
|
Sep 01 12:38:53 PM UTC 24 |
Sep 01 12:39:08 PM UTC 24 |
654836016 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.940766596 |
|
|
Sep 01 12:39:06 PM UTC 24 |
Sep 01 12:39:09 PM UTC 24 |
324332856 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.606468365 |
|
|
Sep 01 12:39:06 PM UTC 24 |
Sep 01 12:39:09 PM UTC 24 |
41441231 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3894634290 |
|
|
Sep 01 12:38:57 PM UTC 24 |
Sep 01 12:39:10 PM UTC 24 |
773135885 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.3627998431 |
|
|
Sep 01 12:38:57 PM UTC 24 |
Sep 01 12:39:10 PM UTC 24 |
1051717391 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.1895601031 |
|
|
Sep 01 12:39:07 PM UTC 24 |
Sep 01 12:39:11 PM UTC 24 |
31002475 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2607900082 |
|
|
Sep 01 12:38:47 PM UTC 24 |
Sep 01 12:39:12 PM UTC 24 |
709662981 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2381848536 |
|
|
Sep 01 12:38:59 PM UTC 24 |
Sep 01 12:39:14 PM UTC 24 |
462308745 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2475189270 |
|
|
Sep 01 12:38:34 PM UTC 24 |
Sep 01 12:39:14 PM UTC 24 |
6999077147 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2440862468 |
|
|
Sep 01 12:38:41 PM UTC 24 |
Sep 01 12:39:15 PM UTC 24 |
223427583 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.119386796 |
|
|
Sep 01 12:40:11 PM UTC 24 |
Sep 01 12:40:27 PM UTC 24 |
5650596889 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.215249495 |
|
|
Sep 01 12:39:07 PM UTC 24 |
Sep 01 12:39:19 PM UTC 24 |
49524653 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.3140269947 |
|
|
Sep 01 12:39:10 PM UTC 24 |
Sep 01 12:39:19 PM UTC 24 |
772940347 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.3734706697 |
|
|
Sep 01 12:39:15 PM UTC 24 |
Sep 01 12:39:20 PM UTC 24 |
29245763 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3186119359 |
|
|
Sep 01 12:37:50 PM UTC 24 |
Sep 01 12:39:22 PM UTC 24 |
2297306006 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.4054917872 |
|
|
Sep 01 12:39:10 PM UTC 24 |
Sep 01 12:39:22 PM UTC 24 |
925850769 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.1112277779 |
|
|
Sep 01 12:37:39 PM UTC 24 |
Sep 01 12:39:24 PM UTC 24 |
2595737676 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.2013244899 |
|
|
Sep 01 12:39:19 PM UTC 24 |
Sep 01 12:39:24 PM UTC 24 |
458177727 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2183950738 |
|
|
Sep 01 12:39:21 PM UTC 24 |
Sep 01 12:39:24 PM UTC 24 |
129054944 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1374738969 |
|
|
Sep 01 12:39:10 PM UTC 24 |
Sep 01 12:39:24 PM UTC 24 |
1380327229 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.4260757259 |
|
|
Sep 01 12:39:16 PM UTC 24 |
Sep 01 12:39:25 PM UTC 24 |
309669145 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.3189243179 |
|
|
Sep 01 12:39:11 PM UTC 24 |
Sep 01 12:39:25 PM UTC 24 |
1086834090 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.1716981795 |
|
|
Sep 01 12:39:26 PM UTC 24 |
Sep 01 12:39:28 PM UTC 24 |
151052608 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.319881128 |
|
|
Sep 01 12:39:26 PM UTC 24 |
Sep 01 12:39:28 PM UTC 24 |
28250707 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1386970838 |
|
|
Sep 01 12:39:09 PM UTC 24 |
Sep 01 12:39:30 PM UTC 24 |
492070909 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.1870625611 |
|
|
Sep 01 12:39:21 PM UTC 24 |
Sep 01 12:39:32 PM UTC 24 |
410512006 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.3074534292 |
|
|
Sep 01 12:39:26 PM UTC 24 |
Sep 01 12:39:33 PM UTC 24 |
91506065 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1028283324 |
|
|
Sep 01 12:39:09 PM UTC 24 |
Sep 01 12:39:34 PM UTC 24 |
2154646309 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.1547504979 |
|
|
Sep 01 12:39:23 PM UTC 24 |
Sep 01 12:39:34 PM UTC 24 |
233455874 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.1248213459 |
|
|
Sep 01 12:39:29 PM UTC 24 |
Sep 01 12:39:34 PM UTC 24 |
75874225 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3024200732 |
|
|
Sep 01 12:39:21 PM UTC 24 |
Sep 01 12:39:36 PM UTC 24 |
306841525 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1068275208 |
|
|
Sep 01 12:34:57 PM UTC 24 |
Sep 01 12:39:39 PM UTC 24 |
30485136428 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.2152985382 |
|
|
Sep 01 12:39:23 PM UTC 24 |
Sep 01 12:39:40 PM UTC 24 |
585882320 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.4154278481 |
|
|
Sep 01 12:38:52 PM UTC 24 |
Sep 01 12:39:40 PM UTC 24 |
278878261 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2227205540 |
|
|
Sep 01 12:39:29 PM UTC 24 |
Sep 01 12:39:41 PM UTC 24 |
1230528815 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.1683857711 |
|
|
Sep 01 12:39:21 PM UTC 24 |
Sep 01 12:39:41 PM UTC 24 |
715165283 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.1921773982 |
|
|
Sep 01 12:39:07 PM UTC 24 |
Sep 01 12:39:42 PM UTC 24 |
3242065246 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3075739767 |
|
|
Sep 01 12:38:35 PM UTC 24 |
Sep 01 12:39:43 PM UTC 24 |
908443391 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2519557969 |
|
|
Sep 01 12:39:41 PM UTC 24 |
Sep 01 12:39:43 PM UTC 24 |
10689267 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.1094383014 |
|
|
Sep 01 12:39:41 PM UTC 24 |
Sep 01 12:39:44 PM UTC 24 |
21816559 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.2478499508 |
|
|
Sep 01 12:39:41 PM UTC 24 |
Sep 01 12:39:44 PM UTC 24 |
98615138 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.2846963185 |
|
|
Sep 01 12:38:24 PM UTC 24 |
Sep 01 12:39:44 PM UTC 24 |
8369312262 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.1924431964 |
|
|
Sep 01 12:39:35 PM UTC 24 |
Sep 01 12:39:46 PM UTC 24 |
1085009255 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.1483727201 |
|
|
Sep 01 12:40:12 PM UTC 24 |
Sep 01 12:40:29 PM UTC 24 |
2733618876 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.4178397550 |
|
|
Sep 01 12:39:32 PM UTC 24 |
Sep 01 12:39:47 PM UTC 24 |
775422752 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2413015783 |
|
|
Sep 01 12:39:31 PM UTC 24 |
Sep 01 12:39:47 PM UTC 24 |
2585062024 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.1425081880 |
|
|
Sep 01 12:39:26 PM UTC 24 |
Sep 01 12:39:48 PM UTC 24 |
608039566 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3555276222 |
|
|
Sep 01 12:39:45 PM UTC 24 |
Sep 01 12:39:48 PM UTC 24 |
15535784 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1477088210 |
|
|
Sep 01 12:39:35 PM UTC 24 |
Sep 01 12:39:49 PM UTC 24 |
489556206 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.1913209827 |
|
|
Sep 01 12:39:35 PM UTC 24 |
Sep 01 12:39:50 PM UTC 24 |
351546349 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.382697545 |
|
|
Sep 01 12:39:45 PM UTC 24 |
Sep 01 12:39:51 PM UTC 24 |
525051581 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.3026872499 |
|
|
Sep 01 12:39:49 PM UTC 24 |
Sep 01 12:39:52 PM UTC 24 |
18223443 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.1473304140 |
|
|
Sep 01 12:39:35 PM UTC 24 |
Sep 01 12:39:52 PM UTC 24 |
240889032 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3360578671 |
|
|
Sep 01 12:39:51 PM UTC 24 |
Sep 01 12:39:54 PM UTC 24 |
29410917 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.654250237 |
|
|
Sep 01 12:39:50 PM UTC 24 |
Sep 01 12:39:54 PM UTC 24 |
26356353 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1166849089 |
|
|
Sep 01 12:39:44 PM UTC 24 |
Sep 01 12:39:56 PM UTC 24 |
102767281 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3643697765 |
|
|
Sep 01 12:37:17 PM UTC 24 |
Sep 01 12:39:57 PM UTC 24 |
12729529966 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.2206558704 |
|
|
Sep 01 12:39:54 PM UTC 24 |
Sep 01 12:39:57 PM UTC 24 |
76774842 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3928877652 |
|
|
Sep 01 12:39:45 PM UTC 24 |
Sep 01 12:39:58 PM UTC 24 |
973985098 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.2574150478 |
|
|
Sep 01 12:39:46 PM UTC 24 |
Sep 01 12:39:58 PM UTC 24 |
461504749 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.49338809 |
|
|
Sep 01 12:39:52 PM UTC 24 |
Sep 01 12:39:59 PM UTC 24 |
313898074 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.3585617253 |
|
|
Sep 01 12:39:45 PM UTC 24 |
Sep 01 12:39:59 PM UTC 24 |
247943759 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3210087340 |
|
|
Sep 01 12:39:45 PM UTC 24 |
Sep 01 12:40:01 PM UTC 24 |
912129091 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.4158329032 |
|
|
Sep 01 12:39:48 PM UTC 24 |
Sep 01 12:40:03 PM UTC 24 |
477754528 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.3369562658 |
|
|
Sep 01 12:40:01 PM UTC 24 |
Sep 01 12:40:04 PM UTC 24 |
40854529 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1504164084 |
|
|
Sep 01 12:40:03 PM UTC 24 |
Sep 01 12:40:05 PM UTC 24 |
33376506 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.2553952451 |
|
|
Sep 01 12:39:16 PM UTC 24 |
Sep 01 12:40:07 PM UTC 24 |
496672385 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.2828919189 |
|
|
Sep 01 12:39:04 PM UTC 24 |
Sep 01 12:40:08 PM UTC 24 |
2646292306 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2645076491 |
|
|
Sep 01 12:39:58 PM UTC 24 |
Sep 01 12:40:09 PM UTC 24 |
285613808 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2050823679 |
|
|
Sep 01 12:39:55 PM UTC 24 |
Sep 01 12:40:09 PM UTC 24 |
1015975206 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3460548983 |
|
|
Sep 01 12:40:02 PM UTC 24 |
Sep 01 12:40:10 PM UTC 24 |
571181889 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.1353125736 |
|
|
Sep 01 12:39:55 PM UTC 24 |
Sep 01 12:40:10 PM UTC 24 |
255746742 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.2923393303 |
|
|
Sep 01 12:39:42 PM UTC 24 |
Sep 01 12:40:10 PM UTC 24 |
519435779 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.3349414481 |
|
|
Sep 01 12:39:57 PM UTC 24 |
Sep 01 12:40:12 PM UTC 24 |
427126283 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2707370446 |
|
|
Sep 01 12:40:09 PM UTC 24 |
Sep 01 12:40:12 PM UTC 24 |
70174601 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.117886577 |
|
|
Sep 01 12:31:53 PM UTC 24 |
Sep 01 12:40:12 PM UTC 24 |
48339253236 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.3041661480 |
|
|
Sep 01 12:38:14 PM UTC 24 |
Sep 01 12:40:16 PM UTC 24 |
16143783575 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.3110598649 |
|
|
Sep 01 12:39:58 PM UTC 24 |
Sep 01 12:40:16 PM UTC 24 |
353291041 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2011007313 |
|
|
Sep 01 12:40:14 PM UTC 24 |
Sep 01 12:40:17 PM UTC 24 |
56073331 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.3218963302 |
|
|
Sep 01 12:40:10 PM UTC 24 |
Sep 01 12:40:18 PM UTC 24 |
1811056603 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3350809096 |
|
|
Sep 01 12:40:09 PM UTC 24 |
Sep 01 12:40:19 PM UTC 24 |
235283161 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.3914223263 |
|
|
Sep 01 12:40:06 PM UTC 24 |
Sep 01 12:40:20 PM UTC 24 |
266081482 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2831549376 |
|
|
Sep 01 12:40:10 PM UTC 24 |
Sep 01 12:40:20 PM UTC 24 |
486789627 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3183745465 |
|
|
Sep 01 12:40:18 PM UTC 24 |
Sep 01 12:40:20 PM UTC 24 |
20261393 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.3304421919 |
|
|
Sep 01 12:39:49 PM UTC 24 |
Sep 01 12:40:20 PM UTC 24 |
2572433944 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1155827496 |
|
|
Sep 01 12:40:18 PM UTC 24 |
Sep 01 12:40:27 PM UTC 24 |
212337466 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2476104491 |
|
|
Sep 01 12:40:20 PM UTC 24 |
Sep 01 12:40:23 PM UTC 24 |
369339685 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3769799175 |
|
|
Sep 01 12:40:00 PM UTC 24 |
Sep 01 12:40:24 PM UTC 24 |
2503408528 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.2824079022 |
|
|
Sep 01 12:40:19 PM UTC 24 |
Sep 01 12:40:25 PM UTC 24 |
343367613 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2764963297 |
|
|
Sep 01 12:38:48 PM UTC 24 |
Sep 01 12:40:29 PM UTC 24 |
7534056981 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.3446689925 |
|
|
Sep 01 12:40:21 PM UTC 24 |
Sep 01 12:40:31 PM UTC 24 |
5269683459 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.1114566904 |
|
|
Sep 01 12:40:21 PM UTC 24 |
Sep 01 12:40:32 PM UTC 24 |
281591746 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.378486379 |
|
|
Sep 01 12:40:30 PM UTC 24 |
Sep 01 12:40:32 PM UTC 24 |
18807889 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2227931125 |
|
|
Sep 01 12:40:21 PM UTC 24 |
Sep 01 12:40:32 PM UTC 24 |
741555459 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.926680666 |
|
|
Sep 01 12:40:28 PM UTC 24 |
Sep 01 12:40:32 PM UTC 24 |
43491415 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1271489924 |
|
|
Sep 01 12:40:10 PM UTC 24 |
Sep 01 12:40:34 PM UTC 24 |
6393439861 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.2174426506 |
|
|
Sep 01 12:34:32 PM UTC 24 |
Sep 01 12:40:34 PM UTC 24 |
8774414714 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.2928193536 |
|
|
Sep 01 12:40:32 PM UTC 24 |
Sep 01 12:40:36 PM UTC 24 |
145807628 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3621318805 |
|
|
Sep 01 12:39:52 PM UTC 24 |
Sep 01 12:40:38 PM UTC 24 |
839917274 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.4105827472 |
|
|
Sep 01 12:40:24 PM UTC 24 |
Sep 01 12:40:40 PM UTC 24 |
1754712068 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.36126636 |
|
|
Sep 01 12:40:21 PM UTC 24 |
Sep 01 12:40:40 PM UTC 24 |
261139054 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2325380413 |
|
|
Sep 01 12:39:26 PM UTC 24 |
Sep 01 12:40:42 PM UTC 24 |
2660040660 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.1096299208 |
|
|
Sep 01 12:40:33 PM UTC 24 |
Sep 01 12:40:42 PM UTC 24 |
4670792009 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.3068344599 |
|
|
Sep 01 12:40:32 PM UTC 24 |
Sep 01 12:40:43 PM UTC 24 |
238788015 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3813851340 |
|
|
Sep 01 12:40:24 PM UTC 24 |
Sep 01 12:40:43 PM UTC 24 |
419908841 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3613410850 |
|
|
Sep 01 12:40:42 PM UTC 24 |
Sep 01 12:40:44 PM UTC 24 |
50633013 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.1288307918 |
|
|
Sep 01 12:40:41 PM UTC 24 |
Sep 01 12:40:44 PM UTC 24 |
159888101 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.2617058574 |
|
|
Sep 01 12:40:04 PM UTC 24 |
Sep 01 12:40:45 PM UTC 24 |
456551933 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.2097445598 |
|
|
Sep 01 12:40:42 PM UTC 24 |
Sep 01 12:40:47 PM UTC 24 |
300011890 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.1479818333 |
|
|
Sep 01 12:40:33 PM UTC 24 |
Sep 01 12:40:48 PM UTC 24 |
932256719 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.1544999310 |
|
|
Sep 01 12:40:44 PM UTC 24 |
Sep 01 12:40:49 PM UTC 24 |
501576653 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.841222992 |
|
|
Sep 01 12:40:33 PM UTC 24 |
Sep 01 12:40:51 PM UTC 24 |
528030883 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.1307080429 |
|
|
Sep 01 12:40:33 PM UTC 24 |
Sep 01 12:40:51 PM UTC 24 |
695752060 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.3479909991 |
|
|
Sep 01 12:40:36 PM UTC 24 |
Sep 01 12:40:52 PM UTC 24 |
5389641723 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.2528438923 |
|
|
Sep 01 12:40:36 PM UTC 24 |
Sep 01 12:40:55 PM UTC 24 |
554958691 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1779537052 |
|
|
Sep 01 12:40:52 PM UTC 24 |
Sep 01 12:40:55 PM UTC 24 |
20020778 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1267937566 |
|
|
Sep 01 12:40:43 PM UTC 24 |
Sep 01 12:40:56 PM UTC 24 |
57282943 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1796285498 |
|
|
Sep 01 12:40:14 PM UTC 24 |
Sep 01 12:40:56 PM UTC 24 |
1773478013 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2757781995 |
|
|
Sep 01 12:40:45 PM UTC 24 |
Sep 01 12:40:58 PM UTC 24 |
252099806 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1287783455 |
|
|
Sep 01 12:40:56 PM UTC 24 |
Sep 01 12:40:58 PM UTC 24 |
18630918 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.1012445762 |
|
|
Sep 01 12:40:45 PM UTC 24 |
Sep 01 12:41:00 PM UTC 24 |
13235104770 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.924435348 |
|
|
Sep 01 12:40:18 PM UTC 24 |
Sep 01 12:41:00 PM UTC 24 |
2773079588 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.2552848574 |
|
|
Sep 01 12:40:48 PM UTC 24 |
Sep 01 12:41:00 PM UTC 24 |
1679290334 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.1855231520 |
|
|
Sep 01 12:40:53 PM UTC 24 |
Sep 01 12:41:01 PM UTC 24 |
103784989 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.2180952097 |
|
|
Sep 01 12:40:57 PM UTC 24 |
Sep 01 12:41:02 PM UTC 24 |
201634200 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1285821930 |
|
|
Sep 01 12:40:44 PM UTC 24 |
Sep 01 12:41:02 PM UTC 24 |
413738660 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.138032271 |
|
|
Sep 01 12:40:30 PM UTC 24 |
Sep 01 12:41:02 PM UTC 24 |
1646088230 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2646368237 |
|
|
Sep 01 12:41:00 PM UTC 24 |
Sep 01 12:41:05 PM UTC 24 |
106473278 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.3483071195 |
|
|
Sep 01 12:40:46 PM UTC 24 |
Sep 01 12:41:05 PM UTC 24 |
432084410 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.1537069816 |
|
|
Sep 01 12:41:03 PM UTC 24 |
Sep 01 12:41:06 PM UTC 24 |
40795598 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.2346070947 |
|
|
Sep 01 12:41:05 PM UTC 24 |
Sep 01 12:41:08 PM UTC 24 |
80044384 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3760770906 |
|
|
Sep 01 12:41:06 PM UTC 24 |
Sep 01 12:41:09 PM UTC 24 |
21884543 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.2885942826 |
|
|
Sep 01 12:40:59 PM UTC 24 |
Sep 01 12:41:09 PM UTC 24 |
207125024 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.298749547 |
|
|
Sep 01 12:40:49 PM UTC 24 |
Sep 01 12:41:14 PM UTC 24 |
5353626403 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.2398397691 |
|
|
Sep 01 12:40:59 PM UTC 24 |
Sep 01 12:41:15 PM UTC 24 |
1149014354 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1436935507 |
|
|
Sep 01 12:41:10 PM UTC 24 |
Sep 01 12:41:15 PM UTC 24 |
66080861 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2745988976 |
|
|
Sep 01 12:40:57 PM UTC 24 |
Sep 01 12:41:15 PM UTC 24 |
108750769 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.1929403755 |
|
|
Sep 01 12:41:00 PM UTC 24 |
Sep 01 12:41:15 PM UTC 24 |
794418646 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.3757481218 |
|
|
Sep 01 12:37:49 PM UTC 24 |
Sep 01 12:41:16 PM UTC 24 |
5568883428 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.1148400539 |
|
|
Sep 01 12:40:56 PM UTC 24 |
Sep 01 12:41:19 PM UTC 24 |
449488950 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.1667129835 |
|
|
Sep 01 12:41:15 PM UTC 24 |
Sep 01 12:41:20 PM UTC 24 |
101561023 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1241667368 |
|
|
Sep 01 12:41:18 PM UTC 24 |
Sep 01 12:41:20 PM UTC 24 |
101126483 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.3063491472 |
|
|
Sep 01 12:41:45 PM UTC 24 |
Sep 01 12:41:48 PM UTC 24 |
16045898 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.709944895 |
|
|
Sep 01 12:40:43 PM UTC 24 |
Sep 01 12:41:20 PM UTC 24 |
1038770038 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2892135453 |
|
|
Sep 01 12:41:45 PM UTC 24 |
Sep 01 12:41:48 PM UTC 24 |
12830875 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.2014508518 |
|
|
Sep 01 12:41:09 PM UTC 24 |
Sep 01 12:41:21 PM UTC 24 |
267518801 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2821986587 |
|
|
Sep 01 12:41:02 PM UTC 24 |
Sep 01 12:41:23 PM UTC 24 |
2402743406 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3176741577 |
|
|
Sep 01 12:41:21 PM UTC 24 |
Sep 01 12:41:24 PM UTC 24 |
75209007 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.4223254864 |
|
|
Sep 01 12:41:10 PM UTC 24 |
Sep 01 12:41:24 PM UTC 24 |
273897956 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2533601252 |
|
|
Sep 01 12:41:02 PM UTC 24 |
Sep 01 12:41:25 PM UTC 24 |
842574956 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.3170716426 |
|
|
Sep 01 12:41:20 PM UTC 24 |
Sep 01 12:41:25 PM UTC 24 |
249019189 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.944552390 |
|
|
Sep 01 12:41:13 PM UTC 24 |
Sep 01 12:41:26 PM UTC 24 |
201379452 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.108909643 |
|
|
Sep 01 12:41:21 PM UTC 24 |
Sep 01 12:41:27 PM UTC 24 |
344901908 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.795869608 |
|
|
Sep 01 12:41:21 PM UTC 24 |
Sep 01 12:41:27 PM UTC 24 |
199874275 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.1889792614 |
|
|
Sep 01 12:41:28 PM UTC 24 |
Sep 01 12:41:30 PM UTC 24 |
70140525 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.374965364 |
|
|
Sep 01 12:41:24 PM UTC 24 |
Sep 01 12:41:30 PM UTC 24 |
655411212 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.1681440988 |
|
|
Sep 01 12:41:16 PM UTC 24 |
Sep 01 12:41:33 PM UTC 24 |
640845144 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1780926410 |
|
|
Sep 01 12:41:31 PM UTC 24 |
Sep 01 12:41:33 PM UTC 24 |
44448091 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1648129621 |
|
|
Sep 01 12:41:28 PM UTC 24 |
Sep 01 12:41:33 PM UTC 24 |
83863558 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3289231767 |
|
|
Sep 01 12:41:16 PM UTC 24 |
Sep 01 12:41:36 PM UTC 24 |
1549397002 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.459913203 |
|
|
Sep 01 12:40:37 PM UTC 24 |
Sep 01 12:41:38 PM UTC 24 |
3899307323 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.2165683783 |
|
|
Sep 01 12:39:37 PM UTC 24 |
Sep 01 12:41:38 PM UTC 24 |
8777307853 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2680585306 |
|
|
Sep 01 12:41:23 PM UTC 24 |
Sep 01 12:41:38 PM UTC 24 |
218756379 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.2593296357 |
|
|
Sep 01 12:41:34 PM UTC 24 |
Sep 01 12:41:39 PM UTC 24 |
174710305 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.1979471436 |
|
|
Sep 01 12:41:16 PM UTC 24 |
Sep 01 12:41:39 PM UTC 24 |
1086651388 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3756895726 |
|
|
Sep 01 12:41:26 PM UTC 24 |
Sep 01 12:41:42 PM UTC 24 |
2907956795 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.945307614 |
|
|
Sep 01 12:41:26 PM UTC 24 |
Sep 01 12:41:44 PM UTC 24 |
1187833675 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.4288287827 |
|
|
Sep 01 12:41:23 PM UTC 24 |
Sep 01 12:41:45 PM UTC 24 |
1509453575 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.1895734764 |
|
|
Sep 01 12:41:37 PM UTC 24 |
Sep 01 12:41:45 PM UTC 24 |
1410826062 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.815474263 |
|
|
Sep 01 12:41:25 PM UTC 24 |
Sep 01 12:41:47 PM UTC 24 |
1540620390 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1953709448 |
|
|
Sep 01 12:41:39 PM UTC 24 |
Sep 01 12:41:50 PM UTC 24 |
196310727 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.847867290 |
|
|
Sep 01 12:37:58 PM UTC 24 |
Sep 01 12:41:51 PM UTC 24 |
35881828266 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.3789452346 |
|
|
Sep 01 12:41:45 PM UTC 24 |
Sep 01 12:41:51 PM UTC 24 |
76833704 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.2129949489 |
|
|
Sep 01 12:42:53 PM UTC 24 |
Sep 01 12:42:56 PM UTC 24 |
104097259 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.1241670655 |
|
|
Sep 01 12:41:34 PM UTC 24 |
Sep 01 12:41:54 PM UTC 24 |
60754390 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.3946511505 |
|
|
Sep 01 12:41:39 PM UTC 24 |
Sep 01 12:41:55 PM UTC 24 |
2480444847 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2692526038 |
|
|
Sep 01 12:41:49 PM UTC 24 |
Sep 01 12:41:56 PM UTC 24 |
1182173767 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1393235206 |
|
|
Sep 01 12:41:34 PM UTC 24 |
Sep 01 12:41:57 PM UTC 24 |
1464106477 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1518540315 |
|
|
Sep 01 12:41:31 PM UTC 24 |
Sep 01 12:41:58 PM UTC 24 |
1050361791 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2704763022 |
|
|
Sep 01 12:41:07 PM UTC 24 |
Sep 01 12:41:59 PM UTC 24 |
1139876720 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.4107867823 |
|
|
Sep 01 12:41:39 PM UTC 24 |
Sep 01 12:42:00 PM UTC 24 |
499056353 ps |
| T800 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2493798571 |
|
|
Sep 01 12:41:58 PM UTC 24 |
Sep 01 12:42:01 PM UTC 24 |
82630572 ps |
| T801 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.757795698 |
|
|
Sep 01 12:41:49 PM UTC 24 |
Sep 01 12:42:01 PM UTC 24 |
83004116 ps |
| T802 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.430179250 |
|
|
Sep 01 12:41:39 PM UTC 24 |
Sep 01 12:42:02 PM UTC 24 |
1117489078 ps |
| T803 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.899191852 |
|
|
Sep 01 12:41:53 PM UTC 24 |
Sep 01 12:42:03 PM UTC 24 |
1318670270 ps |
| T804 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1408407583 |
|
|
Sep 01 12:41:59 PM UTC 24 |
Sep 01 12:42:04 PM UTC 24 |
107562711 ps |
| T805 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2244708492 |
|
|
Sep 01 12:41:51 PM UTC 24 |
Sep 01 12:42:04 PM UTC 24 |
1176759629 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.1965344895 |
|
|
Sep 01 12:41:55 PM UTC 24 |
Sep 01 12:42:06 PM UTC 24 |
276354842 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.1255379766 |
|
|
Sep 01 12:42:02 PM UTC 24 |
Sep 01 12:42:08 PM UTC 24 |
474146044 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.1875907071 |
|
|
Sep 01 12:41:53 PM UTC 24 |
Sep 01 12:42:09 PM UTC 24 |
730901987 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.213196498 |
|
|
Sep 01 12:42:04 PM UTC 24 |
Sep 01 12:42:09 PM UTC 24 |
430191676 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2482925517 |
|
|
Sep 01 12:41:55 PM UTC 24 |
Sep 01 12:42:11 PM UTC 24 |
1738772556 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2288882875 |
|
|
Sep 01 12:42:10 PM UTC 24 |
Sep 01 12:42:12 PM UTC 24 |
80587988 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.1196167478 |
|
|
Sep 01 12:42:02 PM UTC 24 |
Sep 01 12:42:13 PM UTC 24 |
75389008 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2232451162 |
|
|
Sep 01 12:41:57 PM UTC 24 |
Sep 01 12:42:14 PM UTC 24 |
384307372 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.224000472 |
|
|
Sep 01 12:42:13 PM UTC 24 |
Sep 01 12:42:15 PM UTC 24 |
30420199 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.1849256160 |
|
|
Sep 01 12:42:12 PM UTC 24 |
Sep 01 12:42:16 PM UTC 24 |
104879024 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2270974139 |
|
|
Sep 01 12:41:21 PM UTC 24 |
Sep 01 12:42:17 PM UTC 24 |
1438395532 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.253327479 |
|
|
Sep 01 12:41:49 PM UTC 24 |
Sep 01 12:42:17 PM UTC 24 |
2143200261 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.2113650375 |
|
|
Sep 01 12:42:04 PM UTC 24 |
Sep 01 12:42:18 PM UTC 24 |
1324569921 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3676401042 |
|
|
Sep 01 12:42:06 PM UTC 24 |
Sep 01 12:42:19 PM UTC 24 |
1028866939 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.3855477991 |
|
|
Sep 01 12:40:13 PM UTC 24 |
Sep 01 12:42:19 PM UTC 24 |
3715216322 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.1136511322 |
|
|
Sep 01 12:41:47 PM UTC 24 |
Sep 01 12:42:19 PM UTC 24 |
148086676 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2323910275 |
|
|
Sep 01 12:42:14 PM UTC 24 |
Sep 01 12:42:19 PM UTC 24 |
49474348 ps |