| T822 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2155289097 |
|
|
Sep 01 12:42:18 PM UTC 24 |
Sep 01 12:42:22 PM UTC 24 |
149159572 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3975098605 |
|
|
Sep 01 12:42:17 PM UTC 24 |
Sep 01 12:42:23 PM UTC 24 |
370950248 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.557526187 |
|
|
Sep 01 12:39:24 PM UTC 24 |
Sep 01 12:42:23 PM UTC 24 |
17078951210 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1923023728 |
|
|
Sep 01 12:42:08 PM UTC 24 |
Sep 01 12:42:23 PM UTC 24 |
395710931 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.2493336861 |
|
|
Sep 01 12:42:02 PM UTC 24 |
Sep 01 12:42:24 PM UTC 24 |
197992978 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.3009376668 |
|
|
Sep 01 12:42:23 PM UTC 24 |
Sep 01 12:42:25 PM UTC 24 |
35142029 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.191589265 |
|
|
Sep 01 12:42:24 PM UTC 24 |
Sep 01 12:42:27 PM UTC 24 |
24312825 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3385422222 |
|
|
Sep 01 12:40:26 PM UTC 24 |
Sep 01 12:42:27 PM UTC 24 |
16067171764 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.224257025 |
|
|
Sep 01 12:42:03 PM UTC 24 |
Sep 01 12:42:27 PM UTC 24 |
349302187 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.2105245244 |
|
|
Sep 01 12:42:04 PM UTC 24 |
Sep 01 12:42:28 PM UTC 24 |
3424129890 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1383640725 |
|
|
Sep 01 12:42:24 PM UTC 24 |
Sep 01 12:42:28 PM UTC 24 |
24181214 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2665732208 |
|
|
Sep 01 12:41:16 PM UTC 24 |
Sep 01 12:42:28 PM UTC 24 |
2060079912 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.3405537510 |
|
|
Sep 01 12:42:18 PM UTC 24 |
Sep 01 12:42:29 PM UTC 24 |
273024030 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.1288170785 |
|
|
Sep 01 12:42:19 PM UTC 24 |
Sep 01 12:42:29 PM UTC 24 |
222263976 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.363232924 |
|
|
Sep 01 12:42:17 PM UTC 24 |
Sep 01 12:42:30 PM UTC 24 |
257406038 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.289262810 |
|
|
Sep 01 12:40:50 PM UTC 24 |
Sep 01 12:42:30 PM UTC 24 |
3531351789 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.586506118 |
|
|
Sep 01 12:42:26 PM UTC 24 |
Sep 01 12:42:32 PM UTC 24 |
81278547 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3262204492 |
|
|
Sep 01 12:42:32 PM UTC 24 |
Sep 01 12:42:34 PM UTC 24 |
76568892 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1407748553 |
|
|
Sep 01 12:42:38 PM UTC 24 |
Sep 01 12:42:57 PM UTC 24 |
423337819 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.165268831 |
|
|
Sep 01 12:42:33 PM UTC 24 |
Sep 01 12:42:35 PM UTC 24 |
68232927 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.1192871668 |
|
|
Sep 01 12:42:28 PM UTC 24 |
Sep 01 12:42:35 PM UTC 24 |
1770022762 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.1793137849 |
|
|
Sep 01 12:42:32 PM UTC 24 |
Sep 01 12:42:37 PM UTC 24 |
239076973 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.1278386796 |
|
|
Sep 01 12:42:28 PM UTC 24 |
Sep 01 12:42:38 PM UTC 24 |
1865204989 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.263235561 |
|
|
Sep 01 12:42:19 PM UTC 24 |
Sep 01 12:42:38 PM UTC 24 |
2615339026 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.2909848229 |
|
|
Sep 01 12:42:09 PM UTC 24 |
Sep 01 12:42:39 PM UTC 24 |
3769332633 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.586966430 |
|
|
Sep 01 12:42:21 PM UTC 24 |
Sep 01 12:42:39 PM UTC 24 |
377395098 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.3915341807 |
|
|
Sep 01 12:42:36 PM UTC 24 |
Sep 01 12:42:41 PM UTC 24 |
231161298 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.3369781894 |
|
|
Sep 01 12:42:26 PM UTC 24 |
Sep 01 12:42:42 PM UTC 24 |
88402907 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1375543741 |
|
|
Sep 01 12:41:03 PM UTC 24 |
Sep 01 12:42:43 PM UTC 24 |
6778420960 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.1125706532 |
|
|
Sep 01 12:42:38 PM UTC 24 |
Sep 01 12:42:45 PM UTC 24 |
259560268 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2944613820 |
|
|
Sep 01 12:42:30 PM UTC 24 |
Sep 01 12:42:45 PM UTC 24 |
487320984 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.1114027822 |
|
|
Sep 01 12:42:30 PM UTC 24 |
Sep 01 12:42:45 PM UTC 24 |
3605158356 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.2157534786 |
|
|
Sep 01 12:42:28 PM UTC 24 |
Sep 01 12:42:46 PM UTC 24 |
360806681 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.2324801031 |
|
|
Sep 01 12:42:45 PM UTC 24 |
Sep 01 12:42:47 PM UTC 24 |
88523930 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4048435255 |
|
|
Sep 01 12:42:46 PM UTC 24 |
Sep 01 12:42:48 PM UTC 24 |
14150033 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2081141987 |
|
|
Sep 01 12:42:14 PM UTC 24 |
Sep 01 12:42:49 PM UTC 24 |
287171411 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.3760677307 |
|
|
Sep 01 12:39:04 PM UTC 24 |
Sep 01 12:42:49 PM UTC 24 |
6307888619 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.3987036265 |
|
|
Sep 01 12:42:28 PM UTC 24 |
Sep 01 12:42:50 PM UTC 24 |
344797899 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.4269830374 |
|
|
Sep 01 12:42:36 PM UTC 24 |
Sep 01 12:42:51 PM UTC 24 |
127286589 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.2007213456 |
|
|
Sep 01 12:42:47 PM UTC 24 |
Sep 01 12:42:51 PM UTC 24 |
28137774 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.1145326595 |
|
|
Sep 01 12:42:36 PM UTC 24 |
Sep 01 12:42:52 PM UTC 24 |
945840455 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.2585074785 |
|
|
Sep 01 12:42:45 PM UTC 24 |
Sep 01 12:42:52 PM UTC 24 |
285579281 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.2171029411 |
|
|
Sep 01 12:42:41 PM UTC 24 |
Sep 01 12:42:53 PM UTC 24 |
279000030 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.2973515486 |
|
|
Sep 01 12:42:41 PM UTC 24 |
Sep 01 12:42:53 PM UTC 24 |
927515519 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.3178443130 |
|
|
Sep 01 12:42:30 PM UTC 24 |
Sep 01 12:42:54 PM UTC 24 |
533559298 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.695094859 |
|
|
Sep 01 12:41:03 PM UTC 24 |
Sep 01 12:42:59 PM UTC 24 |
5553390839 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.1905857898 |
|
|
Sep 01 12:42:40 PM UTC 24 |
Sep 01 12:43:00 PM UTC 24 |
1941629415 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.4119368043 |
|
|
Sep 01 12:42:48 PM UTC 24 |
Sep 01 12:43:01 PM UTC 24 |
1010328614 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.1059156408 |
|
|
Sep 01 12:42:47 PM UTC 24 |
Sep 01 12:43:05 PM UTC 24 |
70624249 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1411079853 |
|
|
Sep 01 12:42:51 PM UTC 24 |
Sep 01 12:43:05 PM UTC 24 |
2062029495 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.264264433 |
|
|
Sep 01 12:42:49 PM UTC 24 |
Sep 01 12:43:07 PM UTC 24 |
986770386 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3819985564 |
|
|
Sep 01 12:42:24 PM UTC 24 |
Sep 01 12:43:12 PM UTC 24 |
1108567850 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.3113053422 |
|
|
Sep 01 12:42:51 PM UTC 24 |
Sep 01 12:43:12 PM UTC 24 |
3705746317 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.716740169 |
|
|
Sep 01 12:42:50 PM UTC 24 |
Sep 01 12:43:12 PM UTC 24 |
569884513 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.782928942 |
|
|
Sep 01 12:42:47 PM UTC 24 |
Sep 01 12:43:13 PM UTC 24 |
751581722 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.2776812769 |
|
|
Sep 01 12:42:52 PM UTC 24 |
Sep 01 12:43:14 PM UTC 24 |
795808895 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.3356551890 |
|
|
Sep 01 12:42:35 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
3964331156 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.196976672 |
|
|
Sep 01 12:41:41 PM UTC 24 |
Sep 01 12:43:37 PM UTC 24 |
2195355218 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3172705383 |
|
|
Sep 01 12:41:56 PM UTC 24 |
Sep 01 12:43:39 PM UTC 24 |
10832484012 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.842236290 |
|
|
Sep 01 12:42:10 PM UTC 24 |
Sep 01 12:43:47 PM UTC 24 |
8072457397 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.4033205755 |
|
|
Sep 01 12:42:21 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
9516582468 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1319796431 |
|
|
Sep 01 12:40:39 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
43184201265 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2921074745 |
|
|
Sep 01 12:41:43 PM UTC 24 |
Sep 01 12:44:02 PM UTC 24 |
8115847813 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2031843432 |
|
|
Sep 01 12:40:00 PM UTC 24 |
Sep 01 12:44:04 PM UTC 24 |
44030905461 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.83828498 |
|
|
Sep 01 12:42:52 PM UTC 24 |
Sep 01 12:44:48 PM UTC 24 |
6727731438 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.3176147461 |
|
|
Sep 01 12:41:26 PM UTC 24 |
Sep 01 12:45:05 PM UTC 24 |
15407631524 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.2053750581 |
|
|
Sep 01 12:40:25 PM UTC 24 |
Sep 01 12:45:18 PM UTC 24 |
9490389187 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4116177292 |
|
|
Sep 01 12:42:52 PM UTC 24 |
Sep 01 12:45:29 PM UTC 24 |
16530674840 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2562667105 |
|
|
Sep 01 12:37:39 PM UTC 24 |
Sep 01 12:45:56 PM UTC 24 |
29382340664 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.447538962 |
|
|
Sep 01 12:42:42 PM UTC 24 |
Sep 01 12:46:45 PM UTC 24 |
8810387882 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.1215283655 |
|
|
Sep 01 12:42:21 PM UTC 24 |
Sep 01 12:46:45 PM UTC 24 |
6251052313 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.3842753613 |
|
|
Sep 01 12:39:11 PM UTC 24 |
Sep 01 12:49:12 PM UTC 24 |
16469820170 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3281544015 |
|
|
Sep 01 12:42:55 PM UTC 24 |
Sep 01 12:42:58 PM UTC 24 |
51966195 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3802700381 |
|
|
Sep 01 12:42:55 PM UTC 24 |
Sep 01 12:43:00 PM UTC 24 |
449512387 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3744664997 |
|
|
Sep 01 12:42:58 PM UTC 24 |
Sep 01 12:43:01 PM UTC 24 |
24305879 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3785110723 |
|
|
Sep 01 12:43:00 PM UTC 24 |
Sep 01 12:43:02 PM UTC 24 |
21553101 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2564525140 |
|
|
Sep 01 12:43:02 PM UTC 24 |
Sep 01 12:43:04 PM UTC 24 |
34147737 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.411314630 |
|
|
Sep 01 12:43:02 PM UTC 24 |
Sep 01 12:43:04 PM UTC 24 |
58904781 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.464919470 |
|
|
Sep 01 12:42:59 PM UTC 24 |
Sep 01 12:43:05 PM UTC 24 |
224133712 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2974253164 |
|
|
Sep 01 12:43:01 PM UTC 24 |
Sep 01 12:43:06 PM UTC 24 |
895297028 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1101599742 |
|
|
Sep 01 12:43:03 PM UTC 24 |
Sep 01 12:43:07 PM UTC 24 |
200298845 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.306184404 |
|
|
Sep 01 12:43:02 PM UTC 24 |
Sep 01 12:43:07 PM UTC 24 |
396619219 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2476377818 |
|
|
Sep 01 12:43:05 PM UTC 24 |
Sep 01 12:43:08 PM UTC 24 |
16623285 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.85204714 |
|
|
Sep 01 12:42:56 PM UTC 24 |
Sep 01 12:43:08 PM UTC 24 |
973270941 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1956765821 |
|
|
Sep 01 12:43:05 PM UTC 24 |
Sep 01 12:43:08 PM UTC 24 |
70731367 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1492111316 |
|
|
Sep 01 12:43:06 PM UTC 24 |
Sep 01 12:43:09 PM UTC 24 |
67317555 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3806526529 |
|
|
Sep 01 12:43:07 PM UTC 24 |
Sep 01 12:43:10 PM UTC 24 |
367538518 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4094810625 |
|
|
Sep 01 12:43:08 PM UTC 24 |
Sep 01 12:43:10 PM UTC 24 |
60345332 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1223249294 |
|
|
Sep 01 12:43:09 PM UTC 24 |
Sep 01 12:43:12 PM UTC 24 |
70726454 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.916442060 |
|
|
Sep 01 12:43:08 PM UTC 24 |
Sep 01 12:43:12 PM UTC 24 |
167960287 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3942483456 |
|
|
Sep 01 12:43:10 PM UTC 24 |
Sep 01 12:43:13 PM UTC 24 |
62152931 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.4178290604 |
|
|
Sep 01 12:43:09 PM UTC 24 |
Sep 01 12:43:13 PM UTC 24 |
64507341 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2252881161 |
|
|
Sep 01 12:43:11 PM UTC 24 |
Sep 01 12:43:13 PM UTC 24 |
42040913 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1849211529 |
|
|
Sep 01 12:43:09 PM UTC 24 |
Sep 01 12:43:15 PM UTC 24 |
88966161 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2637700555 |
|
|
Sep 01 12:43:13 PM UTC 24 |
Sep 01 12:43:15 PM UTC 24 |
22228370 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1949944804 |
|
|
Sep 01 12:43:11 PM UTC 24 |
Sep 01 12:43:15 PM UTC 24 |
141118088 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3272752175 |
|
|
Sep 01 12:43:13 PM UTC 24 |
Sep 01 12:43:16 PM UTC 24 |
70296917 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.912470547 |
|
|
Sep 01 12:42:57 PM UTC 24 |
Sep 01 12:43:16 PM UTC 24 |
4328549308 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.552808729 |
|
|
Sep 01 12:43:13 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
192696720 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2071649463 |
|
|
Sep 01 12:43:14 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
59678031 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1608648366 |
|
|
Sep 01 12:43:15 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
17912519 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1685984906 |
|
|
Sep 01 12:43:06 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
264381964 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3737987363 |
|
|
Sep 01 12:43:13 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
1482565682 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.718725491 |
|
|
Sep 01 12:43:07 PM UTC 24 |
Sep 01 12:43:17 PM UTC 24 |
2590730623 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1909708437 |
|
|
Sep 01 12:43:16 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
85795531 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2423676104 |
|
|
Sep 01 12:43:08 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
340812447 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.100109293 |
|
|
Sep 01 12:43:16 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
91231229 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1838035733 |
|
|
Sep 01 12:43:13 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
192930059 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.139951073 |
|
|
Sep 01 12:43:16 PM UTC 24 |
Sep 01 12:43:18 PM UTC 24 |
21605535 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2203009633 |
|
|
Sep 01 12:43:14 PM UTC 24 |
Sep 01 12:43:19 PM UTC 24 |
395972425 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3747815167 |
|
|
Sep 01 12:43:17 PM UTC 24 |
Sep 01 12:43:19 PM UTC 24 |
19345120 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1187257260 |
|
|
Sep 01 12:43:17 PM UTC 24 |
Sep 01 12:43:20 PM UTC 24 |
54439902 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3394782549 |
|
|
Sep 01 12:43:17 PM UTC 24 |
Sep 01 12:43:20 PM UTC 24 |
93374844 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2019896600 |
|
|
Sep 01 12:43:16 PM UTC 24 |
Sep 01 12:43:21 PM UTC 24 |
108103029 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1370585186 |
|
|
Sep 01 12:43:19 PM UTC 24 |
Sep 01 12:43:21 PM UTC 24 |
88917364 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2710749983 |
|
|
Sep 01 12:43:18 PM UTC 24 |
Sep 01 12:43:22 PM UTC 24 |
29219313 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.136778355 |
|
|
Sep 01 12:43:18 PM UTC 24 |
Sep 01 12:43:22 PM UTC 24 |
87995857 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.433499072 |
|
|
Sep 01 12:43:19 PM UTC 24 |
Sep 01 12:43:23 PM UTC 24 |
158499663 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.144854203 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:23 PM UTC 24 |
47750343 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3209276650 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:23 PM UTC 24 |
108720200 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2409259268 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:23 PM UTC 24 |
36201054 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1560884830 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:23 PM UTC 24 |
87528571 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1766848172 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:24 PM UTC 24 |
52670495 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1919477499 |
|
|
Sep 01 12:43:21 PM UTC 24 |
Sep 01 12:43:24 PM UTC 24 |
176659546 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2643093956 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:24 PM UTC 24 |
87728001 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.42177954 |
|
|
Sep 01 12:43:19 PM UTC 24 |
Sep 01 12:43:25 PM UTC 24 |
167960089 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.243250901 |
|
|
Sep 01 12:43:22 PM UTC 24 |
Sep 01 12:43:25 PM UTC 24 |
80060083 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.35085127 |
|
|
Sep 01 12:43:22 PM UTC 24 |
Sep 01 12:43:26 PM UTC 24 |
158424784 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3034473141 |
|
|
Sep 01 12:43:14 PM UTC 24 |
Sep 01 12:43:26 PM UTC 24 |
741545424 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2627032722 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
30646635 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1118643750 |
|
|
Sep 01 12:43:23 PM UTC 24 |
Sep 01 12:43:26 PM UTC 24 |
75539982 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.3770063478 |
|
|
Sep 01 12:43:20 PM UTC 24 |
Sep 01 12:43:27 PM UTC 24 |
110942847 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1641341417 |
|
|
Sep 01 12:43:24 PM UTC 24 |
Sep 01 12:43:28 PM UTC 24 |
269726072 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.468770601 |
|
|
Sep 01 12:43:24 PM UTC 24 |
Sep 01 12:43:28 PM UTC 24 |
261727355 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2775473598 |
|
|
Sep 01 12:43:23 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
693632613 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.666946247 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
18107741 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.890055002 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
61497851 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3582807178 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
37611043 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.444925570 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:29 PM UTC 24 |
251019498 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2261828011 |
|
|
Sep 01 12:43:26 PM UTC 24 |
Sep 01 12:43:30 PM UTC 24 |
205597122 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1203862655 |
|
|
Sep 01 12:43:23 PM UTC 24 |
Sep 01 12:43:30 PM UTC 24 |
2944007730 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.669866701 |
|
|
Sep 01 12:43:24 PM UTC 24 |
Sep 01 12:43:30 PM UTC 24 |
100855531 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3551495372 |
|
|
Sep 01 12:43:27 PM UTC 24 |
Sep 01 12:43:31 PM UTC 24 |
378976403 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.308951129 |
|
|
Sep 01 12:43:27 PM UTC 24 |
Sep 01 12:43:31 PM UTC 24 |
35788793 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.447826002 |
|
|
Sep 01 12:43:27 PM UTC 24 |
Sep 01 12:43:31 PM UTC 24 |
79819068 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.493810169 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:32 PM UTC 24 |
41991075 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3792985938 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:33 PM UTC 24 |
260471429 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2784429194 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:33 PM UTC 24 |
181219121 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3358878887 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:33 PM UTC 24 |
236092067 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.513367744 |
|
|
Sep 01 12:43:31 PM UTC 24 |
Sep 01 12:43:34 PM UTC 24 |
14646299 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.4081471509 |
|
|
Sep 01 12:43:31 PM UTC 24 |
Sep 01 12:43:35 PM UTC 24 |
32573384 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.648882395 |
|
|
Sep 01 12:43:32 PM UTC 24 |
Sep 01 12:43:35 PM UTC 24 |
498514247 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3932170707 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:35 PM UTC 24 |
118813998 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2571796729 |
|
|
Sep 01 12:43:31 PM UTC 24 |
Sep 01 12:43:35 PM UTC 24 |
176945766 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3915262858 |
|
|
Sep 01 12:43:30 PM UTC 24 |
Sep 01 12:43:36 PM UTC 24 |
204634605 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1260866488 |
|
|
Sep 01 12:43:33 PM UTC 24 |
Sep 01 12:43:36 PM UTC 24 |
66578724 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3622100667 |
|
|
Sep 01 12:43:34 PM UTC 24 |
Sep 01 12:43:37 PM UTC 24 |
56880869 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1961183357 |
|
|
Sep 01 12:43:35 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
31857325 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3092557936 |
|
|
Sep 01 12:43:29 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
191003543 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1954044642 |
|
|
Sep 01 12:43:35 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
92756585 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2817508842 |
|
|
Sep 01 12:43:19 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
4120312991 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1160736163 |
|
|
Sep 01 12:43:35 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
20065607 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2354430897 |
|
|
Sep 01 12:43:34 PM UTC 24 |
Sep 01 12:43:38 PM UTC 24 |
1939300551 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2398166383 |
|
|
Sep 01 12:43:34 PM UTC 24 |
Sep 01 12:43:39 PM UTC 24 |
322553087 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.290635182 |
|
|
Sep 01 12:43:34 PM UTC 24 |
Sep 01 12:43:40 PM UTC 24 |
413250166 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2903195048 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:43:59 PM UTC 24 |
120605527 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3536663950 |
|
|
Sep 01 12:43:37 PM UTC 24 |
Sep 01 12:43:40 PM UTC 24 |
239632842 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2821036333 |
|
|
Sep 01 12:43:37 PM UTC 24 |
Sep 01 12:43:41 PM UTC 24 |
170007513 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2642037976 |
|
|
Sep 01 12:43:38 PM UTC 24 |
Sep 01 12:43:41 PM UTC 24 |
44001708 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2619342213 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:42 PM UTC 24 |
35384915 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1758978563 |
|
|
Sep 01 12:43:38 PM UTC 24 |
Sep 01 12:43:43 PM UTC 24 |
198308808 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3018024547 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:43 PM UTC 24 |
32771728 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1878182969 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:43 PM UTC 24 |
60704318 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474559930 |
|
|
Sep 01 12:43:38 PM UTC 24 |
Sep 01 12:43:43 PM UTC 24 |
752417900 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4176378427 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:44 PM UTC 24 |
92860282 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.481741155 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:44 PM UTC 24 |
125727994 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.301042391 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:45 PM UTC 24 |
59616812 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1830222306 |
|
|
Sep 01 12:43:41 PM UTC 24 |
Sep 01 12:43:45 PM UTC 24 |
87612156 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.76154216 |
|
|
Sep 01 12:43:44 PM UTC 24 |
Sep 01 12:43:46 PM UTC 24 |
16090731 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3490356194 |
|
|
Sep 01 12:43:40 PM UTC 24 |
Sep 01 12:43:47 PM UTC 24 |
242758329 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3942913666 |
|
|
Sep 01 12:43:44 PM UTC 24 |
Sep 01 12:43:47 PM UTC 24 |
181006939 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1588936785 |
|
|
Sep 01 12:43:27 PM UTC 24 |
Sep 01 12:43:47 PM UTC 24 |
2773939459 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3977602445 |
|
|
Sep 01 12:43:44 PM UTC 24 |
Sep 01 12:43:47 PM UTC 24 |
36418902 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1102321315 |
|
|
Sep 01 12:43:44 PM UTC 24 |
Sep 01 12:43:48 PM UTC 24 |
179378494 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3074756789 |
|
|
Sep 01 12:43:45 PM UTC 24 |
Sep 01 12:43:48 PM UTC 24 |
40607648 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4087631701 |
|
|
Sep 01 12:43:37 PM UTC 24 |
Sep 01 12:43:48 PM UTC 24 |
1509394800 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.424842050 |
|
|
Sep 01 12:43:44 PM UTC 24 |
Sep 01 12:43:48 PM UTC 24 |
59453907 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3954458817 |
|
|
Sep 01 12:43:43 PM UTC 24 |
Sep 01 12:43:48 PM UTC 24 |
423219256 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1076798288 |
|
|
Sep 01 12:43:32 PM UTC 24 |
Sep 01 12:43:49 PM UTC 24 |
1515694432 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2772842900 |
|
|
Sep 01 12:43:45 PM UTC 24 |
Sep 01 12:43:49 PM UTC 24 |
72698056 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4052389011 |
|
|
Sep 01 12:43:45 PM UTC 24 |
Sep 01 12:43:49 PM UTC 24 |
66169540 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3121127875 |
|
|
Sep 01 12:43:19 PM UTC 24 |
Sep 01 12:43:49 PM UTC 24 |
3776662246 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.901701540 |
|
|
Sep 01 12:43:23 PM UTC 24 |
Sep 01 12:43:50 PM UTC 24 |
16567651744 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.221958771 |
|
|
Sep 01 12:43:14 PM UTC 24 |
Sep 01 12:43:50 PM UTC 24 |
1523730807 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.609802387 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:50 PM UTC 24 |
58859991 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3827125478 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:51 PM UTC 24 |
26862757 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1020683165 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:51 PM UTC 24 |
86315065 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3897927273 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:52 PM UTC 24 |
16943410 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2475522519 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:52 PM UTC 24 |
23718080 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.475895652 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:52 PM UTC 24 |
43828673 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3169601836 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:52 PM UTC 24 |
287747755 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2335519349 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:52 PM UTC 24 |
52635127 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2486459237 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:53 PM UTC 24 |
72492344 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1898131008 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
11913555 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2084578481 |
|
|
Sep 01 12:43:47 PM UTC 24 |
Sep 01 12:43:53 PM UTC 24 |
3868889070 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1374544884 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
241907950 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1172166430 |
|
|
Sep 01 12:43:51 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
47524805 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1053384130 |
|
|
Sep 01 12:43:32 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
1026572526 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.736527546 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
337189617 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3587077964 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
683275225 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1028377563 |
|
|
Sep 01 12:43:51 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
131791216 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4197761518 |
|
|
Sep 01 12:43:50 PM UTC 24 |
Sep 01 12:43:54 PM UTC 24 |
296095421 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.350292031 |
|
|
Sep 01 12:43:51 PM UTC 24 |
Sep 01 12:43:55 PM UTC 24 |
20068947 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4043925953 |
|
|
Sep 01 12:43:48 PM UTC 24 |
Sep 01 12:43:55 PM UTC 24 |
134960518 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.863366937 |
|
|
Sep 01 12:43:51 PM UTC 24 |
Sep 01 12:43:55 PM UTC 24 |
523848475 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.320464528 |
|
|
Sep 01 12:43:41 PM UTC 24 |
Sep 01 12:43:56 PM UTC 24 |
974594732 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3895185805 |
|
|
Sep 01 12:43:53 PM UTC 24 |
Sep 01 12:43:56 PM UTC 24 |
14620078 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3818003037 |
|
|
Sep 01 12:43:53 PM UTC 24 |
Sep 01 12:43:56 PM UTC 24 |
35408953 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2650169568 |
|
|
Sep 01 12:43:52 PM UTC 24 |
Sep 01 12:43:56 PM UTC 24 |
138867407 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1870599698 |
|
|
Sep 01 12:43:53 PM UTC 24 |
Sep 01 12:43:56 PM UTC 24 |
21216880 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.336092539 |
|
|
Sep 01 12:43:53 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
242907732 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.936617642 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
38557399 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3289070744 |
|
|
Sep 01 12:43:53 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
30347556 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3247799219 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:43:57 PM UTC 24 |
63265832 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2752125818 |
|
|
Sep 01 12:43:41 PM UTC 24 |
Sep 01 12:43:58 PM UTC 24 |
447938864 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3292736179 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:43:58 PM UTC 24 |
33127898 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.818070550 |
|
|
Sep 01 12:43:37 PM UTC 24 |
Sep 01 12:43:58 PM UTC 24 |
4268875699 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.100985623 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
12599052 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2019348190 |
|
|
Sep 01 12:43:57 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
26951094 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3495516686 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
50912783 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.4100542010 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
20144570 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2481895281 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
100173884 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2258263419 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:44:00 PM UTC 24 |
357911596 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2962422013 |
|
|
Sep 01 12:43:55 PM UTC 24 |
Sep 01 12:44:01 PM UTC 24 |
337706781 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2200899434 |
|
|
Sep 01 12:43:57 PM UTC 24 |
Sep 01 12:44:01 PM UTC 24 |
27102138 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2801685380 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:01 PM UTC 24 |
27355538 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4037325526 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:01 PM UTC 24 |
106627916 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1925005474 |
|
|
Sep 01 12:43:57 PM UTC 24 |
Sep 01 12:44:02 PM UTC 24 |
462692593 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1683838792 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:02 PM UTC 24 |
449880113 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3940930670 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:02 PM UTC 24 |
34982219 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2371763981 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
16138237 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1948892834 |
|
|
Sep 01 12:43:57 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
653394449 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.987969822 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
24830639 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3781305407 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
60213557 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3595258741 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
148244554 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2155885950 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:03 PM UTC 24 |
165276184 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1352501295 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:04 PM UTC 24 |
190143944 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.173332953 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:04 PM UTC 24 |
459942494 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2760653421 |
|
|
Sep 01 12:43:58 PM UTC 24 |
Sep 01 12:44:04 PM UTC 24 |
154376208 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2101415783 |
|
|
Sep 01 12:44:00 PM UTC 24 |
Sep 01 12:44:04 PM UTC 24 |
68782903 ps |