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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.92 95.29 93.40 100.00 98.52 99.00 96.11


Total test records in report: 1001
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T376 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2615074602 Sep 11 08:06:43 AM UTC 24 Sep 11 08:06:50 AM UTC 24 71819234 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1194082464 Sep 11 08:06:46 AM UTC 24 Sep 11 08:06:52 AM UTC 24 107223364 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1686954684 Sep 11 08:05:52 AM UTC 24 Sep 11 08:06:54 AM UTC 24 4783151570 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2063632530 Sep 11 08:06:35 AM UTC 24 Sep 11 08:06:54 AM UTC 24 349718922 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1355196540 Sep 11 08:02:15 AM UTC 24 Sep 11 08:06:55 AM UTC 24 7136830988 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1492968508 Sep 11 08:05:32 AM UTC 24 Sep 11 08:06:56 AM UTC 24 14342220899 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3230920708 Sep 11 08:06:51 AM UTC 24 Sep 11 08:06:56 AM UTC 24 159346621 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3629140999 Sep 11 08:06:24 AM UTC 24 Sep 11 08:06:58 AM UTC 24 303147606 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2980748014 Sep 11 08:06:57 AM UTC 24 Sep 11 08:07:00 AM UTC 24 105379482 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.443830748 Sep 11 08:06:45 AM UTC 24 Sep 11 08:07:01 AM UTC 24 298314098 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.916485268 Sep 11 08:06:11 AM UTC 24 Sep 11 08:07:01 AM UTC 24 7865819915 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3607640523 Sep 11 08:06:59 AM UTC 24 Sep 11 08:07:02 AM UTC 24 45173082 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3346476925 Sep 11 08:06:59 AM UTC 24 Sep 11 08:07:03 AM UTC 24 110661084 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3114063495 Sep 11 08:06:55 AM UTC 24 Sep 11 08:07:05 AM UTC 24 1023645886 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2489270985 Sep 11 08:06:29 AM UTC 24 Sep 11 08:07:05 AM UTC 24 19416407578 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1085430276 Sep 11 08:06:45 AM UTC 24 Sep 11 08:07:05 AM UTC 24 603073050 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.3873175713 Sep 11 08:06:55 AM UTC 24 Sep 11 08:07:06 AM UTC 24 245020675 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1111664940 Sep 11 08:06:07 AM UTC 24 Sep 11 08:07:06 AM UTC 24 507621964 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.4204379483 Sep 11 08:06:48 AM UTC 24 Sep 11 08:07:06 AM UTC 24 1550970075 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3083225119 Sep 11 08:06:54 AM UTC 24 Sep 11 08:07:07 AM UTC 24 200971603 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1445795840 Sep 11 08:06:32 AM UTC 24 Sep 11 08:07:07 AM UTC 24 782040503 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.662513446 Sep 11 08:07:03 AM UTC 24 Sep 11 08:07:07 AM UTC 24 208741689 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1688299885 Sep 11 08:06:53 AM UTC 24 Sep 11 08:07:10 AM UTC 24 630552368 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.568308217 Sep 11 08:07:05 AM UTC 24 Sep 11 08:07:11 AM UTC 24 103513768 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.1166146453 Sep 11 08:06:42 AM UTC 24 Sep 11 08:07:11 AM UTC 24 174064416 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.773437383 Sep 11 08:07:03 AM UTC 24 Sep 11 08:07:13 AM UTC 24 1057895221 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3330450447 Sep 11 08:07:07 AM UTC 24 Sep 11 08:07:13 AM UTC 24 694321662 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3538536237 Sep 11 08:07:02 AM UTC 24 Sep 11 08:07:14 AM UTC 24 1172987756 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2949691821 Sep 11 08:07:12 AM UTC 24 Sep 11 08:07:14 AM UTC 24 54914065 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2634455346 Sep 11 08:07:12 AM UTC 24 Sep 11 08:07:15 AM UTC 24 41669966 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3254851721 Sep 11 08:07:13 AM UTC 24 Sep 11 08:07:16 AM UTC 24 19089156 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.488378100 Sep 11 08:07:08 AM UTC 24 Sep 11 08:07:16 AM UTC 24 308614651 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3270432043 Sep 11 08:07:08 AM UTC 24 Sep 11 08:07:19 AM UTC 24 446181467 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3033659897 Sep 11 08:07:08 AM UTC 24 Sep 11 08:07:19 AM UTC 24 1597343598 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1381440733 Sep 11 08:04:31 AM UTC 24 Sep 11 08:07:19 AM UTC 24 13763278183 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1795664825 Sep 11 08:07:15 AM UTC 24 Sep 11 08:07:19 AM UTC 24 29884565 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1387061111 Sep 11 08:07:03 AM UTC 24 Sep 11 08:07:20 AM UTC 24 522747843 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.300113308 Sep 11 08:07:14 AM UTC 24 Sep 11 08:07:20 AM UTC 24 49502076 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2052415981 Sep 11 08:07:08 AM UTC 24 Sep 11 08:07:22 AM UTC 24 315614335 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.663970215 Sep 11 08:07:17 AM UTC 24 Sep 11 08:07:24 AM UTC 24 610246637 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1674752399 Sep 11 08:07:07 AM UTC 24 Sep 11 08:07:27 AM UTC 24 1733252257 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3599825258 Sep 11 08:07:15 AM UTC 24 Sep 11 08:07:31 AM UTC 24 284152280 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.923031158 Sep 11 08:07:23 AM UTC 24 Sep 11 08:07:31 AM UTC 24 904458317 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.312451022 Sep 11 08:07:21 AM UTC 24 Sep 11 08:07:31 AM UTC 24 203540385 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1750225483 Sep 11 08:07:20 AM UTC 24 Sep 11 08:07:32 AM UTC 24 259202319 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.837378234 Sep 11 08:07:17 AM UTC 24 Sep 11 08:07:32 AM UTC 24 333032019 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3250709628 Sep 11 08:05:34 AM UTC 24 Sep 11 08:07:33 AM UTC 24 3160273003 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3322316658 Sep 11 08:06:51 AM UTC 24 Sep 11 08:07:34 AM UTC 24 5112425126 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.40275286 Sep 11 08:07:32 AM UTC 24 Sep 11 08:07:34 AM UTC 24 14125313 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2630414806 Sep 11 08:07:33 AM UTC 24 Sep 11 08:07:36 AM UTC 24 62260375 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.360585907 Sep 11 08:05:18 AM UTC 24 Sep 11 08:07:37 AM UTC 24 14832006176 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.789031439 Sep 11 08:07:32 AM UTC 24 Sep 11 08:07:38 AM UTC 24 631137706 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2850289624 Sep 11 08:07:36 AM UTC 24 Sep 11 08:07:42 AM UTC 24 192048178 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.68795014 Sep 11 08:07:01 AM UTC 24 Sep 11 08:07:44 AM UTC 24 666581574 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.4213301085 Sep 11 08:07:25 AM UTC 24 Sep 11 08:07:45 AM UTC 24 432008085 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3164183900 Sep 11 08:07:38 AM UTC 24 Sep 11 08:07:47 AM UTC 24 1541489406 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2067223107 Sep 11 08:07:22 AM UTC 24 Sep 11 08:07:48 AM UTC 24 726648935 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.2582039044 Sep 11 08:05:42 AM UTC 24 Sep 11 08:07:48 AM UTC 24 4208678554 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3413378910 Sep 11 08:07:46 AM UTC 24 Sep 11 08:07:49 AM UTC 24 109926978 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3325567769 Sep 11 08:07:43 AM UTC 24 Sep 11 08:07:49 AM UTC 24 255920080 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.16747602 Sep 11 08:07:35 AM UTC 24 Sep 11 08:07:51 AM UTC 24 124275821 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.345136455 Sep 11 08:07:36 AM UTC 24 Sep 11 08:07:52 AM UTC 24 634711126 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3571694536 Sep 11 08:07:20 AM UTC 24 Sep 11 08:07:52 AM UTC 24 443864724 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.3069861624 Sep 11 08:07:52 AM UTC 24 Sep 11 08:07:54 AM UTC 24 71681423 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2086058197 Sep 11 08:07:14 AM UTC 24 Sep 11 08:07:54 AM UTC 24 1231016345 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.97556174 Sep 11 08:07:53 AM UTC 24 Sep 11 08:07:55 AM UTC 24 45123568 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.836855214 Sep 11 08:07:53 AM UTC 24 Sep 11 08:07:56 AM UTC 24 79541528 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3589560101 Sep 11 08:07:07 AM UTC 24 Sep 11 08:07:58 AM UTC 24 13361208914 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.1330945598 Sep 11 08:07:37 AM UTC 24 Sep 11 08:08:00 AM UTC 24 724542757 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3979960276 Sep 11 08:07:48 AM UTC 24 Sep 11 08:08:00 AM UTC 24 398024652 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1459097380 Sep 11 08:07:55 AM UTC 24 Sep 11 08:08:01 AM UTC 24 46429745 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1495375939 Sep 11 08:07:49 AM UTC 24 Sep 11 08:08:05 AM UTC 24 1065836085 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3980817586 Sep 11 08:08:51 AM UTC 24 Sep 11 08:09:01 AM UTC 24 505324744 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3241621925 Sep 11 08:07:49 AM UTC 24 Sep 11 08:08:07 AM UTC 24 316832915 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2464972829 Sep 11 08:07:58 AM UTC 24 Sep 11 08:08:09 AM UTC 24 302537145 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2314435132 Sep 11 08:07:59 AM UTC 24 Sep 11 08:08:10 AM UTC 24 1510671761 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2347147710 Sep 11 08:07:33 AM UTC 24 Sep 11 08:08:10 AM UTC 24 291912916 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1609501603 Sep 11 08:07:58 AM UTC 24 Sep 11 08:08:11 AM UTC 24 511905719 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2520352335 Sep 11 08:07:40 AM UTC 24 Sep 11 08:08:14 AM UTC 24 798485984 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1645715640 Sep 11 08:08:12 AM UTC 24 Sep 11 08:08:15 AM UTC 24 28371938 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.164886260 Sep 11 08:08:01 AM UTC 24 Sep 11 08:08:17 AM UTC 24 333606709 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.39587101 Sep 11 08:08:08 AM UTC 24 Sep 11 08:08:17 AM UTC 24 874546669 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.1914498296 Sep 11 08:07:49 AM UTC 24 Sep 11 08:08:17 AM UTC 24 2432189209 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.977420444 Sep 11 08:06:57 AM UTC 24 Sep 11 08:08:17 AM UTC 24 6340573513 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.4068816925 Sep 11 08:08:05 AM UTC 24 Sep 11 08:08:18 AM UTC 24 633382231 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.37008907 Sep 11 08:08:16 AM UTC 24 Sep 11 08:08:18 AM UTC 24 24565221 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.383576879 Sep 11 08:05:59 AM UTC 24 Sep 11 08:08:20 AM UTC 24 13197128568 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.3516136285 Sep 11 08:08:15 AM UTC 24 Sep 11 08:08:20 AM UTC 24 288172266 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2396134658 Sep 11 08:06:26 AM UTC 24 Sep 11 08:08:20 AM UTC 24 10953293793 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.3015090905 Sep 11 08:06:36 AM UTC 24 Sep 11 08:08:22 AM UTC 24 3038369956 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3651094265 Sep 11 08:07:05 AM UTC 24 Sep 11 08:08:23 AM UTC 24 2750382389 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.4101529642 Sep 11 08:08:19 AM UTC 24 Sep 11 08:08:24 AM UTC 24 129135100 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2018258061 Sep 11 08:06:47 AM UTC 24 Sep 11 08:08:24 AM UTC 24 2235972550 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3959196355 Sep 11 08:08:18 AM UTC 24 Sep 11 08:08:25 AM UTC 24 149317209 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.315437588 Sep 11 08:08:19 AM UTC 24 Sep 11 08:08:25 AM UTC 24 255827395 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3446774233 Sep 11 08:08:01 AM UTC 24 Sep 11 08:08:25 AM UTC 24 4651024649 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1690579463 Sep 11 08:08:10 AM UTC 24 Sep 11 08:08:26 AM UTC 24 1751636268 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3424877172 Sep 11 08:08:08 AM UTC 24 Sep 11 08:08:27 AM UTC 24 403007739 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.59951607 Sep 11 08:08:26 AM UTC 24 Sep 11 08:08:28 AM UTC 24 20933261 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3155117475 Sep 11 08:08:27 AM UTC 24 Sep 11 08:08:30 AM UTC 24 24095910 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3402245378 Sep 11 08:06:57 AM UTC 24 Sep 11 08:08:31 AM UTC 24 2063303281 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1423084634 Sep 11 08:08:25 AM UTC 24 Sep 11 08:08:31 AM UTC 24 116147155 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1956932469 Sep 11 08:08:27 AM UTC 24 Sep 11 08:08:32 AM UTC 24 113071890 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.894681413 Sep 11 08:08:45 AM UTC 24 Sep 11 08:09:02 AM UTC 24 486355420 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2103334834 Sep 11 08:08:19 AM UTC 24 Sep 11 08:08:33 AM UTC 24 485836493 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3437488391 Sep 11 08:08:22 AM UTC 24 Sep 11 08:08:33 AM UTC 24 2147479410 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.333280097 Sep 11 08:08:26 AM UTC 24 Sep 11 08:08:33 AM UTC 24 185427023 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3709755788 Sep 11 08:07:20 AM UTC 24 Sep 11 08:08:33 AM UTC 24 8020352202 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.1346520078 Sep 11 08:08:19 AM UTC 24 Sep 11 08:08:34 AM UTC 24 3910991127 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.953232015 Sep 11 08:08:32 AM UTC 24 Sep 11 08:08:35 AM UTC 24 167591620 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.2516881618 Sep 11 08:07:55 AM UTC 24 Sep 11 08:08:38 AM UTC 24 1065339465 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3279129993 Sep 11 08:06:37 AM UTC 24 Sep 11 08:08:39 AM UTC 24 3815639151 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.1299543979 Sep 11 08:07:46 AM UTC 24 Sep 11 08:08:39 AM UTC 24 1381055763 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1739827223 Sep 11 08:08:01 AM UTC 24 Sep 11 08:08:40 AM UTC 24 8770090200 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3959440061 Sep 11 08:08:32 AM UTC 24 Sep 11 08:08:40 AM UTC 24 219076859 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.4175554234 Sep 11 08:08:26 AM UTC 24 Sep 11 08:08:42 AM UTC 24 295112200 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.3827764494 Sep 11 08:08:25 AM UTC 24 Sep 11 08:08:43 AM UTC 24 490815015 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.433247963 Sep 11 08:08:41 AM UTC 24 Sep 11 08:08:44 AM UTC 24 29999308 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1679867551 Sep 11 08:08:41 AM UTC 24 Sep 11 08:08:44 AM UTC 24 31425685 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.1610705531 Sep 11 08:08:32 AM UTC 24 Sep 11 08:08:45 AM UTC 24 1350087768 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2837733472 Sep 11 08:08:18 AM UTC 24 Sep 11 08:08:45 AM UTC 24 210653753 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2299764134 Sep 11 08:07:20 AM UTC 24 Sep 11 08:08:46 AM UTC 24 2734949311 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1634438901 Sep 11 08:08:31 AM UTC 24 Sep 11 08:08:46 AM UTC 24 139778925 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4089484612 Sep 11 08:07:10 AM UTC 24 Sep 11 08:08:46 AM UTC 24 5083427188 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1443942717 Sep 11 08:08:41 AM UTC 24 Sep 11 08:08:46 AM UTC 24 41716055 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3809600026 Sep 11 08:08:32 AM UTC 24 Sep 11 08:08:48 AM UTC 24 219548773 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.4092505889 Sep 11 08:08:36 AM UTC 24 Sep 11 08:08:48 AM UTC 24 324231595 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1909326213 Sep 11 08:08:34 AM UTC 24 Sep 11 08:08:50 AM UTC 24 3411090705 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3229781931 Sep 11 08:08:22 AM UTC 24 Sep 11 08:08:51 AM UTC 24 2319279945 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.605499451 Sep 11 08:08:45 AM UTC 24 Sep 11 08:08:52 AM UTC 24 78634632 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1097270756 Sep 11 08:08:01 AM UTC 24 Sep 11 08:08:52 AM UTC 24 1353497272 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.392530 Sep 11 08:08:49 AM UTC 24 Sep 11 08:08:52 AM UTC 24 205206495 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1455098423 Sep 11 08:08:39 AM UTC 24 Sep 11 08:08:53 AM UTC 24 230328334 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.123657385 Sep 11 08:08:48 AM UTC 24 Sep 11 08:08:54 AM UTC 24 227802117 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2798470609 Sep 11 08:08:35 AM UTC 24 Sep 11 08:08:54 AM UTC 24 3386422283 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3522501921 Sep 11 08:08:34 AM UTC 24 Sep 11 08:08:55 AM UTC 24 706927584 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2121497813 Sep 11 08:08:35 AM UTC 24 Sep 11 08:08:55 AM UTC 24 1637414740 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1468722216 Sep 11 08:08:53 AM UTC 24 Sep 11 08:08:56 AM UTC 24 13493550 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.1106586589 Sep 11 08:08:44 AM UTC 24 Sep 11 08:08:56 AM UTC 24 853242918 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2651484211 Sep 11 08:08:55 AM UTC 24 Sep 11 08:08:57 AM UTC 24 31094657 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2120627154 Sep 11 08:08:46 AM UTC 24 Sep 11 08:08:57 AM UTC 24 554889155 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3347467835 Sep 11 08:08:26 AM UTC 24 Sep 11 08:08:58 AM UTC 24 1813618445 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.4183581325 Sep 11 08:08:55 AM UTC 24 Sep 11 08:08:58 AM UTC 24 25687711 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2794794995 Sep 11 08:08:46 AM UTC 24 Sep 11 08:08:58 AM UTC 24 656155998 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.2200599805 Sep 11 08:08:22 AM UTC 24 Sep 11 08:09:01 AM UTC 24 26104728242 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.10897578 Sep 11 08:08:56 AM UTC 24 Sep 11 08:09:02 AM UTC 24 85933723 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.1245310614 Sep 11 08:08:49 AM UTC 24 Sep 11 08:09:02 AM UTC 24 1557822112 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.3855284421 Sep 11 08:07:39 AM UTC 24 Sep 11 08:09:03 AM UTC 24 2211872527 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.1436141412 Sep 11 08:09:02 AM UTC 24 Sep 11 08:09:04 AM UTC 24 69613465 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.4200156003 Sep 11 08:08:30 AM UTC 24 Sep 11 08:09:04 AM UTC 24 194420880 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.251788212 Sep 11 08:08:52 AM UTC 24 Sep 11 08:09:05 AM UTC 24 214030378 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4293419655 Sep 11 08:09:03 AM UTC 24 Sep 11 08:09:06 AM UTC 24 144992589 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.1596287162 Sep 11 08:09:03 AM UTC 24 Sep 11 08:09:06 AM UTC 24 70211572 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2482576018 Sep 11 08:09:05 AM UTC 24 Sep 11 08:09:08 AM UTC 24 107953829 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4237442471 Sep 11 08:08:48 AM UTC 24 Sep 11 08:09:08 AM UTC 24 4486369700 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.1847281919 Sep 11 08:08:34 AM UTC 24 Sep 11 08:09:09 AM UTC 24 1063202795 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.4118062505 Sep 11 08:08:58 AM UTC 24 Sep 11 08:09:10 AM UTC 24 832030085 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.657247470 Sep 11 08:08:56 AM UTC 24 Sep 11 08:09:10 AM UTC 24 100129698 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3933808620 Sep 11 08:09:00 AM UTC 24 Sep 11 08:09:11 AM UTC 24 936824210 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1515341431 Sep 11 08:08:57 AM UTC 24 Sep 11 08:09:11 AM UTC 24 330157098 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2008434102 Sep 11 08:09:00 AM UTC 24 Sep 11 08:09:12 AM UTC 24 454752073 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1622687878 Sep 11 08:09:45 AM UTC 24 Sep 11 08:09:57 AM UTC 24 231730172 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2180132163 Sep 11 08:09:11 AM UTC 24 Sep 11 08:09:13 AM UTC 24 101369220 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2479655324 Sep 11 08:08:57 AM UTC 24 Sep 11 08:09:13 AM UTC 24 2902582890 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3434480522 Sep 11 08:08:23 AM UTC 24 Sep 11 08:09:14 AM UTC 24 13038652295 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3664111557 Sep 11 08:09:11 AM UTC 24 Sep 11 08:09:14 AM UTC 24 23997012 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2412734959 Sep 11 08:09:12 AM UTC 24 Sep 11 08:09:14 AM UTC 24 94732379 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1288292846 Sep 11 08:08:58 AM UTC 24 Sep 11 08:09:15 AM UTC 24 2108530383 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3575944700 Sep 11 08:09:05 AM UTC 24 Sep 11 08:09:15 AM UTC 24 52340214 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1307728547 Sep 11 08:09:06 AM UTC 24 Sep 11 08:09:16 AM UTC 24 369004160 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1137468979 Sep 11 08:09:12 AM UTC 24 Sep 11 08:09:17 AM UTC 24 159754041 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.3395195018 Sep 11 08:09:13 AM UTC 24 Sep 11 08:09:17 AM UTC 24 37514190 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1075231246 Sep 11 08:09:06 AM UTC 24 Sep 11 08:09:17 AM UTC 24 1024499833 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2620094964 Sep 11 08:09:07 AM UTC 24 Sep 11 08:09:18 AM UTC 24 1428418688 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.527085314 Sep 11 08:09:17 AM UTC 24 Sep 11 08:09:20 AM UTC 24 17831485 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.564045342 Sep 11 08:09:19 AM UTC 24 Sep 11 08:09:21 AM UTC 24 43544101 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1737995686 Sep 11 08:09:06 AM UTC 24 Sep 11 08:09:21 AM UTC 24 523339524 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.942947561 Sep 11 08:09:17 AM UTC 24 Sep 11 08:09:22 AM UTC 24 112694615 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1688514278 Sep 11 08:09:06 AM UTC 24 Sep 11 08:09:26 AM UTC 24 752180070 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2278601720 Sep 11 08:09:14 AM UTC 24 Sep 11 08:09:26 AM UTC 24 609285332 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2700176519 Sep 11 08:09:07 AM UTC 24 Sep 11 08:09:26 AM UTC 24 1745626611 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2790175570 Sep 11 08:09:23 AM UTC 24 Sep 11 08:09:26 AM UTC 24 234430125 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1107771184 Sep 11 08:09:14 AM UTC 24 Sep 11 08:09:28 AM UTC 24 1991920598 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3941934853 Sep 11 08:08:44 AM UTC 24 Sep 11 08:09:29 AM UTC 24 332398451 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.814721238 Sep 11 08:09:14 AM UTC 24 Sep 11 08:09:30 AM UTC 24 648132218 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3861109843 Sep 11 08:09:21 AM UTC 24 Sep 11 08:09:30 AM UTC 24 478680092 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3169676958 Sep 11 08:08:34 AM UTC 24 Sep 11 08:09:31 AM UTC 24 2124193710 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.289632066 Sep 11 08:09:16 AM UTC 24 Sep 11 08:09:32 AM UTC 24 347059853 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.3574021133 Sep 11 08:09:16 AM UTC 24 Sep 11 08:09:32 AM UTC 24 386984647 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.72900086 Sep 11 08:09:30 AM UTC 24 Sep 11 08:09:33 AM UTC 24 69209318 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.760134526 Sep 11 08:08:48 AM UTC 24 Sep 11 08:09:33 AM UTC 24 4549436906 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2969816044 Sep 11 08:09:31 AM UTC 24 Sep 11 08:09:34 AM UTC 24 34939866 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.827130006 Sep 11 08:09:19 AM UTC 24 Sep 11 08:09:35 AM UTC 24 328395542 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.370432656 Sep 11 08:09:23 AM UTC 24 Sep 11 08:09:37 AM UTC 24 251526372 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.4210139757 Sep 11 08:08:11 AM UTC 24 Sep 11 08:09:39 AM UTC 24 4075464976 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2506059164 Sep 11 08:09:34 AM UTC 24 Sep 11 08:09:39 AM UTC 24 191774114 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.884896407 Sep 11 08:09:16 AM UTC 24 Sep 11 08:09:40 AM UTC 24 2573961814 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.484357160 Sep 11 08:09:22 AM UTC 24 Sep 11 08:09:40 AM UTC 24 482438801 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2759802184 Sep 11 08:09:46 AM UTC 24 Sep 11 08:09:58 AM UTC 24 853889282 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2382156967 Sep 11 08:09:26 AM UTC 24 Sep 11 08:09:41 AM UTC 24 501955379 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1879427598 Sep 11 08:09:26 AM UTC 24 Sep 11 08:09:42 AM UTC 24 287602576 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.939778288 Sep 11 08:09:35 AM UTC 24 Sep 11 08:09:42 AM UTC 24 341168787 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2352269550 Sep 11 08:08:55 AM UTC 24 Sep 11 08:09:43 AM UTC 24 609581401 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1527091761 Sep 11 08:09:28 AM UTC 24 Sep 11 08:09:43 AM UTC 24 906180947 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3260801895 Sep 11 08:09:33 AM UTC 24 Sep 11 08:09:43 AM UTC 24 172368834 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3069375950 Sep 11 08:09:31 AM UTC 24 Sep 11 08:09:43 AM UTC 24 226395863 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.122247918 Sep 11 08:09:42 AM UTC 24 Sep 11 08:09:44 AM UTC 24 39610303 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1760835021 Sep 11 08:09:42 AM UTC 24 Sep 11 08:09:44 AM UTC 24 31742279 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.259731738 Sep 11 08:09:42 AM UTC 24 Sep 11 08:09:45 AM UTC 24 28279833 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.3062568923 Sep 11 08:06:18 AM UTC 24 Sep 11 08:09:46 AM UTC 24 12974430752 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3335483657 Sep 11 08:09:34 AM UTC 24 Sep 11 08:09:47 AM UTC 24 1553118267 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2611969881 Sep 11 08:09:33 AM UTC 24 Sep 11 08:09:49 AM UTC 24 216644333 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1628676916 Sep 11 08:09:45 AM UTC 24 Sep 11 08:09:49 AM UTC 24 216374022 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1414940697 Sep 11 08:09:41 AM UTC 24 Sep 11 08:09:51 AM UTC 24 872789174 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.4101182882 Sep 11 08:09:35 AM UTC 24 Sep 11 08:09:51 AM UTC 24 4608542002 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2453072916 Sep 11 08:09:03 AM UTC 24 Sep 11 08:09:52 AM UTC 24 672813222 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1747026041 Sep 11 08:09:12 AM UTC 24 Sep 11 08:09:52 AM UTC 24 166311804 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.64591482 Sep 11 08:09:51 AM UTC 24 Sep 11 08:09:53 AM UTC 24 43649212 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3984722133 Sep 11 08:09:43 AM UTC 24 Sep 11 08:09:54 AM UTC 24 545503619 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1516268654 Sep 11 08:09:51 AM UTC 24 Sep 11 08:09:54 AM UTC 24 92511428 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3352102408 Sep 11 08:09:52 AM UTC 24 Sep 11 08:09:54 AM UTC 24 13194699 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1858748266 Sep 11 08:09:36 AM UTC 24 Sep 11 08:09:58 AM UTC 24 1615942732 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1202333763 Sep 11 08:09:45 AM UTC 24 Sep 11 08:09:55 AM UTC 24 518999738 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3442715201 Sep 11 08:09:38 AM UTC 24 Sep 11 08:09:55 AM UTC 24 513650322 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1561459795 Sep 11 08:09:53 AM UTC 24 Sep 11 08:09:56 AM UTC 24 22142887 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3355371504 Sep 11 08:09:53 AM UTC 24 Sep 11 08:09:59 AM UTC 24 87128514 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2091924467 Sep 11 08:10:48 AM UTC 24 Sep 11 08:10:51 AM UTC 24 307983272 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3922875540 Sep 11 08:09:45 AM UTC 24 Sep 11 08:09:59 AM UTC 24 776240274 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2075799724 Sep 11 08:09:58 AM UTC 24 Sep 11 08:10:00 AM UTC 24 35453456 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1613785180 Sep 11 08:09:46 AM UTC 24 Sep 11 08:10:01 AM UTC 24 326211363 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.492639029 Sep 11 08:09:59 AM UTC 24 Sep 11 08:10:01 AM UTC 24 39420169 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3359528889 Sep 11 08:09:54 AM UTC 24 Sep 11 08:10:02 AM UTC 24 1605705621 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.1377802408 Sep 11 08:09:19 AM UTC 24 Sep 11 08:10:02 AM UTC 24 1274228367 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1313083951 Sep 11 08:07:29 AM UTC 24 Sep 11 08:10:02 AM UTC 24 16433086560 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.2428796709 Sep 11 08:10:01 AM UTC 24 Sep 11 08:10:04 AM UTC 24 28209513 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.313051314 Sep 11 08:10:00 AM UTC 24 Sep 11 08:10:05 AM UTC 24 204011938 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3632278589 Sep 11 08:09:59 AM UTC 24 Sep 11 08:10:05 AM UTC 24 571099256 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.82806288 Sep 11 08:09:54 AM UTC 24 Sep 11 08:10:06 AM UTC 24 744286909 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.965711451 Sep 11 08:09:56 AM UTC 24 Sep 11 08:10:07 AM UTC 24 183981875 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1668546570 Sep 11 08:08:47 AM UTC 24 Sep 11 08:10:09 AM UTC 24 13142934968 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.708644286 Sep 11 08:09:45 AM UTC 24 Sep 11 08:10:09 AM UTC 24 541765661 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2831127939 Sep 11 08:10:07 AM UTC 24 Sep 11 08:10:09 AM UTC 24 69505506 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1791477367 Sep 11 08:10:07 AM UTC 24 Sep 11 08:10:09 AM UTC 24 36918549 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2433605257 Sep 11 08:09:56 AM UTC 24 Sep 11 08:10:10 AM UTC 24 378578103 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1679908025 Sep 11 08:10:07 AM UTC 24 Sep 11 08:10:11 AM UTC 24 39935550 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.3529763337 Sep 11 08:09:53 AM UTC 24 Sep 11 08:10:13 AM UTC 24 2072992209 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.452634643 Sep 11 08:09:56 AM UTC 24 Sep 11 08:10:14 AM UTC 24 4255753980 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2038509664 Sep 11 08:10:01 AM UTC 24 Sep 11 08:10:15 AM UTC 24 1057954222 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1550446662 Sep 11 08:08:52 AM UTC 24 Sep 11 08:10:16 AM UTC 24 2991832535 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.3200853824 Sep 11 08:12:56 AM UTC 24 Sep 11 08:12:59 AM UTC 24 16526696 ps
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