| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.18 | 97.92 | 95.29 | 93.40 | 100.00 | 98.52 | 99.00 | 96.11 |
| T130 | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2560897240 | Sep 11 10:31:24 AM UTC 24 | Sep 11 10:31:29 AM UTC 24 | 162175848 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_security_escalation.3785648860 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 311491397 ps |
| CPU time | 17.78 seconds |
| Started | Sep 11 08:01:53 AM UTC 24 |
| Finished | Sep 11 08:02:12 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785648860 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3785648860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_errors.4161342466 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1193717678 ps |
| CPU time | 22.91 seconds |
| Started | Sep 11 08:02:02 AM UTC 24 |
| Finished | Sep 11 08:02:26 AM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161342466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_ jtag_errors.4161342466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_mubi.327570499 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 689131236 ps |
| CPU time | 12.74 seconds |
| Started | Sep 11 08:02:13 AM UTC 24 |
| Finished | Sep 11 08:02:27 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327570499 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.327570499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_regwen_during_op.4005858423 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1099532189 ps |
| CPU time | 11.5 seconds |
| Started | Sep 11 08:03:23 AM UTC 24 |
| Finished | Sep 11 08:03:36 AM UTC 24 |
| Peak memory | 225904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005858423 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.4005858423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_failure.3939509571 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3037235090 ps |
| CPU time | 62 seconds |
| Started | Sep 11 08:01:58 AM UTC 24 |
| Finished | Sep 11 08:03:02 AM UTC 24 |
| Peak memory | 285528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939509571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_c trl_jtag_state_failure.3939509571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.4210139757 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 4075464976 ps |
| CPU time | 86.33 seconds |
| Started | Sep 11 08:08:11 AM UTC 24 |
| Finished | Sep 11 08:09:39 AM UTC 24 |
| Peak memory | 291752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210139757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.4210139757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_security_escalation.2842973213 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 250028604 ps |
| CPU time | 9.26 seconds |
| Started | Sep 11 08:06:25 AM UTC 24 |
| Finished | Sep 11 08:06:35 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2842973213 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2842973213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_mux.1555241539 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 940551297 ps |
| CPU time | 19.77 seconds |
| Started | Sep 11 08:02:13 AM UTC 24 |
| Finished | Sep 11 08:02:34 AM UTC 24 |
| Peak memory | 237876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1555241539 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_toke n_mux.1555241539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_cm.2744853083 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 876105581 ps |
| CPU time | 60.71 seconds |
| Started | Sep 11 08:02:18 AM UTC 24 |
| Finished | Sep 11 08:03:20 AM UTC 24 |
| Peak memory | 291952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744853083 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2744853083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_access.4265975888 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 476270997 ps |
| CPU time | 8.21 seconds |
| Started | Sep 11 08:02:06 AM UTC 24 |
| Finished | Sep 11 08:02:16 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265975888 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4265975888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1449066815 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 52364928652 ps |
| CPU time | 99.76 seconds |
| Started | Sep 11 08:03:13 AM UTC 24 |
| Finished | Sep 11 08:04:55 AM UTC 24 |
| Peak memory | 289428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1449066815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 2.lc_ctrl_stress_all.1449066815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1515341431 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 330157098 ps |
| CPU time | 12.84 seconds |
| Started | Sep 11 08:08:57 AM UTC 24 |
| Finished | Sep 11 08:09:11 AM UTC 24 |
| Peak memory | 238208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515341431 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1515341431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_post_trans.4278319215 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 91202856 ps |
| CPU time | 10.66 seconds |
| Started | Sep 11 08:01:50 AM UTC 24 |
| Finished | Sep 11 08:02:02 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278319215 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.4278319215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2344131617 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 110444780 ps |
| CPU time | 2.37 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344131617 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_t l_intg_err.2344131617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.893995863 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 40192247571 ps |
| CPU time | 600.23 seconds |
| Started | Sep 11 08:09:41 AM UTC 24 |
| Finished | Sep 11 08:19:48 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=893995863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 24.lc_ctrl_stress_all.893995863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.2798931511 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 643203464 ps |
| CPU time | 8.88 seconds |
| Started | Sep 11 08:11:57 AM UTC 24 |
| Finished | Sep 11 08:12:07 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798931511 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2798931511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_errors.3270516434 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 1288045572 ps |
| CPU time | 22.1 seconds |
| Started | Sep 11 08:02:55 AM UTC 24 |
| Finished | Sep 11 08:03:18 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270516434 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3270516434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.1355196540 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7136830988 ps |
| CPU time | 275.8 seconds |
| Started | Sep 11 08:02:15 AM UTC 24 |
| Finished | Sep 11 08:06:55 AM UTC 24 |
| Peak memory | 301984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1355196540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 0.lc_ctrl_stress_all.1355196540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474306584 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 102585624 ps |
| CPU time | 3.21 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 231600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474306584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474306584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2110923022 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 18536243 ps |
| CPU time | 0.99 seconds |
| Started | Sep 11 10:31:23 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 218056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110923022 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2110923022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_alert_test.864302033 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 58165278 ps |
| CPU time | 1.87 seconds |
| Started | Sep 11 08:02:23 AM UTC 24 |
| Finished | Sep 11 08:02:26 AM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864302033 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.864302033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3717857527 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 209446261 ps |
| CPU time | 3.7 seconds |
| Started | Sep 11 10:30:55 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 229504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717857527 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_ tl_intg_err.3717857527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_state_failure.3140633078 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 1564309687 ps |
| CPU time | 51.15 seconds |
| Started | Sep 11 08:01:50 AM UTC 24 |
| Finished | Sep 11 08:02:43 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140633078 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.3140633078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2985036039 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 488490973 ps |
| CPU time | 2.84 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:47 AM UTC 24 |
| Peak memory | 229748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985036039 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2985036039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_mubi.1835635188 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 425073218 ps |
| CPU time | 17.41 seconds |
| Started | Sep 11 08:03:11 AM UTC 24 |
| Finished | Sep 11 08:03:29 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835635188 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1835635188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_prog_failure.3802320155 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 23398192 ps |
| CPU time | 2.44 seconds |
| Started | Sep 11 08:01:51 AM UTC 24 |
| Finished | Sep 11 08:01:55 AM UTC 24 |
| Peak memory | 232468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802320155 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3802320155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3738209219 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 75587605 ps |
| CPU time | 2.82 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:48 AM UTC 24 |
| Peak memory | 229812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738209219 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_t l_intg_err.3738209219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_failure.476086819 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 9090550090 ps |
| CPU time | 67.24 seconds |
| Started | Sep 11 08:03:27 AM UTC 24 |
| Finished | Sep 11 08:04:36 AM UTC 24 |
| Peak memory | 295496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476086819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_jtag_state_failure.476086819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_state_post_trans.2246989880 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 3126734108 ps |
| CPU time | 29.87 seconds |
| Started | Sep 11 08:01:59 AM UTC 24 |
| Finished | Sep 11 08:02:30 AM UTC 24 |
| Peak memory | 258632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246989880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.l c_ctrl_jtag_state_post_trans.2246989880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1913212843 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 46832119 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:34 AM UTC 24 |
| Peak memory | 220172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913212843 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ hw_reset.1913212843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.936648377 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 68223432 ps |
| CPU time | 1.85 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:33 AM UTC 24 |
| Peak memory | 218380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=936648377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.936648377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.685178139 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 1297558894 ps |
| CPU time | 79.29 seconds |
| Started | Sep 11 08:04:06 AM UTC 24 |
| Finished | Sep 11 08:05:28 AM UTC 24 |
| Peak memory | 279328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685178139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.685178139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2634767114 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 127799476 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:31:01 AM UTC 24 |
| Peak memory | 235624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634767114 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_ tl_intg_err.2634767114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2529675229 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 48210861 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 10:31:23 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 222156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529675229 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_ tl_intg_err.2529675229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1273624961 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 1076132174 ps |
| CPU time | 3.32 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273624961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1273624961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2791326042 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 303088941 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 235624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791326042 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_t l_intg_err.2791326042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1266425155 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 141882291 ps |
| CPU time | 3.48 seconds |
| Started | Sep 11 10:30:53 AM UTC 24 |
| Finished | Sep 11 10:30:57 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266425155 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_t l_intg_err.1266425155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1388983412 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 53427878 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 08:01:50 AM UTC 24 |
| Finished | Sep 11 08:01:52 AM UTC 24 |
| Peak memory | 229396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1388983412 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_volatile_unlock_smoke.1388983412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_claim_transition_if.11167560 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 14967289 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 08:05:05 AM UTC 24 |
| Finished | Sep 11 08:05:08 AM UTC 24 |
| Peak memory | 217232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11167560 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.11167560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_claim_transition_if.1979154454 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 11969788 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 08:05:28 AM UTC 24 |
| Finished | Sep 11 08:05:31 AM UTC 24 |
| Peak memory | 217356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979154454 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1979154454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_claim_transition_if.1082063009 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 11029407 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 08:05:51 AM UTC 24 |
| Finished | Sep 11 08:05:54 AM UTC 24 |
| Peak memory | 219088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082063009 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1082063009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2398674422 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 65268853 ps |
| CPU time | 2.07 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 235788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398674422 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_t l_intg_err.2398674422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2568641020 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 178314439 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 10:30:46 AM UTC 24 |
| Finished | Sep 11 10:30:49 AM UTC 24 |
| Peak memory | 229888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568641020 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_t l_intg_err.2568641020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2838150834 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 19614156779 ps |
| CPU time | 596.92 seconds |
| Started | Sep 11 08:10:25 AM UTC 24 |
| Finished | Sep 11 08:20:29 AM UTC 24 |
| Peak memory | 295832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2838150834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 29.lc_ctrl_stress_all.2838150834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_stress_all.4076206919 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 44375322570 ps |
| CPU time | 198.77 seconds |
| Started | Sep 11 08:02:47 AM UTC 24 |
| Finished | Sep 11 08:06:09 AM UTC 24 |
| Peak memory | 262872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4076206919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 1.lc_ctrl_stress_all.4076206919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1438596089 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 201880623 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 218544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438596089 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ aliasing.1438596089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3558588389 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 25605008 ps |
| CPU time | 1.66 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 218676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558588389 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_ bit_bash.3558588389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2716922492 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 301672096 ps |
| CPU time | 1.81 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2716922492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2716922492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4214533620 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 39852651 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:34 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214533620 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.4214533620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.888841397 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 124403850 ps |
| CPU time | 1.62 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:33 AM UTC 24 |
| Peak memory | 217792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=888841397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 0.lc_ctrl_jtag_alert_test.888841397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.478481359 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 1310506367 ps |
| CPU time | 4.61 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 219284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=478481359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.478481359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4201302912 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 3707121397 ps |
| CPU time | 21.51 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4201302912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4201302912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3330029204 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 795069798 ps |
| CPU time | 4.23 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 221232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3330029204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3330029204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.71530055 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 585414502 ps |
| CPU time | 4.16 seconds |
| Started | Sep 11 10:30:30 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 219168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=71530055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_rw.71530055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3848996854 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 238587878 ps |
| CPU time | 1.44 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38489 96854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0. lc_ctrl_same_csr_outstanding.3848996854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3995898474 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 72051583 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:34 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995898474 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3995898474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3451765603 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 26378461 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451765603 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ aliasing.3451765603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.258995548 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 228788815 ps |
| CPU time | 1.68 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:37 AM UTC 24 |
| Peak memory | 218840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258995548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_b it_bash.258995548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1693708004 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 29543105 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 220036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693708004 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_ hw_reset.1693708004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4098491575 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 17726688 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4098491575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.4098491575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2766704489 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 51897912 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766704489 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2766704489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1116756591 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 98281127 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:37 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1116756591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1116756591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.103490309 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 339143095 ps |
| CPU time | 5.06 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 218964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=103490309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.103490309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2128903163 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 848032538 ps |
| CPU time | 10.11 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2128903163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2128903163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1617564041 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 95620907 ps |
| CPU time | 2.94 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 221228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1617564041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1617564041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3538755127 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 341069890 ps |
| CPU time | 3.05 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 229880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538755127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3538755127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3598179503 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 243363876 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 10:30:32 AM UTC 24 |
| Finished | Sep 11 10:30:35 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=3598179503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.lc_ctrl_jtag_csr_rw.3598179503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1121662091 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 162285716 ps |
| CPU time | 1.71 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:37 AM UTC 24 |
| Peak memory | 228780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1121662091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1121662091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2350053595 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 69829182 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:36 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23500 53595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1. lc_ctrl_same_csr_outstanding.2350053595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.629372049 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 32731680 ps |
| CPU time | 2.74 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629372049 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.629372049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2692617812 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 247683064 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 10:30:34 AM UTC 24 |
| Finished | Sep 11 10:30:37 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692617812 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_t l_intg_err.2692617812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.650661869 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 22361387 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 10:30:55 AM UTC 24 |
| Finished | Sep 11 10:30:58 AM UTC 24 |
| Peak memory | 234448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=650661869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.650661869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3453945150 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 24881736 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 10:30:55 AM UTC 24 |
| Finished | Sep 11 10:30:57 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453945150 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3453945150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.687182233 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 125699192 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 10:30:55 AM UTC 24 |
| Finished | Sep 11 10:30:57 AM UTC 24 |
| Peak memory | 220592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68718 2233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10. lc_ctrl_same_csr_outstanding.687182233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.933114489 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 73243927 ps |
| CPU time | 3.03 seconds |
| Started | Sep 11 10:30:54 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933114489 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.933114489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1828956347 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 32871966 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 230356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1828956347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1828956347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1073502611 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 12021065 ps |
| CPU time | 1 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:30:58 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1073502611 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1073502611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2132784033 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 31941487 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 228720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21327 84033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11 .lc_ctrl_same_csr_outstanding.2132784033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2730483420 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 552794064 ps |
| CPU time | 4.81 seconds |
| Started | Sep 11 10:30:55 AM UTC 24 |
| Finished | Sep 11 10:31:01 AM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730483420 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2730483420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1276115660 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 113868002 ps |
| CPU time | 2.31 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:31:00 AM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276115660 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_ tl_intg_err.1276115660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1077506277 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 68810230 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1077506277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1077506277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1062510879 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 23902855 ps |
| CPU time | 0.95 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:30:58 AM UTC 24 |
| Peak memory | 218768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062510879 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1062510879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.301424822 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 17125294 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30142 4822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12. lc_ctrl_same_csr_outstanding.301424822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.243865824 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 69608576 ps |
| CPU time | 3 seconds |
| Started | Sep 11 10:30:56 AM UTC 24 |
| Finished | Sep 11 10:31:00 AM UTC 24 |
| Peak memory | 229560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243865824 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.243865824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.92372320 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 97727683 ps |
| CPU time | 1.96 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:31:00 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=92372320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.92372320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.411162486 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 12046740 ps |
| CPU time | 1.01 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 218524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411162486 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.411162486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.984125849 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 149663708 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 220576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98412 5849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13. lc_ctrl_same_csr_outstanding.984125849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3105983861 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 66640406 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105983861 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3105983861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4273338714 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 122662094 ps |
| CPU time | 1.72 seconds |
| Started | Sep 11 10:30:57 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273338714 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_ tl_intg_err.4273338714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2881725775 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 30181648 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2881725775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2881725775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2526668811 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 23533993 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 10:31:23 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25266 68811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14 .lc_ctrl_same_csr_outstanding.2526668811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1416218036 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 55704603 ps |
| CPU time | 2.47 seconds |
| Started | Sep 11 10:31:23 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416218036 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1416218036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.69719530 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 24391732 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=69719530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.69719530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.247841832 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 14168003 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247841832 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.247841832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.135967429 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 24569783 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 218484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13596 7429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15. lc_ctrl_same_csr_outstanding.135967429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2515655289 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 131168400 ps |
| CPU time | 2.76 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:28 AM UTC 24 |
| Peak memory | 229476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515655289 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2515655289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1209984565 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1836545954 ps |
| CPU time | 4.15 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:29 AM UTC 24 |
| Peak memory | 229552 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1209984565 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_ tl_intg_err.1209984565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2984194345 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 60130683 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2984194345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2984194345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.929643394 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 81821219 ps |
| CPU time | 0.91 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929643394 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.929643394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2859945694 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 24285786 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 220180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28599 45694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_same_csr_outstanding.2859945694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.635712734 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 193578559 ps |
| CPU time | 2.2 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635712734 -assert nopostpr oc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.635712734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2861928869 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 197768526 ps |
| CPU time | 3.3 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:29 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861928869 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_ tl_intg_err.2861928869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2507777756 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 84082181 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2507777756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2507777756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2564123442 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 42420244 ps |
| CPU time | 0.96 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:26 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2564123442 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2564123442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2572136231 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 133537344 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 218508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25721 36231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17 .lc_ctrl_same_csr_outstanding.2572136231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1858417389 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 29563168 ps |
| CPU time | 1.77 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858417389 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1858417389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1772683023 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 394237588 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:28 AM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772683023 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_ tl_intg_err.1772683023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1071432413 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 23228012 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 232352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1071432413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1071432413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4074515598 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 31227234 ps |
| CPU time | 0.88 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074515598 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4074515598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4051478796 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 32085691 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 218580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40514 78796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18 .lc_ctrl_same_csr_outstanding.4051478796 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2770783754 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 111474347 ps |
| CPU time | 3.3 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:29 AM UTC 24 |
| Peak memory | 229460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770783754 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2770783754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2560897240 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 162175848 ps |
| CPU time | 3.39 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:29 AM UTC 24 |
| Peak memory | 235624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2560897240 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_ tl_intg_err.2560897240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1058197748 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 117674496 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:28 AM UTC 24 |
| Peak memory | 234452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1058197748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1058197748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1938720429 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 44093339 ps |
| CPU time | 1.06 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 219064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938720429 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1938720429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1185476519 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 54854182 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:27 AM UTC 24 |
| Peak memory | 218124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11854 76519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19 .lc_ctrl_same_csr_outstanding.1185476519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2292480341 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 63118310 ps |
| CPU time | 2.42 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:28 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292480341 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2292480341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.189387276 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 65294652 ps |
| CPU time | 2.57 seconds |
| Started | Sep 11 10:31:24 AM UTC 24 |
| Finished | Sep 11 10:31:29 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189387276 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_t l_intg_err.189387276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3211234095 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 39274905 ps |
| CPU time | 1.9 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211234095 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ aliasing.3211234095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2728871135 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 69796923 ps |
| CPU time | 2.16 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 219208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728871135 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ bit_bash.2728871135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3571546604 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 143305591 ps |
| CPU time | 1.3 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:39 AM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571546604 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_ hw_reset.3571546604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.646340615 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 139271586 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=646340615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.646340615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3433234053 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 117894658 ps |
| CPU time | 0.93 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:39 AM UTC 24 |
| Peak memory | 218128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433234053 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3433234053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.129994984 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 29119507 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 10:30:36 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 218512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=129994984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 2.lc_ctrl_jtag_alert_test.129994984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.921088010 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 267138552 ps |
| CPU time | 2.78 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:39 AM UTC 24 |
| Peak memory | 218116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=921088010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.921088010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4210768512 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 1969859560 ps |
| CPU time | 11.15 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:48 AM UTC 24 |
| Peak memory | 219268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=4210768512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4210768512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1005386054 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 82380399 ps |
| CPU time | 3.17 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 221480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1005386054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1005386054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1456972686 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 99592021 ps |
| CPU time | 2.44 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:39 AM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456972686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1456972686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1418178476 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 665950501 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 218644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1418178476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1418178476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2860506391 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 35928916 ps |
| CPU time | 1.68 seconds |
| Started | Sep 11 10:30:35 AM UTC 24 |
| Finished | Sep 11 10:30:38 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2860506391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2860506391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1619563230 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 480250829 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 228784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16195 63230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2. lc_ctrl_same_csr_outstanding.1619563230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2734802541 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 173284601 ps |
| CPU time | 5.79 seconds |
| Started | Sep 11 10:30:36 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 231836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734802541 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2734802541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.333899081 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 149667103 ps |
| CPU time | 2.44 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:40 AM UTC 24 |
| Peak memory | 229608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333899081 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl _intg_err.333899081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.802140474 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 28041069 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802140474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_a liasing.802140474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1645233599 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 133249579 ps |
| CPU time | 2.13 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:43 AM UTC 24 |
| Peak memory | 219240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645233599 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ bit_bash.1645233599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1943031523 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 21346837 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 220172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943031523 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_ hw_reset.1943031523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1168018610 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 22742731 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=1168018610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1168018610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3933177569 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 24851784 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933177569 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3933177569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3344335114 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 52149712 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3344335114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3344335114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3231154298 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 193007619 ps |
| CPU time | 5.34 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3231154298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3231154298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1742775366 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 7566320644 ps |
| CPU time | 15.7 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 219272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1742775366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1742775366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1978291982 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 191164546 ps |
| CPU time | 4.26 seconds |
| Started | Sep 11 10:30:37 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 221560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1978291982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1978291982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3817734676 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 341160649 ps |
| CPU time | 1.93 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817734676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3817734676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2620537728 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 227124839 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2620537728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 3.lc_ctrl_jtag_csr_rw.2620537728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.962717602 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 14634363 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:41 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=962717602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.962717602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2548421360 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 17479711 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 218572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25484 21360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3. lc_ctrl_same_csr_outstanding.2548421360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1104797964 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 64311943 ps |
| CPU time | 2.93 seconds |
| Started | Sep 11 10:30:38 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 231860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104797964 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1104797964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1061669289 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 17019762 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 218776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061669289 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ aliasing.1061669289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.377754959 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 52766982 ps |
| CPU time | 2.25 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 219204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377754959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_b it_bash.377754959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3158544660 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 29848568 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 220172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158544660 -asser t nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_ hw_reset.3158544660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4279762883 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 86666768 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=4279762883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4279762883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3787194348 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 49916495 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787194348 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3787194348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1187373832 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 58102086 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=1187373832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1187373832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1626497769 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2240450424 ps |
| CPU time | 11.92 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 219480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1626497769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.1626497769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2380841179 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 1244818468 ps |
| CPU time | 18.04 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 219020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2380841179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2380841179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.880595921 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 876868013 ps |
| CPU time | 2.96 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 221288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=880595921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.880595921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776983741 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 168753077 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 229556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776983741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776983741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2021288359 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 140190168 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:30:40 AM UTC 24 |
| Finished | Sep 11 10:30:42 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2021288359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2021288359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2831801752 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 47363707 ps |
| CPU time | 1.81 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 218540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2831801752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2831801752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.449850409 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 27034840 ps |
| CPU time | 1.44 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:44 AM UTC 24 |
| Peak memory | 218584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44985 0409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.l c_ctrl_same_csr_outstanding.449850409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3415939126 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 104601285 ps |
| CPU time | 3.08 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3415939126 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3415939126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2096719782 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 781803791 ps |
| CPU time | 2.8 seconds |
| Started | Sep 11 10:30:41 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 236104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096719782 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace s/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_t l_intg_err.2096719782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2094837862 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 19564254 ps |
| CPU time | 1.45 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:47 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2094837862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2094837862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3745309972 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 18531889 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745309972 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3745309972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3355861265 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 153900087 ps |
| CPU time | 3 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:47 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3355861265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3355861265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3978964498 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 951802919 ps |
| CPU time | 11.65 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:56 AM UTC 24 |
| Peak memory | 219352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3978964498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3978964498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2551794775 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 5942909608 ps |
| CPU time | 9.54 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 219216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2551794775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2551794775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.252726339 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 644529202 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 220524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=252726339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.252726339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2909144973 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 63931015 ps |
| CPU time | 2.46 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 229884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2909144973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2909144973 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1514413248 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 94695668 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:45 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1514413248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 5.lc_ctrl_jtag_csr_rw.1514413248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3954293952 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 139358852 ps |
| CPU time | 2.05 seconds |
| Started | Sep 11 10:30:43 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 219304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3954293952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3954293952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3732784075 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 39140604 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 228764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37327 84075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5. lc_ctrl_same_csr_outstanding.3732784075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3243097586 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 85800982 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:49 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=3243097586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3243097586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1077430524 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 61359072 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:49 AM UTC 24 |
| Peak memory | 219068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077430524 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1077430524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3325543263 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 21534094 ps |
| CPU time | 1.07 seconds |
| Started | Sep 11 10:30:45 AM UTC 24 |
| Finished | Sep 11 10:30:48 AM UTC 24 |
| Peak memory | 218712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3325543263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3325543263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1558506202 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 857181941 ps |
| CPU time | 3.43 seconds |
| Started | Sep 11 10:30:45 AM UTC 24 |
| Finished | Sep 11 10:30:50 AM UTC 24 |
| Peak memory | 219000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1558506202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1558506202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2932491220 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 558445507 ps |
| CPU time | 6.84 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:52 AM UTC 24 |
| Peak memory | 218568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2932491220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2932491220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.907075288 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 97720032 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:47 AM UTC 24 |
| Peak memory | 220524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=907075288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.907075288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1794956010 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1254220047 ps |
| CPU time | 7.29 seconds |
| Started | Sep 11 10:30:45 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 231616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794956010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1794956010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2741501558 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 172229542 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 10:30:44 AM UTC 24 |
| Finished | Sep 11 10:30:46 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2741501558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.lc_ctrl_jtag_csr_rw.2741501558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3028331347 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 40320409 ps |
| CPU time | 1.6 seconds |
| Started | Sep 11 10:30:45 AM UTC 24 |
| Finished | Sep 11 10:30:48 AM UTC 24 |
| Peak memory | 228732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=3028331347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3028331347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.915477507 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 14999934 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:49 AM UTC 24 |
| Peak memory | 218536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91547 7507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_same_csr_outstanding.915477507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1699410978 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 49652364 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 10:30:46 AM UTC 24 |
| Finished | Sep 11 10:30:49 AM UTC 24 |
| Peak memory | 229492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699410978 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1699410978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2172103260 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 28351827 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=2172103260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2172103260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2417710542 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 18095229 ps |
| CPU time | 1.22 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417710542 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2417710542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2666198641 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 197156348 ps |
| CPU time | 1.78 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=2666198641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2666198641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2332857636 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 1291544611 ps |
| CPU time | 5.65 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 219364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=2332857636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2332857636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3990822890 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 1663559185 ps |
| CPU time | 17.15 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:31:05 AM UTC 24 |
| Peak memory | 218336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3990822890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3990822890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1237318451 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 87751434 ps |
| CPU time | 1.75 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:50 AM UTC 24 |
| Peak memory | 220532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1237318451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1237318451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440543369 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2160401432 ps |
| CPU time | 6.12 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 231632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440543369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440543369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.600970591 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 233736833 ps |
| CPU time | 1.75 seconds |
| Started | Sep 11 10:30:47 AM UTC 24 |
| Finished | Sep 11 10:30:50 AM UTC 24 |
| Peak memory | 218704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=600970591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_rw.600970591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1381024696 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 62612678 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=1381024696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1381024696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1720603327 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 29220423 ps |
| CPU time | 1.16 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17206 03327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7. lc_ctrl_same_csr_outstanding.1720603327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3254114694 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 136153893 ps |
| CPU time | 4.81 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 229548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254114694 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3254114694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.840660185 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 273195260 ps |
| CPU time | 3.35 seconds |
| Started | Sep 11 10:30:48 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840660185 -ass ert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl _intg_err.840660185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.960771308 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 183643219 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=960771308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.960771308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3165297655 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 15877866 ps |
| CPU time | 1.33 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165297655 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3165297655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3775696784 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 39870457 ps |
| CPU time | 0.97 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:52 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=3775696784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3775696784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1579083878 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 642999496 ps |
| CPU time | 4.3 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 218464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1579083878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1579083878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3071877337 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 352468314 ps |
| CPU time | 5.56 seconds |
| Started | Sep 11 10:30:49 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3071877337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3071877337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1698628310 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 467470894 ps |
| CPU time | 3.75 seconds |
| Started | Sep 11 10:30:49 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 221236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1698628310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1698628310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1624575933 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 35020562 ps |
| CPU time | 1.21 seconds |
| Started | Sep 11 10:30:49 AM UTC 24 |
| Finished | Sep 11 10:30:51 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=1624575933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.lc_ctrl_jtag_csr_rw.1624575933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2900080556 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 80900137 ps |
| CPU time | 1.8 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:53 AM UTC 24 |
| Peak memory | 220588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=2900080556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_ top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2900080556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.258002472 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 103873511 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 218536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25800 2472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_same_csr_outstanding.258002472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3500204893 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 110143019 ps |
| CPU time | 3.46 seconds |
| Started | Sep 11 10:30:50 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 229484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500204893 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3500204893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.855630687 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 44445403 ps |
| CPU time | 0.96 seconds |
| Started | Sep 11 10:30:54 AM UTC 24 |
| Finished | Sep 11 10:30:56 AM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t ools/sim.tcl +ntb_random_seed=855630687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.855630687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3051129518 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 33388301 ps |
| CPU time | 1.14 seconds |
| Started | Sep 11 10:30:54 AM UTC 24 |
| Finished | Sep 11 10:30:56 AM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051129518 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3051129518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.220686994 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 35995986 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 10:30:53 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 218652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +c reate_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim .tcl +ntb_random_seed=220686994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 9.lc_ctrl_jtag_alert_test.220686994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3907807942 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 444482388 ps |
| CPU time | 6.55 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:59 AM UTC 24 |
| Peak memory | 218492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=3907807942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3907807942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1320375241 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 4404106046 ps |
| CPU time | 10.28 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:31:03 AM UTC 24 |
| Peak memory | 219356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=1320375241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1320375241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.780875045 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 81127171 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:54 AM UTC 24 |
| Peak memory | 220464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_r iscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.t cl +ntb_random_seed=780875045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_l og /dev/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.780875045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1119188446 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 297352729 ps |
| CPU time | 2.92 seconds |
| Started | Sep 11 10:30:53 AM UTC 24 |
| Finished | Sep 11 10:30:56 AM UTC 24 |
| Peak memory | 231928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_ti meout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119188446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_d isabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1119188446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2349559664 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 67232770 ps |
| CPU time | 2.98 seconds |
| Started | Sep 11 10:30:51 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 219172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_m ap=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +nt b_random_seed=2349559664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 9.lc_ctrl_jtag_csr_rw.2349559664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.408932247 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 37179634 ps |
| CPU time | 1.91 seconds |
| Started | Sep 11 10:30:53 AM UTC 24 |
| Finished | Sep 11 10:30:55 AM UTC 24 |
| Peak memory | 218480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +c reate_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv /tools/sim.tcl +ntb_random_seed=408932247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_t op.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.408932247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.354398744 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 30216506 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 10:30:54 AM UTC 24 |
| Finished | Sep 11 10:30:57 AM UTC 24 |
| Peak memory | 218576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35439 8744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.l c_ctrl_same_csr_outstanding.354398744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4269765604 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 30632437 ps |
| CPU time | 2.5 seconds |
| Started | Sep 11 10:30:53 AM UTC 24 |
| Finished | Sep 11 10:30:56 AM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269765604 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4269765604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_claim_transition_if.955315517 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 34838647 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 08:01:56 AM UTC 24 |
| Finished | Sep 11 08:01:58 AM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955315517 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.955315517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_errors.1850733436 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 565027647 ps |
| CPU time | 19.11 seconds |
| Started | Sep 11 08:01:51 AM UTC 24 |
| Finished | Sep 11 08:02:12 AM UTC 24 |
| Peak memory | 237868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850733436 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1850733436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_priority.3373368472 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2958114509 ps |
| CPU time | 4.61 seconds |
| Started | Sep 11 08:02:09 AM UTC 24 |
| Finished | Sep 11 08:02:14 AM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373368472 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_pri ority.3373368472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_prog_failure.950731447 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 577263205 ps |
| CPU time | 24.15 seconds |
| Started | Sep 11 08:02:00 AM UTC 24 |
| Finished | Sep 11 08:02:26 AM UTC 24 |
| Peak memory | 236248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950731447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr l_jtag_prog_failure.950731447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_regwen_during_op.585609396 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 1224091992 ps |
| CPU time | 31.18 seconds |
| Started | Sep 11 08:02:13 AM UTC 24 |
| Finished | Sep 11 08:02:45 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585609396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc _ctrl_jtag_regwen_during_op.585609396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_jtag_smoke.259525867 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 4538788365 ps |
| CPU time | 8.04 seconds |
| Started | Sep 11 08:01:57 AM UTC 24 |
| Finished | Sep 11 08:02:06 AM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259525867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_ smoke.259525867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_regwen_during_op.542680650 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 923356651 ps |
| CPU time | 15.95 seconds |
| Started | Sep 11 08:01:55 AM UTC 24 |
| Finished | Sep 11 08:02:12 AM UTC 24 |
| Peak memory | 226016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542680650 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.542680650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_sec_token_digest.1316403899 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 240972384 ps |
| CPU time | 12.11 seconds |
| Started | Sep 11 08:02:14 AM UTC 24 |
| Finished | Sep 11 08:02:27 AM UTC 24 |
| Peak memory | 238148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316403899 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_t oken_digest.1316403899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/0.lc_ctrl_smoke.2882151798 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 421880172 ps |
| CPU time | 7.59 seconds |
| Started | Sep 11 08:01:48 AM UTC 24 |
| Finished | Sep 11 08:01:57 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882151798 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2882151798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/0.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_alert_test.893722900 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 54027599 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:02:48 AM UTC 24 |
| Finished | Sep 11 08:02:51 AM UTC 24 |
| Peak memory | 218812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893722900 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.893722900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_claim_transition_if.952050275 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 25879689 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 08:02:31 AM UTC 24 |
| Finished | Sep 11 08:02:33 AM UTC 24 |
| Peak memory | 218596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952050275 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.952050275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_errors.2777676239 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 612700051 ps |
| CPU time | 23.11 seconds |
| Started | Sep 11 08:02:28 AM UTC 24 |
| Finished | Sep 11 08:02:53 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777676239 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2777676239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_access.2151487838 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4813495813 ps |
| CPU time | 7.98 seconds |
| Started | Sep 11 08:02:37 AM UTC 24 |
| Finished | Sep 11 08:02:46 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151487838 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2151487838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_errors.340900655 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6173462527 ps |
| CPU time | 42.81 seconds |
| Started | Sep 11 08:02:36 AM UTC 24 |
| Finished | Sep 11 08:03:20 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340900655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j tag_errors.340900655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_priority.2379590623 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 744168596 ps |
| CPU time | 5.12 seconds |
| Started | Sep 11 08:02:41 AM UTC 24 |
| Finished | Sep 11 08:02:47 AM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379590623 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_pri ority.2379590623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_prog_failure.2768659846 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 1092449816 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 08:02:35 AM UTC 24 |
| Finished | Sep 11 08:02:45 AM UTC 24 |
| Peak memory | 232100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768659846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_jtag_prog_failure.2768659846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1961454521 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 928885561 ps |
| CPU time | 28.95 seconds |
| Started | Sep 11 08:02:43 AM UTC 24 |
| Finished | Sep 11 08:03:14 AM UTC 24 |
| Peak memory | 229784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961454521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.l c_ctrl_jtag_regwen_during_op.1961454521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_smoke.1985846224 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 41932657 ps |
| CPU time | 2.27 seconds |
| Started | Sep 11 08:02:32 AM UTC 24 |
| Finished | Sep 11 08:02:35 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985846224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag _smoke.1985846224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_failure.592102554 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 2653934980 ps |
| CPU time | 104.86 seconds |
| Started | Sep 11 08:02:33 AM UTC 24 |
| Finished | Sep 11 08:04:20 AM UTC 24 |
| Peak memory | 295772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=592102554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct rl_jtag_state_failure.592102554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_jtag_state_post_trans.4039452 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 668397727 ps |
| CPU time | 22.94 seconds |
| Started | Sep 11 08:02:34 AM UTC 24 |
| Finished | Sep 11 08:02:58 AM UTC 24 |
| Peak memory | 262968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039452 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_c trl_jtag_state_post_trans.4039452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_prog_failure.1418610689 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 98440824 ps |
| CPU time | 6.82 seconds |
| Started | Sep 11 08:02:28 AM UTC 24 |
| Finished | Sep 11 08:02:36 AM UTC 24 |
| Peak memory | 232512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418610689 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1418610689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_regwen_during_op.3235867142 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 1594932758 ps |
| CPU time | 9.45 seconds |
| Started | Sep 11 08:02:30 AM UTC 24 |
| Finished | Sep 11 08:02:40 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3235867142 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3235867142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_cm.2850846068 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 1231471679 ps |
| CPU time | 50.07 seconds |
| Started | Sep 11 08:02:47 AM UTC 24 |
| Finished | Sep 11 08:03:38 AM UTC 24 |
| Peak memory | 289852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850846068 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2850846068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_mubi.1628396116 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3146782875 ps |
| CPU time | 25.16 seconds |
| Started | Sep 11 08:02:43 AM UTC 24 |
| Finished | Sep 11 08:03:10 AM UTC 24 |
| Peak memory | 232220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628396116 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1628396116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_digest.1901510369 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 437954082 ps |
| CPU time | 13.23 seconds |
| Started | Sep 11 08:02:45 AM UTC 24 |
| Finished | Sep 11 08:02:59 AM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901510369 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_t oken_digest.1901510369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_sec_token_mux.2971107813 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 590755750 ps |
| CPU time | 7.74 seconds |
| Started | Sep 11 08:02:45 AM UTC 24 |
| Finished | Sep 11 08:02:54 AM UTC 24 |
| Peak memory | 231956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971107813 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_toke n_mux.2971107813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_security_escalation.3223002004 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 947802506 ps |
| CPU time | 15.88 seconds |
| Started | Sep 11 08:02:30 AM UTC 24 |
| Finished | Sep 11 08:02:47 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223002004 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3223002004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_smoke.746374938 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 477839610 ps |
| CPU time | 4.9 seconds |
| Started | Sep 11 08:02:25 AM UTC 24 |
| Finished | Sep 11 08:02:31 AM UTC 24 |
| Peak memory | 236136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746374938 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.746374938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_failure.480244481 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 213207959 ps |
| CPU time | 46.73 seconds |
| Started | Sep 11 08:02:27 AM UTC 24 |
| Finished | Sep 11 08:03:15 AM UTC 24 |
| Peak memory | 260888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480244481 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.480244481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_state_post_trans.552873261 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 1063724061 ps |
| CPU time | 4.21 seconds |
| Started | Sep 11 08:02:27 AM UTC 24 |
| Finished | Sep 11 08:02:32 AM UTC 24 |
| Peak memory | 234568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552873261 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.552873261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2859037177 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 27852993 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:02:26 AM UTC 24 |
| Finished | Sep 11 08:02:28 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859037177 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_volatile_unlock_smoke.2859037177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/1.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_alert_test.149224418 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 65749295 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 08:06:19 AM UTC 24 |
| Finished | Sep 11 08:06:22 AM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149224418 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.149224418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_errors.1399910756 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 1343270959 ps |
| CPU time | 12.17 seconds |
| Started | Sep 11 08:06:10 AM UTC 24 |
| Finished | Sep 11 08:06:23 AM UTC 24 |
| Peak memory | 232316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399910756 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1399910756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_access.2729609851 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 66792962 ps |
| CPU time | 3.56 seconds |
| Started | Sep 11 08:06:12 AM UTC 24 |
| Finished | Sep 11 08:06:17 AM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729609851 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_acce ss.2729609851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.916485268 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 7865819915 ps |
| CPU time | 48.53 seconds |
| Started | Sep 11 08:06:11 AM UTC 24 |
| Finished | Sep 11 08:07:01 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916485268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_ jtag_errors.916485268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_prog_failure.1614172096 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 450366492 ps |
| CPU time | 11.3 seconds |
| Started | Sep 11 08:06:11 AM UTC 24 |
| Finished | Sep 11 08:06:24 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614172096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c trl_jtag_prog_failure.1614172096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_smoke.2747048216 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 610126589 ps |
| CPU time | 6.71 seconds |
| Started | Sep 11 08:06:10 AM UTC 24 |
| Finished | Sep 11 08:06:18 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747048216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta g_smoke.2747048216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3766532193 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 724922530 ps |
| CPU time | 32.42 seconds |
| Started | Sep 11 08:06:11 AM UTC 24 |
| Finished | Sep 11 08:06:45 AM UTC 24 |
| Peak memory | 262628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766532193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ ctrl_jtag_state_failure.3766532193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_post_trans.2306782395 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 1002682750 ps |
| CPU time | 13.29 seconds |
| Started | Sep 11 08:06:11 AM UTC 24 |
| Finished | Sep 11 08:06:26 AM UTC 24 |
| Peak memory | 237424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306782395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10. lc_ctrl_jtag_state_post_trans.2306782395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_prog_failure.3891607833 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 50449126 ps |
| CPU time | 2.92 seconds |
| Started | Sep 11 08:06:10 AM UTC 24 |
| Finished | Sep 11 08:06:14 AM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891607833 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3891607833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_mubi.3525013498 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 1814425219 ps |
| CPU time | 24.43 seconds |
| Started | Sep 11 08:06:14 AM UTC 24 |
| Finished | Sep 11 08:06:40 AM UTC 24 |
| Peak memory | 237896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525013498 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3525013498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_digest.3359686067 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1072592633 ps |
| CPU time | 7.91 seconds |
| Started | Sep 11 08:06:18 AM UTC 24 |
| Finished | Sep 11 08:06:27 AM UTC 24 |
| Peak memory | 236772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359686067 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_ token_digest.3359686067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_sec_token_mux.1461301669 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 548612679 ps |
| CPU time | 14.55 seconds |
| Started | Sep 11 08:06:16 AM UTC 24 |
| Finished | Sep 11 08:06:31 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461301669 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_tok en_mux.1461301669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_security_escalation.1642191462 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 4482619773 ps |
| CPU time | 11.83 seconds |
| Started | Sep 11 08:06:10 AM UTC 24 |
| Finished | Sep 11 08:06:23 AM UTC 24 |
| Peak memory | 237220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642191462 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1642191462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_smoke.2730737026 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 25754608 ps |
| CPU time | 2.3 seconds |
| Started | Sep 11 08:06:06 AM UTC 24 |
| Finished | Sep 11 08:06:09 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730737026 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.2730737026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_failure.1111664940 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 507621964 ps |
| CPU time | 56.85 seconds |
| Started | Sep 11 08:06:07 AM UTC 24 |
| Finished | Sep 11 08:07:06 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111664940 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1111664940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_state_post_trans.1711990310 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 820955022 ps |
| CPU time | 12.54 seconds |
| Started | Sep 11 08:06:08 AM UTC 24 |
| Finished | Sep 11 08:06:22 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711990310 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1711990310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.3062568923 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 12974430752 ps |
| CPU time | 205.52 seconds |
| Started | Sep 11 08:06:18 AM UTC 24 |
| Finished | Sep 11 08:09:46 AM UTC 24 |
| Peak memory | 237956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3062568923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 10.lc_ctrl_stress_all.3062568923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/10.lc_ctrl_volatile_unlock_smoke.639389934 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 25721250 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:06:07 AM UTC 24 |
| Finished | Sep 11 08:06:10 AM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639389934 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 0.lc_ctrl_volatile_unlock_smoke.639389934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/10.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_alert_test.480767099 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 26414771 ps |
| CPU time | 1.69 seconds |
| Started | Sep 11 08:06:38 AM UTC 24 |
| Finished | Sep 11 08:06:41 AM UTC 24 |
| Peak memory | 218692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480767099 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.480767099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_errors.466797788 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1544676101 ps |
| CPU time | 17.88 seconds |
| Started | Sep 11 08:06:24 AM UTC 24 |
| Finished | Sep 11 08:06:43 AM UTC 24 |
| Peak memory | 237956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466797788 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.466797788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.4104313623 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 803850793 ps |
| CPU time | 12.48 seconds |
| Started | Sep 11 08:06:29 AM UTC 24 |
| Finished | Sep 11 08:06:42 AM UTC 24 |
| Peak memory | 229228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104313623 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_acce ss.4104313623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2489270985 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 19416407578 ps |
| CPU time | 34.74 seconds |
| Started | Sep 11 08:06:29 AM UTC 24 |
| Finished | Sep 11 08:07:05 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489270985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl _jtag_errors.2489270985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_prog_failure.780478164 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 250526960 ps |
| CPU time | 5.9 seconds |
| Started | Sep 11 08:06:27 AM UTC 24 |
| Finished | Sep 11 08:06:34 AM UTC 24 |
| Peak memory | 232096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780478164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct rl_jtag_prog_failure.780478164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_smoke.1236231250 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 172694060 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 08:06:26 AM UTC 24 |
| Finished | Sep 11 08:06:31 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236231250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta g_smoke.1236231250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.2396134658 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 10953293793 ps |
| CPU time | 112.09 seconds |
| Started | Sep 11 08:06:26 AM UTC 24 |
| Finished | Sep 11 08:08:20 AM UTC 24 |
| Peak memory | 295660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396134658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ ctrl_jtag_state_failure.2396134658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.2258775897 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1095850414 ps |
| CPU time | 15.5 seconds |
| Started | Sep 11 08:06:27 AM UTC 24 |
| Finished | Sep 11 08:06:44 AM UTC 24 |
| Peak memory | 262680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258775897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11. lc_ctrl_jtag_state_post_trans.2258775897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_prog_failure.671136139 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 97986838 ps |
| CPU time | 3.02 seconds |
| Started | Sep 11 08:06:24 AM UTC 24 |
| Finished | Sep 11 08:06:28 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671136139 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.671136139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_mubi.1445795840 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 782040503 ps |
| CPU time | 34.12 seconds |
| Started | Sep 11 08:06:32 AM UTC 24 |
| Finished | Sep 11 08:07:07 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445795840 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1445795840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.2063632530 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 349718922 ps |
| CPU time | 18.07 seconds |
| Started | Sep 11 08:06:35 AM UTC 24 |
| Finished | Sep 11 08:06:54 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2063632530 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_ token_digest.2063632530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_mux.1771868530 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 228170529 ps |
| CPU time | 7.7 seconds |
| Started | Sep 11 08:06:32 AM UTC 24 |
| Finished | Sep 11 08:06:41 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771868530 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_tok en_mux.1771868530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_smoke.3757839160 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 40774201 ps |
| CPU time | 4.06 seconds |
| Started | Sep 11 08:06:22 AM UTC 24 |
| Finished | Sep 11 08:06:28 AM UTC 24 |
| Peak memory | 229864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757839160 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3757839160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.3629140999 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 303147606 ps |
| CPU time | 33.17 seconds |
| Started | Sep 11 08:06:24 AM UTC 24 |
| Finished | Sep 11 08:06:58 AM UTC 24 |
| Peak memory | 263012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629140999 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3629140999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_state_post_trans.2225860842 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 224360602 ps |
| CPU time | 12.66 seconds |
| Started | Sep 11 08:06:24 AM UTC 24 |
| Finished | Sep 11 08:06:37 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225860842 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2225860842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.3015090905 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3038369956 ps |
| CPU time | 104.09 seconds |
| Started | Sep 11 08:06:36 AM UTC 24 |
| Finished | Sep 11 08:08:22 AM UTC 24 |
| Peak memory | 273120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3015090905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 11.lc_ctrl_stress_all.3015090905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3279129993 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 3815639151 ps |
| CPU time | 119.5 seconds |
| Started | Sep 11 08:06:37 AM UTC 24 |
| Finished | Sep 11 08:08:39 AM UTC 24 |
| Peak memory | 291612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3279129993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3279129993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4003850976 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 13192681 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:06:22 AM UTC 24 |
| Finished | Sep 11 08:06:25 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003850976 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_volatile_unlock_smoke.4003850976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/11.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.2980748014 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 105379482 ps |
| CPU time | 1.54 seconds |
| Started | Sep 11 08:06:57 AM UTC 24 |
| Finished | Sep 11 08:07:00 AM UTC 24 |
| Peak memory | 217716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980748014 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.2980748014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1085430276 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 603073050 ps |
| CPU time | 19.2 seconds |
| Started | Sep 11 08:06:45 AM UTC 24 |
| Finished | Sep 11 08:07:05 AM UTC 24 |
| Peak memory | 230392 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085430276 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1085430276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.1688299885 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 630552368 ps |
| CPU time | 16.04 seconds |
| Started | Sep 11 08:06:53 AM UTC 24 |
| Finished | Sep 11 08:07:10 AM UTC 24 |
| Peak memory | 229796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688299885 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_acce ss.1688299885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.3322316658 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 5112425126 ps |
| CPU time | 42.01 seconds |
| Started | Sep 11 08:06:51 AM UTC 24 |
| Finished | Sep 11 08:07:34 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322316658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl _jtag_errors.3322316658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3230920708 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 159346621 ps |
| CPU time | 4.49 seconds |
| Started | Sep 11 08:06:51 AM UTC 24 |
| Finished | Sep 11 08:06:56 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230920708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c trl_jtag_prog_failure.3230920708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_smoke.1194082464 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 107223364 ps |
| CPU time | 4.73 seconds |
| Started | Sep 11 08:06:46 AM UTC 24 |
| Finished | Sep 11 08:06:52 AM UTC 24 |
| Peak memory | 230048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194082464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta g_smoke.1194082464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.2018258061 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2235972550 ps |
| CPU time | 95.05 seconds |
| Started | Sep 11 08:06:47 AM UTC 24 |
| Finished | Sep 11 08:08:24 AM UTC 24 |
| Peak memory | 291508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018258061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ ctrl_jtag_state_failure.2018258061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.4204379483 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 1550970075 ps |
| CPU time | 16.89 seconds |
| Started | Sep 11 08:06:48 AM UTC 24 |
| Finished | Sep 11 08:07:06 AM UTC 24 |
| Peak memory | 262648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204379483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12. lc_ctrl_jtag_state_post_trans.4204379483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_prog_failure.89553280 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 13839543 ps |
| CPU time | 2.14 seconds |
| Started | Sep 11 08:06:44 AM UTC 24 |
| Finished | Sep 11 08:06:47 AM UTC 24 |
| Peak memory | 234288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89553280 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.89553280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.3083225119 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 200971603 ps |
| CPU time | 12.28 seconds |
| Started | Sep 11 08:06:54 AM UTC 24 |
| Finished | Sep 11 08:07:07 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083225119 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3083225119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3114063495 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 1023645886 ps |
| CPU time | 8.31 seconds |
| Started | Sep 11 08:06:55 AM UTC 24 |
| Finished | Sep 11 08:07:05 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114063495 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_ token_digest.3114063495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.3873175713 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 245020675 ps |
| CPU time | 9.21 seconds |
| Started | Sep 11 08:06:55 AM UTC 24 |
| Finished | Sep 11 08:07:06 AM UTC 24 |
| Peak memory | 232048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873175713 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_tok en_mux.3873175713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.443830748 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 298314098 ps |
| CPU time | 15 seconds |
| Started | Sep 11 08:06:45 AM UTC 24 |
| Finished | Sep 11 08:07:01 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443830748 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.443830748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_smoke.1467597635 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 54404752 ps |
| CPU time | 3.8 seconds |
| Started | Sep 11 08:06:42 AM UTC 24 |
| Finished | Sep 11 08:06:46 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467597635 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1467597635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.1166146453 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 174064416 ps |
| CPU time | 28.35 seconds |
| Started | Sep 11 08:06:42 AM UTC 24 |
| Finished | Sep 11 08:07:11 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166146453 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1166146453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_state_post_trans.2615074602 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 71819234 ps |
| CPU time | 5.66 seconds |
| Started | Sep 11 08:06:43 AM UTC 24 |
| Finished | Sep 11 08:06:50 AM UTC 24 |
| Peak memory | 234500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2615074602 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2615074602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.977420444 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 6340573513 ps |
| CPU time | 78.74 seconds |
| Started | Sep 11 08:06:57 AM UTC 24 |
| Finished | Sep 11 08:08:17 AM UTC 24 |
| Peak memory | 281228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=977420444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 12.lc_ctrl_stress_all.977420444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3402245378 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2063303281 ps |
| CPU time | 91.87 seconds |
| Started | Sep 11 08:06:57 AM UTC 24 |
| Finished | Sep 11 08:08:31 AM UTC 24 |
| Peak memory | 264916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3402245378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3402245378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1842650001 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 59894968 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 08:06:42 AM UTC 24 |
| Finished | Sep 11 08:06:44 AM UTC 24 |
| Peak memory | 222900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842650001 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_volatile_unlock_smoke.1842650001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/12.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2949691821 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 54914065 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:07:12 AM UTC 24 |
| Finished | Sep 11 08:07:14 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949691821 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2949691821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_errors.1387061111 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 522747843 ps |
| CPU time | 15.98 seconds |
| Started | Sep 11 08:07:03 AM UTC 24 |
| Finished | Sep 11 08:07:20 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387061111 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.1387061111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.488378100 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 308614651 ps |
| CPU time | 6.69 seconds |
| Started | Sep 11 08:07:08 AM UTC 24 |
| Finished | Sep 11 08:07:16 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488378100 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.488378100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.3589560101 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 13361208914 ps |
| CPU time | 49.21 seconds |
| Started | Sep 11 08:07:07 AM UTC 24 |
| Finished | Sep 11 08:07:58 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589560101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl _jtag_errors.3589560101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.3330450447 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 694321662 ps |
| CPU time | 5.45 seconds |
| Started | Sep 11 08:07:07 AM UTC 24 |
| Finished | Sep 11 08:07:13 AM UTC 24 |
| Peak memory | 231908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330450447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c trl_jtag_prog_failure.3330450447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.568308217 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 103513768 ps |
| CPU time | 4.77 seconds |
| Started | Sep 11 08:07:05 AM UTC 24 |
| Finished | Sep 11 08:07:11 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568308217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag _smoke.568308217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3651094265 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2750382389 ps |
| CPU time | 76.33 seconds |
| Started | Sep 11 08:07:05 AM UTC 24 |
| Finished | Sep 11 08:08:23 AM UTC 24 |
| Peak memory | 281192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651094265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ ctrl_jtag_state_failure.3651094265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.1674752399 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 1733252257 ps |
| CPU time | 19.41 seconds |
| Started | Sep 11 08:07:07 AM UTC 24 |
| Finished | Sep 11 08:07:27 AM UTC 24 |
| Peak memory | 237656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674752399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13. lc_ctrl_jtag_state_post_trans.1674752399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.662513446 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 208741689 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 08:07:03 AM UTC 24 |
| Finished | Sep 11 08:07:07 AM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662513446 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.662513446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2052415981 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 315614335 ps |
| CPU time | 12.71 seconds |
| Started | Sep 11 08:07:08 AM UTC 24 |
| Finished | Sep 11 08:07:22 AM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052415981 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2052415981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.3270432043 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 446181467 ps |
| CPU time | 9.48 seconds |
| Started | Sep 11 08:07:08 AM UTC 24 |
| Finished | Sep 11 08:07:19 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270432043 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_ token_digest.3270432043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3033659897 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1597343598 ps |
| CPU time | 9.75 seconds |
| Started | Sep 11 08:07:08 AM UTC 24 |
| Finished | Sep 11 08:07:19 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033659897 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_tok en_mux.3033659897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.773437383 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1057895221 ps |
| CPU time | 8.52 seconds |
| Started | Sep 11 08:07:03 AM UTC 24 |
| Finished | Sep 11 08:07:13 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773437383 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.773437383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3346476925 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 110661084 ps |
| CPU time | 2.14 seconds |
| Started | Sep 11 08:06:59 AM UTC 24 |
| Finished | Sep 11 08:07:03 AM UTC 24 |
| Peak memory | 223716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346476925 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3346476925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.68795014 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 666581574 ps |
| CPU time | 42.47 seconds |
| Started | Sep 11 08:07:01 AM UTC 24 |
| Finished | Sep 11 08:07:44 AM UTC 24 |
| Peak memory | 263148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68795014 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.68795014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3538536237 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 1172987756 ps |
| CPU time | 10.98 seconds |
| Started | Sep 11 08:07:02 AM UTC 24 |
| Finished | Sep 11 08:07:14 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538536237 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3538536237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4089484612 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5083427188 ps |
| CPU time | 94.4 seconds |
| Started | Sep 11 08:07:10 AM UTC 24 |
| Finished | Sep 11 08:08:46 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4089484612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 13.lc_ctrl_stress_all.4089484612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3607640523 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 45173082 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 08:06:59 AM UTC 24 |
| Finished | Sep 11 08:07:02 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607640523 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_volatile_unlock_smoke.3607640523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/13.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.40275286 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 14125313 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:07:32 AM UTC 24 |
| Finished | Sep 11 08:07:34 AM UTC 24 |
| Peak memory | 217708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40275286 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.40275286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_errors.3599825258 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 284152280 ps |
| CPU time | 14.33 seconds |
| Started | Sep 11 08:07:15 AM UTC 24 |
| Finished | Sep 11 08:07:31 AM UTC 24 |
| Peak memory | 238160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599825258 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3599825258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.312451022 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 203540385 ps |
| CPU time | 8.4 seconds |
| Started | Sep 11 08:07:21 AM UTC 24 |
| Finished | Sep 11 08:07:31 AM UTC 24 |
| Peak memory | 229768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312451022 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.312451022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2299764134 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2734949311 ps |
| CPU time | 83.32 seconds |
| Started | Sep 11 08:07:20 AM UTC 24 |
| Finished | Sep 11 08:08:46 AM UTC 24 |
| Peak memory | 237472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299764134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl _jtag_errors.2299764134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1750225483 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 259202319 ps |
| CPU time | 10.31 seconds |
| Started | Sep 11 08:07:20 AM UTC 24 |
| Finished | Sep 11 08:07:32 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750225483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c trl_jtag_prog_failure.1750225483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.663970215 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 610246637 ps |
| CPU time | 6.76 seconds |
| Started | Sep 11 08:07:17 AM UTC 24 |
| Finished | Sep 11 08:07:24 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663970215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag _smoke.663970215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.3709755788 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 8020352202 ps |
| CPU time | 71.29 seconds |
| Started | Sep 11 08:07:20 AM UTC 24 |
| Finished | Sep 11 08:08:33 AM UTC 24 |
| Peak memory | 280952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709755788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ ctrl_jtag_state_failure.3709755788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3571694536 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 443864724 ps |
| CPU time | 30.03 seconds |
| Started | Sep 11 08:07:20 AM UTC 24 |
| Finished | Sep 11 08:07:52 AM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571694536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14. lc_ctrl_jtag_state_post_trans.3571694536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.1795664825 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 29884565 ps |
| CPU time | 2.99 seconds |
| Started | Sep 11 08:07:15 AM UTC 24 |
| Finished | Sep 11 08:07:19 AM UTC 24 |
| Peak memory | 234560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795664825 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1795664825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.2067223107 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 726648935 ps |
| CPU time | 24.36 seconds |
| Started | Sep 11 08:07:22 AM UTC 24 |
| Finished | Sep 11 08:07:48 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067223107 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2067223107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.4213301085 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 432008085 ps |
| CPU time | 18.47 seconds |
| Started | Sep 11 08:07:25 AM UTC 24 |
| Finished | Sep 11 08:07:45 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213301085 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_ token_digest.4213301085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.923031158 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 904458317 ps |
| CPU time | 7.36 seconds |
| Started | Sep 11 08:07:23 AM UTC 24 |
| Finished | Sep 11 08:07:31 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923031158 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_toke n_mux.923031158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.837378234 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 333032019 ps |
| CPU time | 14.57 seconds |
| Started | Sep 11 08:07:17 AM UTC 24 |
| Finished | Sep 11 08:07:32 AM UTC 24 |
| Peak memory | 238148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837378234 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.837378234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2634455346 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 41669966 ps |
| CPU time | 2.09 seconds |
| Started | Sep 11 08:07:12 AM UTC 24 |
| Finished | Sep 11 08:07:15 AM UTC 24 |
| Peak memory | 223772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634455346 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2634455346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.2086058197 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1231016345 ps |
| CPU time | 38.81 seconds |
| Started | Sep 11 08:07:14 AM UTC 24 |
| Finished | Sep 11 08:07:54 AM UTC 24 |
| Peak memory | 262960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086058197 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2086058197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.300113308 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 49502076 ps |
| CPU time | 5 seconds |
| Started | Sep 11 08:07:14 AM UTC 24 |
| Finished | Sep 11 08:07:20 AM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300113308 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.300113308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.1313083951 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 16433086560 ps |
| CPU time | 150.16 seconds |
| Started | Sep 11 08:07:29 AM UTC 24 |
| Finished | Sep 11 08:10:02 AM UTC 24 |
| Peak memory | 295568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1313083951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 14.lc_ctrl_stress_all.1313083951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3254851721 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 19089156 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:07:13 AM UTC 24 |
| Finished | Sep 11 08:07:16 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254851721 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_volatile_unlock_smoke.3254851721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/14.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.3069861624 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 71681423 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 08:07:52 AM UTC 24 |
| Finished | Sep 11 08:07:54 AM UTC 24 |
| Peak memory | 218760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069861624 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3069861624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_errors.345136455 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 634711126 ps |
| CPU time | 14.56 seconds |
| Started | Sep 11 08:07:36 AM UTC 24 |
| Finished | Sep 11 08:07:52 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345136455 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.345136455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.3413378910 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 109926978 ps |
| CPU time | 2.06 seconds |
| Started | Sep 11 08:07:46 AM UTC 24 |
| Finished | Sep 11 08:07:49 AM UTC 24 |
| Peak memory | 229912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413378910 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_acce ss.3413378910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.1299543979 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 1381055763 ps |
| CPU time | 51.93 seconds |
| Started | Sep 11 08:07:46 AM UTC 24 |
| Finished | Sep 11 08:08:39 AM UTC 24 |
| Peak memory | 237896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299543979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _jtag_errors.1299543979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.3325567769 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 255920080 ps |
| CPU time | 4.47 seconds |
| Started | Sep 11 08:07:43 AM UTC 24 |
| Finished | Sep 11 08:07:49 AM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325567769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c trl_jtag_prog_failure.3325567769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3164183900 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 1541489406 ps |
| CPU time | 7.81 seconds |
| Started | Sep 11 08:07:38 AM UTC 24 |
| Finished | Sep 11 08:07:47 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3164183900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta g_smoke.3164183900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.3855284421 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2211872527 ps |
| CPU time | 81.92 seconds |
| Started | Sep 11 08:07:39 AM UTC 24 |
| Finished | Sep 11 08:09:03 AM UTC 24 |
| Peak memory | 289352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855284421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ ctrl_jtag_state_failure.3855284421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.2520352335 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 798485984 ps |
| CPU time | 32.15 seconds |
| Started | Sep 11 08:07:40 AM UTC 24 |
| Finished | Sep 11 08:08:14 AM UTC 24 |
| Peak memory | 262756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2520352335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15. lc_ctrl_jtag_state_post_trans.2520352335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.2850289624 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 192048178 ps |
| CPU time | 5.28 seconds |
| Started | Sep 11 08:07:36 AM UTC 24 |
| Finished | Sep 11 08:07:42 AM UTC 24 |
| Peak memory | 236268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850289624 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2850289624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.3979960276 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 398024652 ps |
| CPU time | 11.03 seconds |
| Started | Sep 11 08:07:48 AM UTC 24 |
| Finished | Sep 11 08:08:00 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3979960276 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3979960276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.3241621925 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 316832915 ps |
| CPU time | 16.32 seconds |
| Started | Sep 11 08:07:49 AM UTC 24 |
| Finished | Sep 11 08:08:07 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241621925 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_ token_digest.3241621925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1495375939 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 1065836085 ps |
| CPU time | 14.45 seconds |
| Started | Sep 11 08:07:49 AM UTC 24 |
| Finished | Sep 11 08:08:05 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495375939 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_tok en_mux.1495375939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.1330945598 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 724542757 ps |
| CPU time | 21.83 seconds |
| Started | Sep 11 08:07:37 AM UTC 24 |
| Finished | Sep 11 08:08:00 AM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330945598 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.1330945598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.789031439 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 631137706 ps |
| CPU time | 5.13 seconds |
| Started | Sep 11 08:07:32 AM UTC 24 |
| Finished | Sep 11 08:07:38 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789031439 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.789031439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.2347147710 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 291912916 ps |
| CPU time | 35.67 seconds |
| Started | Sep 11 08:07:33 AM UTC 24 |
| Finished | Sep 11 08:08:10 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347147710 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2347147710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.16747602 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 124275821 ps |
| CPU time | 14.88 seconds |
| Started | Sep 11 08:07:35 AM UTC 24 |
| Finished | Sep 11 08:07:51 AM UTC 24 |
| Peak memory | 262904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16747602 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.16747602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.1914498296 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2432189209 ps |
| CPU time | 26.64 seconds |
| Started | Sep 11 08:07:49 AM UTC 24 |
| Finished | Sep 11 08:08:17 AM UTC 24 |
| Peak memory | 238344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1914498296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 15.lc_ctrl_stress_all.1914498296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2630414806 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 62260375 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:07:33 AM UTC 24 |
| Finished | Sep 11 08:07:36 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630414806 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_volatile_unlock_smoke.2630414806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/15.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.1645715640 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 28371938 ps |
| CPU time | 1.47 seconds |
| Started | Sep 11 08:08:12 AM UTC 24 |
| Finished | Sep 11 08:08:15 AM UTC 24 |
| Peak memory | 218924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645715640 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.1645715640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1609501603 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 511905719 ps |
| CPU time | 12.79 seconds |
| Started | Sep 11 08:07:58 AM UTC 24 |
| Finished | Sep 11 08:08:11 AM UTC 24 |
| Peak memory | 232312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609501603 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1609501603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.4068816925 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 633382231 ps |
| CPU time | 11.31 seconds |
| Started | Sep 11 08:08:05 AM UTC 24 |
| Finished | Sep 11 08:08:18 AM UTC 24 |
| Peak memory | 229944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068816925 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_acce ss.4068816925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.1739827223 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 8770090200 ps |
| CPU time | 37.09 seconds |
| Started | Sep 11 08:08:01 AM UTC 24 |
| Finished | Sep 11 08:08:40 AM UTC 24 |
| Peak memory | 232312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739827223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl _jtag_errors.1739827223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.164886260 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 333606709 ps |
| CPU time | 14.55 seconds |
| Started | Sep 11 08:08:01 AM UTC 24 |
| Finished | Sep 11 08:08:17 AM UTC 24 |
| Peak memory | 232104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164886260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct rl_jtag_prog_failure.164886260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.2314435132 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 1510671761 ps |
| CPU time | 9.67 seconds |
| Started | Sep 11 08:07:59 AM UTC 24 |
| Finished | Sep 11 08:08:10 AM UTC 24 |
| Peak memory | 229804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314435132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta g_smoke.2314435132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.1097270756 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1353497272 ps |
| CPU time | 49.38 seconds |
| Started | Sep 11 08:08:01 AM UTC 24 |
| Finished | Sep 11 08:08:52 AM UTC 24 |
| Peak memory | 281460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097270756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ ctrl_jtag_state_failure.1097270756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3446774233 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 4651024649 ps |
| CPU time | 23.15 seconds |
| Started | Sep 11 08:08:01 AM UTC 24 |
| Finished | Sep 11 08:08:25 AM UTC 24 |
| Peak memory | 256592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446774233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16. lc_ctrl_jtag_state_post_trans.3446774233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.2199441025 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 64030480 ps |
| CPU time | 2.63 seconds |
| Started | Sep 11 08:07:56 AM UTC 24 |
| Finished | Sep 11 08:08:00 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199441025 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2199441025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.3424877172 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 403007739 ps |
| CPU time | 17.86 seconds |
| Started | Sep 11 08:08:08 AM UTC 24 |
| Finished | Sep 11 08:08:27 AM UTC 24 |
| Peak memory | 238160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424877172 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3424877172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1690579463 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 1751636268 ps |
| CPU time | 15.06 seconds |
| Started | Sep 11 08:08:10 AM UTC 24 |
| Finished | Sep 11 08:08:26 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690579463 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_ token_digest.1690579463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.39587101 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 874546669 ps |
| CPU time | 8.36 seconds |
| Started | Sep 11 08:08:08 AM UTC 24 |
| Finished | Sep 11 08:08:17 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39587101 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token _mux.39587101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.2464972829 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 302537145 ps |
| CPU time | 10.34 seconds |
| Started | Sep 11 08:07:58 AM UTC 24 |
| Finished | Sep 11 08:08:09 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464972829 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2464972829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.836855214 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 79541528 ps |
| CPU time | 2.23 seconds |
| Started | Sep 11 08:07:53 AM UTC 24 |
| Finished | Sep 11 08:07:56 AM UTC 24 |
| Peak memory | 223456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836855214 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.836855214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.2516881618 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 1065339465 ps |
| CPU time | 41.59 seconds |
| Started | Sep 11 08:07:55 AM UTC 24 |
| Finished | Sep 11 08:08:38 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516881618 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2516881618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1459097380 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 46429745 ps |
| CPU time | 4.32 seconds |
| Started | Sep 11 08:07:55 AM UTC 24 |
| Finished | Sep 11 08:08:01 AM UTC 24 |
| Peak memory | 234564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459097380 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1459097380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.4157145410 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 87957272365 ps |
| CPU time | 130.64 seconds |
| Started | Sep 11 08:08:10 AM UTC 24 |
| Finished | Sep 11 08:10:23 AM UTC 24 |
| Peak memory | 295592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4157145410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 16.lc_ctrl_stress_all.4157145410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.97556174 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 45123568 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:07:53 AM UTC 24 |
| Finished | Sep 11 08:07:55 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97556174 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16 .lc_ctrl_volatile_unlock_smoke.97556174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/16.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.59951607 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 20933261 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:08:26 AM UTC 24 |
| Finished | Sep 11 08:08:28 AM UTC 24 |
| Peak memory | 218744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59951607 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.59951607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_errors.1346520078 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3910991127 ps |
| CPU time | 13.73 seconds |
| Started | Sep 11 08:08:19 AM UTC 24 |
| Finished | Sep 11 08:08:34 AM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346520078 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1346520078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1423084634 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 116147155 ps |
| CPU time | 5.34 seconds |
| Started | Sep 11 08:08:25 AM UTC 24 |
| Finished | Sep 11 08:08:31 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423084634 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_acce ss.1423084634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3434480522 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 13038652295 ps |
| CPU time | 49.68 seconds |
| Started | Sep 11 08:08:23 AM UTC 24 |
| Finished | Sep 11 08:09:14 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434480522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _jtag_errors.3434480522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3229781931 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2319279945 ps |
| CPU time | 27.83 seconds |
| Started | Sep 11 08:08:22 AM UTC 24 |
| Finished | Sep 11 08:08:51 AM UTC 24 |
| Peak memory | 234280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229781931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c trl_jtag_prog_failure.3229781931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.4101529642 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 129135100 ps |
| CPU time | 3.88 seconds |
| Started | Sep 11 08:08:19 AM UTC 24 |
| Finished | Sep 11 08:08:24 AM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101529642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta g_smoke.4101529642 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.2200599805 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 26104728242 ps |
| CPU time | 37.78 seconds |
| Started | Sep 11 08:08:22 AM UTC 24 |
| Finished | Sep 11 08:09:01 AM UTC 24 |
| Peak memory | 283228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2200599805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ ctrl_jtag_state_failure.2200599805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.3437488391 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2147479410 ps |
| CPU time | 10.12 seconds |
| Started | Sep 11 08:08:22 AM UTC 24 |
| Finished | Sep 11 08:08:33 AM UTC 24 |
| Peak memory | 236740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437488391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17. lc_ctrl_jtag_state_post_trans.3437488391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.315437588 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 255827395 ps |
| CPU time | 5.18 seconds |
| Started | Sep 11 08:08:19 AM UTC 24 |
| Finished | Sep 11 08:08:25 AM UTC 24 |
| Peak memory | 232348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315437588 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.315437588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.3827764494 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 490815015 ps |
| CPU time | 17.04 seconds |
| Started | Sep 11 08:08:25 AM UTC 24 |
| Finished | Sep 11 08:08:43 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827764494 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3827764494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.4175554234 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 295112200 ps |
| CPU time | 15.06 seconds |
| Started | Sep 11 08:08:26 AM UTC 24 |
| Finished | Sep 11 08:08:42 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175554234 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_ token_digest.4175554234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.333280097 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 185427023 ps |
| CPU time | 6.12 seconds |
| Started | Sep 11 08:08:26 AM UTC 24 |
| Finished | Sep 11 08:08:33 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333280097 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_toke n_mux.333280097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2103334834 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 485836493 ps |
| CPU time | 12.62 seconds |
| Started | Sep 11 08:08:19 AM UTC 24 |
| Finished | Sep 11 08:08:33 AM UTC 24 |
| Peak memory | 232356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103334834 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2103334834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.3516136285 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 288172266 ps |
| CPU time | 3.65 seconds |
| Started | Sep 11 08:08:15 AM UTC 24 |
| Finished | Sep 11 08:08:20 AM UTC 24 |
| Peak memory | 230184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516136285 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3516136285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2837733472 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 210653753 ps |
| CPU time | 26.21 seconds |
| Started | Sep 11 08:08:18 AM UTC 24 |
| Finished | Sep 11 08:08:45 AM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837733472 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2837733472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3959196355 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 149317209 ps |
| CPU time | 6.38 seconds |
| Started | Sep 11 08:08:18 AM UTC 24 |
| Finished | Sep 11 08:08:25 AM UTC 24 |
| Peak memory | 236612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959196355 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3959196355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.1164957012 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 10711608359 ps |
| CPU time | 121.9 seconds |
| Started | Sep 11 08:08:26 AM UTC 24 |
| Finished | Sep 11 08:10:30 AM UTC 24 |
| Peak memory | 295584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1164957012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 17.lc_ctrl_stress_all.1164957012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.3347467835 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 1813618445 ps |
| CPU time | 30.72 seconds |
| Started | Sep 11 08:08:26 AM UTC 24 |
| Finished | Sep 11 08:08:58 AM UTC 24 |
| Peak memory | 252704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347467835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.3347467835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.37008907 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 24565221 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:08:16 AM UTC 24 |
| Finished | Sep 11 08:08:18 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37008907 -as sert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17 .lc_ctrl_volatile_unlock_smoke.37008907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/17.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.1679867551 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 31425685 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 08:08:41 AM UTC 24 |
| Finished | Sep 11 08:08:44 AM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679867551 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1679867551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3809600026 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 219548773 ps |
| CPU time | 14.08 seconds |
| Started | Sep 11 08:08:32 AM UTC 24 |
| Finished | Sep 11 08:08:48 AM UTC 24 |
| Peak memory | 230120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809600026 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3809600026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.2798470609 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 3386422283 ps |
| CPU time | 17.86 seconds |
| Started | Sep 11 08:08:35 AM UTC 24 |
| Finished | Sep 11 08:08:54 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798470609 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_acce ss.2798470609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.1847281919 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 1063202795 ps |
| CPU time | 34.22 seconds |
| Started | Sep 11 08:08:34 AM UTC 24 |
| Finished | Sep 11 08:09:09 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847281919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl _jtag_errors.1847281919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.3522501921 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 706927584 ps |
| CPU time | 19.87 seconds |
| Started | Sep 11 08:08:34 AM UTC 24 |
| Finished | Sep 11 08:08:55 AM UTC 24 |
| Peak memory | 237496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522501921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c trl_jtag_prog_failure.3522501921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.3959440061 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 219076859 ps |
| CPU time | 6.27 seconds |
| Started | Sep 11 08:08:32 AM UTC 24 |
| Finished | Sep 11 08:08:40 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959440061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta g_smoke.3959440061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.3169676958 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2124193710 ps |
| CPU time | 56.3 seconds |
| Started | Sep 11 08:08:34 AM UTC 24 |
| Finished | Sep 11 08:09:31 AM UTC 24 |
| Peak memory | 283168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169676958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ ctrl_jtag_state_failure.3169676958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.1909326213 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3411090705 ps |
| CPU time | 15.59 seconds |
| Started | Sep 11 08:08:34 AM UTC 24 |
| Finished | Sep 11 08:08:50 AM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909326213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18. lc_ctrl_jtag_state_post_trans.1909326213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.953232015 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 167591620 ps |
| CPU time | 2.17 seconds |
| Started | Sep 11 08:08:32 AM UTC 24 |
| Finished | Sep 11 08:08:35 AM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953232015 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.953232015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.2121497813 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 1637414740 ps |
| CPU time | 19.13 seconds |
| Started | Sep 11 08:08:35 AM UTC 24 |
| Finished | Sep 11 08:08:55 AM UTC 24 |
| Peak memory | 238096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121497813 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2121497813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.1455098423 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 230328334 ps |
| CPU time | 13.06 seconds |
| Started | Sep 11 08:08:39 AM UTC 24 |
| Finished | Sep 11 08:08:53 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455098423 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_ token_digest.1455098423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.4092505889 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 324231595 ps |
| CPU time | 11.16 seconds |
| Started | Sep 11 08:08:36 AM UTC 24 |
| Finished | Sep 11 08:08:48 AM UTC 24 |
| Peak memory | 238204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4092505889 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_tok en_mux.4092505889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.1610705531 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 1350087768 ps |
| CPU time | 11.35 seconds |
| Started | Sep 11 08:08:32 AM UTC 24 |
| Finished | Sep 11 08:08:45 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1610705531 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1610705531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1956932469 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 113071890 ps |
| CPU time | 3.13 seconds |
| Started | Sep 11 08:08:27 AM UTC 24 |
| Finished | Sep 11 08:08:32 AM UTC 24 |
| Peak memory | 225536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956932469 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1956932469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.4200156003 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 194420880 ps |
| CPU time | 33.42 seconds |
| Started | Sep 11 08:08:30 AM UTC 24 |
| Finished | Sep 11 08:09:04 AM UTC 24 |
| Peak memory | 260688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200156003 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.4200156003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.1634438901 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 139778925 ps |
| CPU time | 13.99 seconds |
| Started | Sep 11 08:08:31 AM UTC 24 |
| Finished | Sep 11 08:08:46 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1634438901 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1634438901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.917083134 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 19435011257 ps |
| CPU time | 161.17 seconds |
| Started | Sep 11 08:08:41 AM UTC 24 |
| Finished | Sep 11 08:11:25 AM UTC 24 |
| Peak memory | 279152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=917083134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 18.lc_ctrl_stress_all.917083134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3155117475 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 24095910 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:08:27 AM UTC 24 |
| Finished | Sep 11 08:08:30 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155117475 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_volatile_unlock_smoke.3155117475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/18.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1468722216 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 13493550 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:08:53 AM UTC 24 |
| Finished | Sep 11 08:08:56 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468722216 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1468722216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_errors.894681413 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 486355420 ps |
| CPU time | 15.95 seconds |
| Started | Sep 11 08:08:45 AM UTC 24 |
| Finished | Sep 11 08:09:02 AM UTC 24 |
| Peak memory | 237956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894681413 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.894681413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.392530 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 205206495 ps |
| CPU time | 2.24 seconds |
| Started | Sep 11 08:08:49 AM UTC 24 |
| Finished | Sep 11 08:08:52 AM UTC 24 |
| Peak memory | 229984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392530 -assert nopostp roc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.392530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.760134526 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 4549436906 ps |
| CPU time | 44.32 seconds |
| Started | Sep 11 08:08:48 AM UTC 24 |
| Finished | Sep 11 08:09:33 AM UTC 24 |
| Peak memory | 237896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760134526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_ jtag_errors.760134526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.123657385 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 227802117 ps |
| CPU time | 5.38 seconds |
| Started | Sep 11 08:08:48 AM UTC 24 |
| Finished | Sep 11 08:08:54 AM UTC 24 |
| Peak memory | 232104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123657385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct rl_jtag_prog_failure.123657385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2794794995 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 656155998 ps |
| CPU time | 11.12 seconds |
| Started | Sep 11 08:08:46 AM UTC 24 |
| Finished | Sep 11 08:08:58 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2794794995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta g_smoke.2794794995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.1668546570 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 13142934968 ps |
| CPU time | 79.54 seconds |
| Started | Sep 11 08:08:47 AM UTC 24 |
| Finished | Sep 11 08:10:09 AM UTC 24 |
| Peak memory | 281100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668546570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ ctrl_jtag_state_failure.1668546570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.4237442471 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 4486369700 ps |
| CPU time | 19.2 seconds |
| Started | Sep 11 08:08:48 AM UTC 24 |
| Finished | Sep 11 08:09:08 AM UTC 24 |
| Peak memory | 262912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237442471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19. lc_ctrl_jtag_state_post_trans.4237442471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.605499451 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 78634632 ps |
| CPU time | 5.78 seconds |
| Started | Sep 11 08:08:45 AM UTC 24 |
| Finished | Sep 11 08:08:52 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605499451 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.605499451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.1245310614 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 1557822112 ps |
| CPU time | 12.01 seconds |
| Started | Sep 11 08:08:49 AM UTC 24 |
| Finished | Sep 11 08:09:02 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245310614 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1245310614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.251788212 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 214030378 ps |
| CPU time | 11.37 seconds |
| Started | Sep 11 08:08:52 AM UTC 24 |
| Finished | Sep 11 08:09:05 AM UTC 24 |
| Peak memory | 232028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251788212 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_t oken_digest.251788212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3980817586 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 505324744 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 08:08:51 AM UTC 24 |
| Finished | Sep 11 08:09:01 AM UTC 24 |
| Peak memory | 237900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980817586 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_tok en_mux.3980817586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.2120627154 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 554889155 ps |
| CPU time | 9.89 seconds |
| Started | Sep 11 08:08:46 AM UTC 24 |
| Finished | Sep 11 08:08:57 AM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120627154 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2120627154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.1443942717 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 41716055 ps |
| CPU time | 3.82 seconds |
| Started | Sep 11 08:08:41 AM UTC 24 |
| Finished | Sep 11 08:08:46 AM UTC 24 |
| Peak memory | 225888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443942717 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1443942717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.3941934853 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 332398451 ps |
| CPU time | 44.43 seconds |
| Started | Sep 11 08:08:44 AM UTC 24 |
| Finished | Sep 11 08:09:29 AM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941934853 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3941934853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.1106586589 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 853242918 ps |
| CPU time | 11.18 seconds |
| Started | Sep 11 08:08:44 AM UTC 24 |
| Finished | Sep 11 08:08:56 AM UTC 24 |
| Peak memory | 262720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106586589 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1106586589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.1550446662 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2991832535 ps |
| CPU time | 81.74 seconds |
| Started | Sep 11 08:08:52 AM UTC 24 |
| Finished | Sep 11 08:10:16 AM UTC 24 |
| Peak memory | 262888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1550446662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 19.lc_ctrl_stress_all.1550446662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.2249686421 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 2569498818 ps |
| CPU time | 99.23 seconds |
| Started | Sep 11 08:08:53 AM UTC 24 |
| Finished | Sep 11 08:10:34 AM UTC 24 |
| Peak memory | 279320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249686421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.2249686421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.433247963 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 29999308 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:08:41 AM UTC 24 |
| Finished | Sep 11 08:08:44 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433247963 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1 9.lc_ctrl_volatile_unlock_smoke.433247963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/19.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_alert_test.3345591520 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 16470573 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 08:03:16 AM UTC 24 |
| Finished | Sep 11 08:03:19 AM UTC 24 |
| Peak memory | 219044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345591520 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3345591520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_claim_transition_if.3943171021 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 12662211 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:02:59 AM UTC 24 |
| Finished | Sep 11 08:03:02 AM UTC 24 |
| Peak memory | 217296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943171021 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3943171021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_access.354926504 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 404079495 ps |
| CPU time | 14.66 seconds |
| Started | Sep 11 08:03:05 AM UTC 24 |
| Finished | Sep 11 08:03:21 AM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354926504 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.354926504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_errors.2526759877 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1531650148 ps |
| CPU time | 46.8 seconds |
| Started | Sep 11 08:03:03 AM UTC 24 |
| Finished | Sep 11 08:03:52 AM UTC 24 |
| Peak memory | 237504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526759877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ jtag_errors.2526759877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_priority.1413044120 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 320956769 ps |
| CPU time | 4.34 seconds |
| Started | Sep 11 08:03:07 AM UTC 24 |
| Finished | Sep 11 08:03:13 AM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413044120 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_pri ority.1413044120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_prog_failure.2904806803 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 747718520 ps |
| CPU time | 7.83 seconds |
| Started | Sep 11 08:03:03 AM UTC 24 |
| Finished | Sep 11 08:03:12 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904806803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct rl_jtag_prog_failure.2904806803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3353316885 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 677296602 ps |
| CPU time | 18.15 seconds |
| Started | Sep 11 08:03:10 AM UTC 24 |
| Finished | Sep 11 08:03:29 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3353316885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_jtag_regwen_during_op.3353316885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_smoke.358876911 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 810543267 ps |
| CPU time | 5.8 seconds |
| Started | Sep 11 08:02:59 AM UTC 24 |
| Finished | Sep 11 08:03:07 AM UTC 24 |
| Peak memory | 229780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358876911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_ smoke.358876911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_failure.1932176089 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5015992075 ps |
| CPU time | 79.42 seconds |
| Started | Sep 11 08:03:01 AM UTC 24 |
| Finished | Sep 11 08:04:22 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932176089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_c trl_jtag_state_failure.1932176089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_jtag_state_post_trans.1736216975 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 390904923 ps |
| CPU time | 17.36 seconds |
| Started | Sep 11 08:03:01 AM UTC 24 |
| Finished | Sep 11 08:03:19 AM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736216975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.l c_ctrl_jtag_state_post_trans.1736216975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_prog_failure.448063810 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 80354713 ps |
| CPU time | 3.71 seconds |
| Started | Sep 11 08:02:54 AM UTC 24 |
| Finished | Sep 11 08:02:59 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448063810 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.448063810 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_regwen_during_op.3819842426 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 894741543 ps |
| CPU time | 15.04 seconds |
| Started | Sep 11 08:02:56 AM UTC 24 |
| Finished | Sep 11 08:03:13 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819842426 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3819842426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_cm.1815980368 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 421965904 ps |
| CPU time | 45.25 seconds |
| Started | Sep 11 08:03:14 AM UTC 24 |
| Finished | Sep 11 08:04:01 AM UTC 24 |
| Peak memory | 298152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815980368 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1815980368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_digest.1079388567 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 994499383 ps |
| CPU time | 11.92 seconds |
| Started | Sep 11 08:03:13 AM UTC 24 |
| Finished | Sep 11 08:03:26 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079388567 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_t oken_digest.1079388567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_sec_token_mux.2002527974 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 179630959 ps |
| CPU time | 8.84 seconds |
| Started | Sep 11 08:03:12 AM UTC 24 |
| Finished | Sep 11 08:03:22 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002527974 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_toke n_mux.2002527974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_security_escalation.3085012424 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 407822687 ps |
| CPU time | 12.5 seconds |
| Started | Sep 11 08:02:55 AM UTC 24 |
| Finished | Sep 11 08:03:09 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085012424 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3085012424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_smoke.466450616 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 325452763 ps |
| CPU time | 5.34 seconds |
| Started | Sep 11 08:02:48 AM UTC 24 |
| Finished | Sep 11 08:02:55 AM UTC 24 |
| Peak memory | 236260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466450616 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.466450616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_failure.1034418653 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 291328556 ps |
| CPU time | 59.1 seconds |
| Started | Sep 11 08:02:52 AM UTC 24 |
| Finished | Sep 11 08:03:52 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034418653 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1034418653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_state_post_trans.2000364139 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 85890732 ps |
| CPU time | 5.67 seconds |
| Started | Sep 11 08:02:53 AM UTC 24 |
| Finished | Sep 11 08:02:59 AM UTC 24 |
| Peak memory | 234760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000364139 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2000364139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2623539011 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 1607199976 ps |
| CPU time | 51.01 seconds |
| Started | Sep 11 08:03:13 AM UTC 24 |
| Finished | Sep 11 08:04:06 AM UTC 24 |
| Peak memory | 281296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623539011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2623539011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/2.lc_ctrl_volatile_unlock_smoke.434371180 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 31039183 ps |
| CPU time | 1.39 seconds |
| Started | Sep 11 08:02:49 AM UTC 24 |
| Finished | Sep 11 08:02:52 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434371180 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 .lc_ctrl_volatile_unlock_smoke.434371180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/2.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.1436141412 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 69613465 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:09:02 AM UTC 24 |
| Finished | Sep 11 08:09:04 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1436141412 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1436141412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2479655324 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 2902582890 ps |
| CPU time | 14.98 seconds |
| Started | Sep 11 08:08:57 AM UTC 24 |
| Finished | Sep 11 08:09:13 AM UTC 24 |
| Peak memory | 237952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479655324 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2479655324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.4118062505 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 832030085 ps |
| CPU time | 10.87 seconds |
| Started | Sep 11 08:08:58 AM UTC 24 |
| Finished | Sep 11 08:09:10 AM UTC 24 |
| Peak memory | 229480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118062505 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_acce ss.4118062505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.10897578 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 85933723 ps |
| CPU time | 4.22 seconds |
| Started | Sep 11 08:08:56 AM UTC 24 |
| Finished | Sep 11 08:09:02 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10897578 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.10897578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1288292846 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2108530383 ps |
| CPU time | 15.43 seconds |
| Started | Sep 11 08:08:58 AM UTC 24 |
| Finished | Sep 11 08:09:15 AM UTC 24 |
| Peak memory | 238256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288292846 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1288292846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2008434102 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 454752073 ps |
| CPU time | 11.17 seconds |
| Started | Sep 11 08:09:00 AM UTC 24 |
| Finished | Sep 11 08:09:12 AM UTC 24 |
| Peak memory | 237976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008434102 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_ token_digest.2008434102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3933808620 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 936824210 ps |
| CPU time | 10.1 seconds |
| Started | Sep 11 08:09:00 AM UTC 24 |
| Finished | Sep 11 08:09:11 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933808620 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_tok en_mux.3933808620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.4183581325 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 25687711 ps |
| CPU time | 2.82 seconds |
| Started | Sep 11 08:08:55 AM UTC 24 |
| Finished | Sep 11 08:08:58 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183581325 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.4183581325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2352269550 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 609581401 ps |
| CPU time | 46.73 seconds |
| Started | Sep 11 08:08:55 AM UTC 24 |
| Finished | Sep 11 08:09:43 AM UTC 24 |
| Peak memory | 260696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352269550 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2352269550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.657247470 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 100129698 ps |
| CPU time | 12.74 seconds |
| Started | Sep 11 08:08:56 AM UTC 24 |
| Finished | Sep 11 08:09:10 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657247470 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.657247470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3584606977 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 34093165485 ps |
| CPU time | 264.73 seconds |
| Started | Sep 11 08:09:00 AM UTC 24 |
| Finished | Sep 11 08:13:28 AM UTC 24 |
| Peak memory | 295716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3584606977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 20.lc_ctrl_stress_all.3584606977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2651484211 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 31094657 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 08:08:55 AM UTC 24 |
| Finished | Sep 11 08:08:57 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651484211 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_volatile_unlock_smoke.2651484211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/20.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.2180132163 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 101369220 ps |
| CPU time | 1.55 seconds |
| Started | Sep 11 08:09:11 AM UTC 24 |
| Finished | Sep 11 08:09:13 AM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180132163 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2180132163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1737995686 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 523339524 ps |
| CPU time | 14.07 seconds |
| Started | Sep 11 08:09:06 AM UTC 24 |
| Finished | Sep 11 08:09:21 AM UTC 24 |
| Peak memory | 230268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737995686 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1737995686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1307728547 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 369004160 ps |
| CPU time | 8.08 seconds |
| Started | Sep 11 08:09:06 AM UTC 24 |
| Finished | Sep 11 08:09:16 AM UTC 24 |
| Peak memory | 230136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307728547 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_acce ss.1307728547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2482576018 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 107953829 ps |
| CPU time | 1.95 seconds |
| Started | Sep 11 08:09:05 AM UTC 24 |
| Finished | Sep 11 08:09:08 AM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482576018 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2482576018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1688514278 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 752180070 ps |
| CPU time | 18.09 seconds |
| Started | Sep 11 08:09:06 AM UTC 24 |
| Finished | Sep 11 08:09:26 AM UTC 24 |
| Peak memory | 237996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688514278 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1688514278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.2700176519 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 1745626611 ps |
| CPU time | 17.7 seconds |
| Started | Sep 11 08:09:07 AM UTC 24 |
| Finished | Sep 11 08:09:26 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700176519 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_ token_digest.2700176519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2620094964 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 1428418688 ps |
| CPU time | 9.52 seconds |
| Started | Sep 11 08:09:07 AM UTC 24 |
| Finished | Sep 11 08:09:18 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620094964 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_tok en_mux.2620094964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1075231246 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 1024499833 ps |
| CPU time | 9.84 seconds |
| Started | Sep 11 08:09:06 AM UTC 24 |
| Finished | Sep 11 08:09:17 AM UTC 24 |
| Peak memory | 237144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075231246 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.1075231246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.1596287162 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 70211572 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:09:03 AM UTC 24 |
| Finished | Sep 11 08:09:06 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596287162 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1596287162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.2453072916 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 672813222 ps |
| CPU time | 46.8 seconds |
| Started | Sep 11 08:09:03 AM UTC 24 |
| Finished | Sep 11 08:09:52 AM UTC 24 |
| Peak memory | 263032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453072916 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2453072916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.3575944700 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 52340214 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 08:09:05 AM UTC 24 |
| Finished | Sep 11 08:09:15 AM UTC 24 |
| Peak memory | 262728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575944700 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3575944700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.3267083624 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3038303766 ps |
| CPU time | 125.65 seconds |
| Started | Sep 11 08:09:08 AM UTC 24 |
| Finished | Sep 11 08:11:16 AM UTC 24 |
| Peak memory | 281312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3267083624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 21.lc_ctrl_stress_all.3267083624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.4293419655 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 144992589 ps |
| CPU time | 1.1 seconds |
| Started | Sep 11 08:09:03 AM UTC 24 |
| Finished | Sep 11 08:09:06 AM UTC 24 |
| Peak memory | 218484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293419655 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_volatile_unlock_smoke.4293419655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/21.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.527085314 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 17831485 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:09:17 AM UTC 24 |
| Finished | Sep 11 08:09:20 AM UTC 24 |
| Peak memory | 219048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=527085314 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.527085314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_errors.2278601720 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 609285332 ps |
| CPU time | 10.33 seconds |
| Started | Sep 11 08:09:14 AM UTC 24 |
| Finished | Sep 11 08:09:26 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278601720 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2278601720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.1107771184 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 1991920598 ps |
| CPU time | 12.83 seconds |
| Started | Sep 11 08:09:14 AM UTC 24 |
| Finished | Sep 11 08:09:28 AM UTC 24 |
| Peak memory | 229964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107771184 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_acce ss.1107771184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.3395195018 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 37514190 ps |
| CPU time | 2.61 seconds |
| Started | Sep 11 08:09:13 AM UTC 24 |
| Finished | Sep 11 08:09:17 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395195018 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3395195018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.884896407 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2573961814 ps |
| CPU time | 22.79 seconds |
| Started | Sep 11 08:09:16 AM UTC 24 |
| Finished | Sep 11 08:09:40 AM UTC 24 |
| Peak memory | 232492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884896407 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.884896407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.3574021133 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 386984647 ps |
| CPU time | 14.93 seconds |
| Started | Sep 11 08:09:16 AM UTC 24 |
| Finished | Sep 11 08:09:32 AM UTC 24 |
| Peak memory | 237968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574021133 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_ token_digest.3574021133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.289632066 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 347059853 ps |
| CPU time | 14.78 seconds |
| Started | Sep 11 08:09:16 AM UTC 24 |
| Finished | Sep 11 08:09:32 AM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289632066 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_toke n_mux.289632066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.814721238 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 648132218 ps |
| CPU time | 14.13 seconds |
| Started | Sep 11 08:09:14 AM UTC 24 |
| Finished | Sep 11 08:09:30 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814721238 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.814721238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.3664111557 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 23997012 ps |
| CPU time | 2.6 seconds |
| Started | Sep 11 08:09:11 AM UTC 24 |
| Finished | Sep 11 08:09:14 AM UTC 24 |
| Peak memory | 229860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664111557 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3664111557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1747026041 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 166311804 ps |
| CPU time | 38.57 seconds |
| Started | Sep 11 08:09:12 AM UTC 24 |
| Finished | Sep 11 08:09:52 AM UTC 24 |
| Peak memory | 260780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747026041 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.1747026041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1137468979 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 159754041 ps |
| CPU time | 3.49 seconds |
| Started | Sep 11 08:09:12 AM UTC 24 |
| Finished | Sep 11 08:09:17 AM UTC 24 |
| Peak memory | 234820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137468979 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1137468979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all.1492941519 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 6581079516 ps |
| CPU time | 93.45 seconds |
| Started | Sep 11 08:09:16 AM UTC 24 |
| Finished | Sep 11 08:10:52 AM UTC 24 |
| Peak memory | 281232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1492941519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 22.lc_ctrl_stress_all.1492941519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2657928125 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 21215560972 ps |
| CPU time | 163.14 seconds |
| Started | Sep 11 08:09:16 AM UTC 24 |
| Finished | Sep 11 08:12:02 AM UTC 24 |
| Peak memory | 433088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2657928125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2657928125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2412734959 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 94732379 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 08:09:12 AM UTC 24 |
| Finished | Sep 11 08:09:14 AM UTC 24 |
| Peak memory | 222968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2412734959 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_volatile_unlock_smoke.2412734959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/22.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.72900086 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 69209318 ps |
| CPU time | 1.67 seconds |
| Started | Sep 11 08:09:30 AM UTC 24 |
| Finished | Sep 11 08:09:33 AM UTC 24 |
| Peak memory | 218624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72900086 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.72900086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_errors.484357160 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 482438801 ps |
| CPU time | 17.22 seconds |
| Started | Sep 11 08:09:22 AM UTC 24 |
| Finished | Sep 11 08:09:40 AM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484357160 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.484357160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2790175570 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 234430125 ps |
| CPU time | 2.12 seconds |
| Started | Sep 11 08:09:23 AM UTC 24 |
| Finished | Sep 11 08:09:26 AM UTC 24 |
| Peak memory | 229632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790175570 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_acce ss.2790175570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.3861109843 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 478680092 ps |
| CPU time | 8.05 seconds |
| Started | Sep 11 08:09:21 AM UTC 24 |
| Finished | Sep 11 08:09:30 AM UTC 24 |
| Peak memory | 236268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861109843 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3861109843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.2382156967 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 501955379 ps |
| CPU time | 13.49 seconds |
| Started | Sep 11 08:09:26 AM UTC 24 |
| Finished | Sep 11 08:09:41 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382156967 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2382156967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.1527091761 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 906180947 ps |
| CPU time | 14.3 seconds |
| Started | Sep 11 08:09:28 AM UTC 24 |
| Finished | Sep 11 08:09:43 AM UTC 24 |
| Peak memory | 238156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527091761 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_ token_digest.1527091761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1879427598 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 287602576 ps |
| CPU time | 14.42 seconds |
| Started | Sep 11 08:09:26 AM UTC 24 |
| Finished | Sep 11 08:09:42 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879427598 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_tok en_mux.1879427598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.370432656 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 251526372 ps |
| CPU time | 12.8 seconds |
| Started | Sep 11 08:09:23 AM UTC 24 |
| Finished | Sep 11 08:09:37 AM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370432656 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.370432656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.942947561 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 112694615 ps |
| CPU time | 3.16 seconds |
| Started | Sep 11 08:09:17 AM UTC 24 |
| Finished | Sep 11 08:09:22 AM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942947561 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.942947561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.1377802408 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 1274228367 ps |
| CPU time | 41.51 seconds |
| Started | Sep 11 08:09:19 AM UTC 24 |
| Finished | Sep 11 08:10:02 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1377802408 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1377802408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.827130006 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 328395542 ps |
| CPU time | 14.5 seconds |
| Started | Sep 11 08:09:19 AM UTC 24 |
| Finished | Sep 11 08:09:35 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827130006 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.827130006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2708144714 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 12060438801 ps |
| CPU time | 262.1 seconds |
| Started | Sep 11 08:09:28 AM UTC 24 |
| Finished | Sep 11 08:13:53 AM UTC 24 |
| Peak memory | 238024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2708144714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 23.lc_ctrl_stress_all.2708144714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2866227576 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 1700905880 ps |
| CPU time | 96.26 seconds |
| Started | Sep 11 08:09:29 AM UTC 24 |
| Finished | Sep 11 08:11:07 AM UTC 24 |
| Peak memory | 281376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866227576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2866227576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.564045342 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 43544101 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:09:19 AM UTC 24 |
| Finished | Sep 11 08:09:21 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564045342 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 3.lc_ctrl_volatile_unlock_smoke.564045342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/23.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.122247918 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 39610303 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:09:42 AM UTC 24 |
| Finished | Sep 11 08:09:44 AM UTC 24 |
| Peak memory | 218752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122247918 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.122247918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3335483657 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1553118267 ps |
| CPU time | 11.8 seconds |
| Started | Sep 11 08:09:34 AM UTC 24 |
| Finished | Sep 11 08:09:47 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335483657 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3335483657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.939778288 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 341168787 ps |
| CPU time | 6.03 seconds |
| Started | Sep 11 08:09:35 AM UTC 24 |
| Finished | Sep 11 08:09:42 AM UTC 24 |
| Peak memory | 229828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939778288 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.939778288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2506059164 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 191774114 ps |
| CPU time | 4.59 seconds |
| Started | Sep 11 08:09:34 AM UTC 24 |
| Finished | Sep 11 08:09:39 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506059164 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2506059164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.1858748266 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1615942732 ps |
| CPU time | 20.48 seconds |
| Started | Sep 11 08:09:36 AM UTC 24 |
| Finished | Sep 11 08:09:58 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858748266 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1858748266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1414940697 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 872789174 ps |
| CPU time | 9.17 seconds |
| Started | Sep 11 08:09:41 AM UTC 24 |
| Finished | Sep 11 08:09:51 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1414940697 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_ token_digest.1414940697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3442715201 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 513650322 ps |
| CPU time | 16.11 seconds |
| Started | Sep 11 08:09:38 AM UTC 24 |
| Finished | Sep 11 08:09:55 AM UTC 24 |
| Peak memory | 232188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442715201 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_tok en_mux.3442715201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.4101182882 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 4608542002 ps |
| CPU time | 15.1 seconds |
| Started | Sep 11 08:09:35 AM UTC 24 |
| Finished | Sep 11 08:09:51 AM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101182882 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4101182882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3069375950 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 226395863 ps |
| CPU time | 10.93 seconds |
| Started | Sep 11 08:09:31 AM UTC 24 |
| Finished | Sep 11 08:09:43 AM UTC 24 |
| Peak memory | 230112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069375950 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3069375950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2611969881 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 216644333 ps |
| CPU time | 15.47 seconds |
| Started | Sep 11 08:09:33 AM UTC 24 |
| Finished | Sep 11 08:09:49 AM UTC 24 |
| Peak memory | 262888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611969881 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2611969881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3260801895 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 172368834 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 08:09:33 AM UTC 24 |
| Finished | Sep 11 08:09:43 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260801895 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3260801895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2969816044 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 34939866 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:09:31 AM UTC 24 |
| Finished | Sep 11 08:09:34 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969816044 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_volatile_unlock_smoke.2969816044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/24.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.64591482 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 43649212 ps |
| CPU time | 1.17 seconds |
| Started | Sep 11 08:09:51 AM UTC 24 |
| Finished | Sep 11 08:09:53 AM UTC 24 |
| Peak memory | 216920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64591482 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.64591482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_errors.708644286 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 541765661 ps |
| CPU time | 23.01 seconds |
| Started | Sep 11 08:09:45 AM UTC 24 |
| Finished | Sep 11 08:10:09 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708644286 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.708644286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.1202333763 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 518999738 ps |
| CPU time | 9.11 seconds |
| Started | Sep 11 08:09:45 AM UTC 24 |
| Finished | Sep 11 08:09:55 AM UTC 24 |
| Peak memory | 229676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202333763 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_acce ss.1202333763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.1628676916 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 216374022 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 08:09:45 AM UTC 24 |
| Finished | Sep 11 08:09:49 AM UTC 24 |
| Peak memory | 230124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628676916 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1628676916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1622687878 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 231730172 ps |
| CPU time | 10.77 seconds |
| Started | Sep 11 08:09:45 AM UTC 24 |
| Finished | Sep 11 08:09:57 AM UTC 24 |
| Peak memory | 237812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1622687878 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1622687878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.2759802184 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 853889282 ps |
| CPU time | 10.45 seconds |
| Started | Sep 11 08:09:46 AM UTC 24 |
| Finished | Sep 11 08:09:58 AM UTC 24 |
| Peak memory | 236968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759802184 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_ token_digest.2759802184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1613785180 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 326211363 ps |
| CPU time | 13.85 seconds |
| Started | Sep 11 08:09:46 AM UTC 24 |
| Finished | Sep 11 08:10:01 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613785180 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_tok en_mux.1613785180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3922875540 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 776240274 ps |
| CPU time | 12.96 seconds |
| Started | Sep 11 08:09:45 AM UTC 24 |
| Finished | Sep 11 08:09:59 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922875540 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3922875540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.259731738 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 28279833 ps |
| CPU time | 1.58 seconds |
| Started | Sep 11 08:09:42 AM UTC 24 |
| Finished | Sep 11 08:09:45 AM UTC 24 |
| Peak memory | 228844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259731738 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.259731738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3053604128 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 6426011227 ps |
| CPU time | 48.75 seconds |
| Started | Sep 11 08:09:43 AM UTC 24 |
| Finished | Sep 11 08:10:34 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053604128 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3053604128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3984722133 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 545503619 ps |
| CPU time | 9.4 seconds |
| Started | Sep 11 08:09:43 AM UTC 24 |
| Finished | Sep 11 08:09:54 AM UTC 24 |
| Peak memory | 260944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3984722133 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.3984722133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3197720214 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 48738039713 ps |
| CPU time | 238.24 seconds |
| Started | Sep 11 08:09:47 AM UTC 24 |
| Finished | Sep 11 08:13:49 AM UTC 24 |
| Peak memory | 295584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3197720214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 25.lc_ctrl_stress_all.3197720214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1760835021 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 31742279 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 08:09:42 AM UTC 24 |
| Finished | Sep 11 08:09:44 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760835021 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_volatile_unlock_smoke.1760835021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/25.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2075799724 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 35453456 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:09:58 AM UTC 24 |
| Finished | Sep 11 08:10:00 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075799724 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2075799724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_errors.3529763337 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2072992209 ps |
| CPU time | 18.15 seconds |
| Started | Sep 11 08:09:53 AM UTC 24 |
| Finished | Sep 11 08:10:13 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529763337 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3529763337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3359528889 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 1605705621 ps |
| CPU time | 6.24 seconds |
| Started | Sep 11 08:09:54 AM UTC 24 |
| Finished | Sep 11 08:10:02 AM UTC 24 |
| Peak memory | 229800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359528889 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_acce ss.3359528889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1561459795 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 22142887 ps |
| CPU time | 1.76 seconds |
| Started | Sep 11 08:09:53 AM UTC 24 |
| Finished | Sep 11 08:09:56 AM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561459795 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1561459795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2433605257 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 378578103 ps |
| CPU time | 12.84 seconds |
| Started | Sep 11 08:09:56 AM UTC 24 |
| Finished | Sep 11 08:10:10 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433605257 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2433605257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.452634643 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 4255753980 ps |
| CPU time | 17.63 seconds |
| Started | Sep 11 08:09:56 AM UTC 24 |
| Finished | Sep 11 08:10:14 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452634643 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_t oken_digest.452634643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.965711451 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 183981875 ps |
| CPU time | 9.89 seconds |
| Started | Sep 11 08:09:56 AM UTC 24 |
| Finished | Sep 11 08:10:07 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965711451 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_toke n_mux.965711451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.82806288 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 744286909 ps |
| CPU time | 10.85 seconds |
| Started | Sep 11 08:09:54 AM UTC 24 |
| Finished | Sep 11 08:10:06 AM UTC 24 |
| Peak memory | 237968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82806288 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.82806288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.1516268654 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 92511428 ps |
| CPU time | 2.38 seconds |
| Started | Sep 11 08:09:51 AM UTC 24 |
| Finished | Sep 11 08:09:54 AM UTC 24 |
| Peak memory | 230064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516268654 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.1516268654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.1191796402 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 422940328 ps |
| CPU time | 32.26 seconds |
| Started | Sep 11 08:09:52 AM UTC 24 |
| Finished | Sep 11 08:10:26 AM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1191796402 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1191796402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.3355371504 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 87128514 ps |
| CPU time | 4.31 seconds |
| Started | Sep 11 08:09:53 AM UTC 24 |
| Finished | Sep 11 08:09:59 AM UTC 24 |
| Peak memory | 236532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355371504 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3355371504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4262675534 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 17328474845 ps |
| CPU time | 300.11 seconds |
| Started | Sep 11 08:09:57 AM UTC 24 |
| Finished | Sep 11 08:15:01 AM UTC 24 |
| Peak memory | 263120 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4262675534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 26.lc_ctrl_stress_all.4262675534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3352102408 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 13194699 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 08:09:52 AM UTC 24 |
| Finished | Sep 11 08:09:54 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352102408 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_volatile_unlock_smoke.3352102408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/26.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2831127939 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 69505506 ps |
| CPU time | 1.15 seconds |
| Started | Sep 11 08:10:07 AM UTC 24 |
| Finished | Sep 11 08:10:09 AM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831127939 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2831127939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2038509664 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1057954222 ps |
| CPU time | 13.13 seconds |
| Started | Sep 11 08:10:01 AM UTC 24 |
| Finished | Sep 11 08:10:15 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038509664 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2038509664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.3366281223 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 594905340 ps |
| CPU time | 19.79 seconds |
| Started | Sep 11 08:10:02 AM UTC 24 |
| Finished | Sep 11 08:10:23 AM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366281223 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_acce ss.3366281223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.2428796709 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 28209513 ps |
| CPU time | 2.65 seconds |
| Started | Sep 11 08:10:01 AM UTC 24 |
| Finished | Sep 11 08:10:04 AM UTC 24 |
| Peak memory | 232136 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428796709 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2428796709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.122463393 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 306913173 ps |
| CPU time | 15.71 seconds |
| Started | Sep 11 08:10:04 AM UTC 24 |
| Finished | Sep 11 08:10:20 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122463393 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.122463393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.4274846718 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1340224690 ps |
| CPU time | 16.51 seconds |
| Started | Sep 11 08:10:04 AM UTC 24 |
| Finished | Sep 11 08:10:21 AM UTC 24 |
| Peak memory | 232080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274846718 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_ token_digest.4274846718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.894617994 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 868328968 ps |
| CPU time | 14.49 seconds |
| Started | Sep 11 08:10:04 AM UTC 24 |
| Finished | Sep 11 08:10:19 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894617994 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_toke n_mux.894617994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.1250289346 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 5349263698 ps |
| CPU time | 17.88 seconds |
| Started | Sep 11 08:10:02 AM UTC 24 |
| Finished | Sep 11 08:10:21 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250289346 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1250289346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.3632278589 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 571099256 ps |
| CPU time | 5.07 seconds |
| Started | Sep 11 08:09:59 AM UTC 24 |
| Finished | Sep 11 08:10:05 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632278589 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3632278589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.1036322225 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 320198483 ps |
| CPU time | 23.57 seconds |
| Started | Sep 11 08:09:59 AM UTC 24 |
| Finished | Sep 11 08:10:24 AM UTC 24 |
| Peak memory | 262948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036322225 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1036322225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.313051314 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 204011938 ps |
| CPU time | 4.03 seconds |
| Started | Sep 11 08:10:00 AM UTC 24 |
| Finished | Sep 11 08:10:05 AM UTC 24 |
| Peak memory | 230132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313051314 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.313051314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_stress_all.1960672927 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 9701600554 ps |
| CPU time | 121.26 seconds |
| Started | Sep 11 08:10:06 AM UTC 24 |
| Finished | Sep 11 08:12:09 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1960672927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 27.lc_ctrl_stress_all.1960672927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.492639029 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 39420169 ps |
| CPU time | 1.05 seconds |
| Started | Sep 11 08:09:59 AM UTC 24 |
| Finished | Sep 11 08:10:01 AM UTC 24 |
| Peak memory | 218428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492639029 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2 7.lc_ctrl_volatile_unlock_smoke.492639029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/27.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.907126737 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 41079323 ps |
| CPU time | 1.51 seconds |
| Started | Sep 11 08:10:17 AM UTC 24 |
| Finished | Sep 11 08:10:19 AM UTC 24 |
| Peak memory | 218724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907126737 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.907126737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_errors.3297761288 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 819564674 ps |
| CPU time | 15.09 seconds |
| Started | Sep 11 08:10:11 AM UTC 24 |
| Finished | Sep 11 08:10:27 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297761288 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3297761288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.3158419634 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 329193396 ps |
| CPU time | 5.42 seconds |
| Started | Sep 11 08:10:12 AM UTC 24 |
| Finished | Sep 11 08:10:18 AM UTC 24 |
| Peak memory | 230164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158419634 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_acce ss.3158419634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.1288010217 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 333936283 ps |
| CPU time | 4.22 seconds |
| Started | Sep 11 08:10:11 AM UTC 24 |
| Finished | Sep 11 08:10:16 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288010217 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1288010217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.288545167 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 799177391 ps |
| CPU time | 12.81 seconds |
| Started | Sep 11 08:10:14 AM UTC 24 |
| Finished | Sep 11 08:10:28 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288545167 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.288545167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2575902763 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 190131858 ps |
| CPU time | 9.4 seconds |
| Started | Sep 11 08:10:17 AM UTC 24 |
| Finished | Sep 11 08:10:27 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575902763 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_ token_digest.2575902763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.3445801157 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 334902649 ps |
| CPU time | 17.95 seconds |
| Started | Sep 11 08:10:15 AM UTC 24 |
| Finished | Sep 11 08:10:34 AM UTC 24 |
| Peak memory | 238140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445801157 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_tok en_mux.3445801157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.3546662505 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 304342554 ps |
| CPU time | 11.58 seconds |
| Started | Sep 11 08:10:11 AM UTC 24 |
| Finished | Sep 11 08:10:23 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546662505 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3546662505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1679908025 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 39935550 ps |
| CPU time | 3.19 seconds |
| Started | Sep 11 08:10:07 AM UTC 24 |
| Finished | Sep 11 08:10:11 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679908025 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1679908025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.2332188114 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 761262240 ps |
| CPU time | 36.04 seconds |
| Started | Sep 11 08:10:09 AM UTC 24 |
| Finished | Sep 11 08:10:47 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332188114 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2332188114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.4292763341 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 1005729896 ps |
| CPU time | 7.1 seconds |
| Started | Sep 11 08:10:11 AM UTC 24 |
| Finished | Sep 11 08:10:19 AM UTC 24 |
| Peak memory | 260672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292763341 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4292763341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.2479578598 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 3312449714 ps |
| CPU time | 75.34 seconds |
| Started | Sep 11 08:10:17 AM UTC 24 |
| Finished | Sep 11 08:11:34 AM UTC 24 |
| Peak memory | 262692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2479578598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 28.lc_ctrl_stress_all.2479578598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1494945145 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1394519491 ps |
| CPU time | 60.06 seconds |
| Started | Sep 11 08:10:17 AM UTC 24 |
| Finished | Sep 11 08:11:19 AM UTC 24 |
| Peak memory | 285472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1494945145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1494945145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1791477367 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 36918549 ps |
| CPU time | 1.31 seconds |
| Started | Sep 11 08:10:07 AM UTC 24 |
| Finished | Sep 11 08:10:09 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791477367 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_volatile_unlock_smoke.1791477367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/28.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.3803388693 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 56452785 ps |
| CPU time | 1.24 seconds |
| Started | Sep 11 08:10:27 AM UTC 24 |
| Finished | Sep 11 08:10:29 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803388693 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3803388693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3557827362 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 277093586 ps |
| CPU time | 9.49 seconds |
| Started | Sep 11 08:10:22 AM UTC 24 |
| Finished | Sep 11 08:10:32 AM UTC 24 |
| Peak memory | 230140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557827362 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3557827362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.3327808972 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 3436171063 ps |
| CPU time | 16.52 seconds |
| Started | Sep 11 08:10:23 AM UTC 24 |
| Finished | Sep 11 08:10:41 AM UTC 24 |
| Peak memory | 229936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327808972 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_acce ss.3327808972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.1325818421 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 91261274 ps |
| CPU time | 5.66 seconds |
| Started | Sep 11 08:10:22 AM UTC 24 |
| Finished | Sep 11 08:10:29 AM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325818421 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1325818421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.840645483 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1884950991 ps |
| CPU time | 13.29 seconds |
| Started | Sep 11 08:10:23 AM UTC 24 |
| Finished | Sep 11 08:10:38 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840645483 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.840645483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3106299754 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1660366355 ps |
| CPU time | 10.78 seconds |
| Started | Sep 11 08:10:25 AM UTC 24 |
| Finished | Sep 11 08:10:37 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106299754 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_ token_digest.3106299754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1248438655 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 684763560 ps |
| CPU time | 8.79 seconds |
| Started | Sep 11 08:10:25 AM UTC 24 |
| Finished | Sep 11 08:10:34 AM UTC 24 |
| Peak memory | 238076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248438655 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_tok en_mux.1248438655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.3338999916 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 215203863 ps |
| CPU time | 8.72 seconds |
| Started | Sep 11 08:10:22 AM UTC 24 |
| Finished | Sep 11 08:10:32 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338999916 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3338999916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.2891975382 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 37217726 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 08:10:19 AM UTC 24 |
| Finished | Sep 11 08:10:22 AM UTC 24 |
| Peak memory | 222716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891975382 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2891975382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.649124037 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1226795336 ps |
| CPU time | 56.1 seconds |
| Started | Sep 11 08:10:20 AM UTC 24 |
| Finished | Sep 11 08:11:18 AM UTC 24 |
| Peak memory | 262728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649124037 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.649124037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.1832911298 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 100991735 ps |
| CPU time | 11.51 seconds |
| Started | Sep 11 08:10:20 AM UTC 24 |
| Finished | Sep 11 08:10:33 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832911298 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1832911298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.4124946675 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 6559856774 ps |
| CPU time | 36.25 seconds |
| Started | Sep 11 08:10:26 AM UTC 24 |
| Finished | Sep 11 08:11:04 AM UTC 24 |
| Peak memory | 238356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124946675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.4124946675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1727226875 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 12357936 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:10:19 AM UTC 24 |
| Finished | Sep 11 08:10:22 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727226875 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_volatile_unlock_smoke.1727226875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/29.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_alert_test.1408159792 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 110298729 ps |
| CPU time | 1.92 seconds |
| Started | Sep 11 08:03:47 AM UTC 24 |
| Finished | Sep 11 08:03:50 AM UTC 24 |
| Peak memory | 218628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408159792 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.1408159792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_claim_transition_if.3937200797 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 13144654 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:03:24 AM UTC 24 |
| Finished | Sep 11 08:03:26 AM UTC 24 |
| Peak memory | 217360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937200797 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3937200797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_errors.1461505587 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 791155065 ps |
| CPU time | 24.77 seconds |
| Started | Sep 11 08:03:22 AM UTC 24 |
| Finished | Sep 11 08:03:48 AM UTC 24 |
| Peak memory | 238220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461505587 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1461505587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_access.991110974 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 1990930748 ps |
| CPU time | 13.84 seconds |
| Started | Sep 11 08:03:30 AM UTC 24 |
| Finished | Sep 11 08:03:45 AM UTC 24 |
| Peak memory | 229896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991110974 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.991110974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_errors.2897230888 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 12325977759 ps |
| CPU time | 29.43 seconds |
| Started | Sep 11 08:03:30 AM UTC 24 |
| Finished | Sep 11 08:04:01 AM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897230888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ jtag_errors.2897230888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_priority.435662543 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 317126220 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 08:03:32 AM UTC 24 |
| Finished | Sep 11 08:03:37 AM UTC 24 |
| Peak memory | 229972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435662543 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_prio rity.435662543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_prog_failure.3773508573 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 1164183115 ps |
| CPU time | 21.38 seconds |
| Started | Sep 11 08:03:30 AM UTC 24 |
| Finished | Sep 11 08:03:53 AM UTC 24 |
| Peak memory | 232104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773508573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct rl_jtag_prog_failure.3773508573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1276447721 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 1610097093 ps |
| CPU time | 18.48 seconds |
| Started | Sep 11 08:03:36 AM UTC 24 |
| Finished | Sep 11 08:03:55 AM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276447721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l c_ctrl_jtag_regwen_during_op.1276447721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_smoke.3202716252 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 285145757 ps |
| CPU time | 2.34 seconds |
| Started | Sep 11 08:03:26 AM UTC 24 |
| Finished | Sep 11 08:03:29 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202716252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag _smoke.3202716252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_jtag_state_post_trans.1673260189 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 4396252898 ps |
| CPU time | 24.7 seconds |
| Started | Sep 11 08:03:27 AM UTC 24 |
| Finished | Sep 11 08:03:53 AM UTC 24 |
| Peak memory | 260952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673260189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.l c_ctrl_jtag_state_post_trans.1673260189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_prog_failure.3721799306 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 383148172 ps |
| CPU time | 2.69 seconds |
| Started | Sep 11 08:03:21 AM UTC 24 |
| Finished | Sep 11 08:03:25 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721799306 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3721799306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_cm.1656394046 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 110056804 ps |
| CPU time | 35.49 seconds |
| Started | Sep 11 08:03:47 AM UTC 24 |
| Finished | Sep 11 08:04:23 AM UTC 24 |
| Peak memory | 287792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656394046 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1656394046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_mubi.390323022 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 203580707 ps |
| CPU time | 7.97 seconds |
| Started | Sep 11 08:03:37 AM UTC 24 |
| Finished | Sep 11 08:03:46 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390323022 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.390323022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_digest.847145879 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 187944359 ps |
| CPU time | 13.58 seconds |
| Started | Sep 11 08:03:38 AM UTC 24 |
| Finished | Sep 11 08:03:53 AM UTC 24 |
| Peak memory | 238152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847145879 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_to ken_digest.847145879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_sec_token_mux.3233052808 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 1556486002 ps |
| CPU time | 14.78 seconds |
| Started | Sep 11 08:03:38 AM UTC 24 |
| Finished | Sep 11 08:03:54 AM UTC 24 |
| Peak memory | 238140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233052808 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_toke n_mux.3233052808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_security_escalation.4054533818 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 428567001 ps |
| CPU time | 7.45 seconds |
| Started | Sep 11 08:03:23 AM UTC 24 |
| Finished | Sep 11 08:03:32 AM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054533818 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4054533818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_smoke.2429226693 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 66894749 ps |
| CPU time | 2.46 seconds |
| Started | Sep 11 08:03:20 AM UTC 24 |
| Finished | Sep 11 08:03:23 AM UTC 24 |
| Peak memory | 236264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429226693 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2429226693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_failure.2120540725 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 191575986 ps |
| CPU time | 39.81 seconds |
| Started | Sep 11 08:03:20 AM UTC 24 |
| Finished | Sep 11 08:04:01 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120540725 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2120540725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_state_post_trans.1432428159 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 68631763 ps |
| CPU time | 14.56 seconds |
| Started | Sep 11 08:03:21 AM UTC 24 |
| Finished | Sep 11 08:03:37 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432428159 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1432428159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.2888117023 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 1377666439 ps |
| CPU time | 77.87 seconds |
| Started | Sep 11 08:03:39 AM UTC 24 |
| Finished | Sep 11 08:04:59 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2888117023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 3.lc_ctrl_stress_all.2888117023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/3.lc_ctrl_volatile_unlock_smoke.248061020 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 197010830 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 08:03:20 AM UTC 24 |
| Finished | Sep 11 08:03:22 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248061020 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3 .lc_ctrl_volatile_unlock_smoke.248061020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/3.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.1208426245 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 69527105 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:10:34 AM UTC 24 |
| Finished | Sep 11 08:10:37 AM UTC 24 |
| Peak memory | 218864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208426245 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1208426245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_errors.3858337685 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 743489827 ps |
| CPU time | 9.29 seconds |
| Started | Sep 11 08:10:30 AM UTC 24 |
| Finished | Sep 11 08:10:40 AM UTC 24 |
| Peak memory | 238160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858337685 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3858337685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.614703882 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 639273114 ps |
| CPU time | 11.69 seconds |
| Started | Sep 11 08:10:32 AM UTC 24 |
| Finished | Sep 11 08:10:45 AM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614703882 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.614703882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.630721866 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 64727846 ps |
| CPU time | 3.99 seconds |
| Started | Sep 11 08:10:30 AM UTC 24 |
| Finished | Sep 11 08:10:35 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630721866 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.630721866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.3624027500 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 285574524 ps |
| CPU time | 13.99 seconds |
| Started | Sep 11 08:10:32 AM UTC 24 |
| Finished | Sep 11 08:10:47 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624027500 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3624027500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.2598751757 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2617905058 ps |
| CPU time | 13.66 seconds |
| Started | Sep 11 08:10:33 AM UTC 24 |
| Finished | Sep 11 08:10:48 AM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598751757 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_ token_digest.2598751757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.1321556629 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 266800960 ps |
| CPU time | 12.36 seconds |
| Started | Sep 11 08:10:32 AM UTC 24 |
| Finished | Sep 11 08:10:45 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321556629 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_tok en_mux.1321556629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2054654894 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 198843136 ps |
| CPU time | 11.51 seconds |
| Started | Sep 11 08:10:32 AM UTC 24 |
| Finished | Sep 11 08:10:44 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054654894 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2054654894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.1623620398 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 356724591 ps |
| CPU time | 9.09 seconds |
| Started | Sep 11 08:10:27 AM UTC 24 |
| Finished | Sep 11 08:10:37 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623620398 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1623620398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.4270330124 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 988193445 ps |
| CPU time | 38.04 seconds |
| Started | Sep 11 08:10:28 AM UTC 24 |
| Finished | Sep 11 08:11:08 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270330124 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4270330124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.2086740397 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 765681787 ps |
| CPU time | 9.71 seconds |
| Started | Sep 11 08:10:30 AM UTC 24 |
| Finished | Sep 11 08:10:41 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086740397 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2086740397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2139709432 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 11121506934 ps |
| CPU time | 288.1 seconds |
| Started | Sep 11 08:10:33 AM UTC 24 |
| Finished | Sep 11 08:15:25 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2139709432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 30.lc_ctrl_stress_all.2139709432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.114346650 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 32711764486 ps |
| CPU time | 120.34 seconds |
| Started | Sep 11 08:10:33 AM UTC 24 |
| Finished | Sep 11 08:12:36 AM UTC 24 |
| Peak memory | 285452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114346650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.114346650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1033071164 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 77762638 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 08:10:28 AM UTC 24 |
| Finished | Sep 11 08:10:31 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033071164 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_volatile_unlock_smoke.1033071164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/30.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.1726896057 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 54460573 ps |
| CPU time | 1.26 seconds |
| Started | Sep 11 08:10:42 AM UTC 24 |
| Finished | Sep 11 08:10:45 AM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726896057 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1726896057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_errors.1756052070 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 552770137 ps |
| CPU time | 19.7 seconds |
| Started | Sep 11 08:10:37 AM UTC 24 |
| Finished | Sep 11 08:10:59 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756052070 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1756052070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.1260802456 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 937099188 ps |
| CPU time | 11.12 seconds |
| Started | Sep 11 08:10:39 AM UTC 24 |
| Finished | Sep 11 08:10:51 AM UTC 24 |
| Peak memory | 229404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260802456 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_acce ss.1260802456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.209590947 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 60013610 ps |
| CPU time | 2.32 seconds |
| Started | Sep 11 08:10:36 AM UTC 24 |
| Finished | Sep 11 08:10:39 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209590947 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.209590947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.3210225184 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1573334680 ps |
| CPU time | 19.27 seconds |
| Started | Sep 11 08:10:39 AM UTC 24 |
| Finished | Sep 11 08:10:59 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210225184 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3210225184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.1837835107 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 614629600 ps |
| CPU time | 12.32 seconds |
| Started | Sep 11 08:10:40 AM UTC 24 |
| Finished | Sep 11 08:10:53 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837835107 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_ token_digest.1837835107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.4055357944 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 903402353 ps |
| CPU time | 17.18 seconds |
| Started | Sep 11 08:10:40 AM UTC 24 |
| Finished | Sep 11 08:10:58 AM UTC 24 |
| Peak memory | 237876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055357944 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_tok en_mux.4055357944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.1128390085 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 251947228 ps |
| CPU time | 10.46 seconds |
| Started | Sep 11 08:10:37 AM UTC 24 |
| Finished | Sep 11 08:10:49 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128390085 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1128390085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.2725486241 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 137202014 ps |
| CPU time | 3.51 seconds |
| Started | Sep 11 08:10:35 AM UTC 24 |
| Finished | Sep 11 08:10:39 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725486241 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2725486241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.43827687 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 643816480 ps |
| CPU time | 53.97 seconds |
| Started | Sep 11 08:10:36 AM UTC 24 |
| Finished | Sep 11 08:11:32 AM UTC 24 |
| Peak memory | 262964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43827687 -assert nopostproc +UVM_TESTNAME=lc_ct rl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.43827687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1870967215 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 54756720 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 08:10:36 AM UTC 24 |
| Finished | Sep 11 08:10:42 AM UTC 24 |
| Peak memory | 234492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870967215 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1870967215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.4249991004 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 91294274400 ps |
| CPU time | 568.73 seconds |
| Started | Sep 11 08:10:41 AM UTC 24 |
| Finished | Sep 11 08:20:17 AM UTC 24 |
| Peak memory | 295980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4249991004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 31.lc_ctrl_stress_all.4249991004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2545761503 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 46600451 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:10:36 AM UTC 24 |
| Finished | Sep 11 08:10:38 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545761503 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_volatile_unlock_smoke.2545761503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/31.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.768631648 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 32857805 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 08:10:52 AM UTC 24 |
| Finished | Sep 11 08:10:54 AM UTC 24 |
| Peak memory | 219108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768631648 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.768631648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_errors.830940586 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 988720620 ps |
| CPU time | 16.41 seconds |
| Started | Sep 11 08:10:47 AM UTC 24 |
| Finished | Sep 11 08:11:04 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830940586 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.830940586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2091924467 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 307983272 ps |
| CPU time | 2.02 seconds |
| Started | Sep 11 08:10:48 AM UTC 24 |
| Finished | Sep 11 08:10:51 AM UTC 24 |
| Peak memory | 230004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091924467 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_acce ss.2091924467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.1439817538 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 18410144 ps |
| CPU time | 2.04 seconds |
| Started | Sep 11 08:10:45 AM UTC 24 |
| Finished | Sep 11 08:10:49 AM UTC 24 |
| Peak memory | 232316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439817538 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1439817538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.3017552366 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 2541179649 ps |
| CPU time | 12.49 seconds |
| Started | Sep 11 08:10:48 AM UTC 24 |
| Finished | Sep 11 08:11:02 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017552366 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3017552366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.2606176767 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 633091025 ps |
| CPU time | 12.86 seconds |
| Started | Sep 11 08:10:49 AM UTC 24 |
| Finished | Sep 11 08:11:03 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606176767 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_ token_digest.2606176767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.2304926499 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 576732958 ps |
| CPU time | 15.59 seconds |
| Started | Sep 11 08:10:49 AM UTC 24 |
| Finished | Sep 11 08:11:06 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304926499 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_tok en_mux.2304926499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3461529366 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 299958412 ps |
| CPU time | 11.03 seconds |
| Started | Sep 11 08:10:47 AM UTC 24 |
| Finished | Sep 11 08:10:59 AM UTC 24 |
| Peak memory | 237224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461529366 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3461529366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.1418655435 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 56045128 ps |
| CPU time | 4.3 seconds |
| Started | Sep 11 08:10:42 AM UTC 24 |
| Finished | Sep 11 08:10:48 AM UTC 24 |
| Peak memory | 235980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418655435 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1418655435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.3669982804 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 224489331 ps |
| CPU time | 33.06 seconds |
| Started | Sep 11 08:10:45 AM UTC 24 |
| Finished | Sep 11 08:11:20 AM UTC 24 |
| Peak memory | 260688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669982804 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3669982804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.3951640341 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 866515593 ps |
| CPU time | 4.78 seconds |
| Started | Sep 11 08:10:45 AM UTC 24 |
| Finished | Sep 11 08:10:52 AM UTC 24 |
| Peak memory | 234484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951640341 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3951640341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.996084568 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 46159908477 ps |
| CPU time | 221.84 seconds |
| Started | Sep 11 08:10:50 AM UTC 24 |
| Finished | Sep 11 08:14:35 AM UTC 24 |
| Peak memory | 234360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=996084568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 32.lc_ctrl_stress_all.996084568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2018953282 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4649858035 ps |
| CPU time | 121.39 seconds |
| Started | Sep 11 08:10:50 AM UTC 24 |
| Finished | Sep 11 08:12:54 AM UTC 24 |
| Peak memory | 281364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018953282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2018953282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2420568417 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 11689699 ps |
| CPU time | 1.43 seconds |
| Started | Sep 11 08:10:43 AM UTC 24 |
| Finished | Sep 11 08:10:46 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420568417 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_volatile_unlock_smoke.2420568417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/32.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.273036793 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 22587415 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:11:02 AM UTC 24 |
| Finished | Sep 11 08:11:05 AM UTC 24 |
| Peak memory | 219168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=273036793 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.273036793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_errors.2125134855 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 961336324 ps |
| CPU time | 12.9 seconds |
| Started | Sep 11 08:10:55 AM UTC 24 |
| Finished | Sep 11 08:11:09 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125134855 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2125134855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.3783075009 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 617752641 ps |
| CPU time | 7.95 seconds |
| Started | Sep 11 08:10:55 AM UTC 24 |
| Finished | Sep 11 08:11:05 AM UTC 24 |
| Peak memory | 229332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783075009 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_acce ss.3783075009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.2279945230 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 197122533 ps |
| CPU time | 3.97 seconds |
| Started | Sep 11 08:10:54 AM UTC 24 |
| Finished | Sep 11 08:10:59 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279945230 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2279945230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.2764634131 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1500167413 ps |
| CPU time | 13.57 seconds |
| Started | Sep 11 08:10:59 AM UTC 24 |
| Finished | Sep 11 08:11:13 AM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764634131 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2764634131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.4152449718 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3011070967 ps |
| CPU time | 10.88 seconds |
| Started | Sep 11 08:11:00 AM UTC 24 |
| Finished | Sep 11 08:11:12 AM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152449718 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_ token_digest.4152449718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.3162057278 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 214081662 ps |
| CPU time | 10.11 seconds |
| Started | Sep 11 08:11:00 AM UTC 24 |
| Finished | Sep 11 08:11:11 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162057278 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_tok en_mux.3162057278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.1969390594 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 711848652 ps |
| CPU time | 11.35 seconds |
| Started | Sep 11 08:10:55 AM UTC 24 |
| Finished | Sep 11 08:11:08 AM UTC 24 |
| Peak memory | 236980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969390594 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1969390594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.2070103143 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 11228024 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 08:10:52 AM UTC 24 |
| Finished | Sep 11 08:10:54 AM UTC 24 |
| Peak memory | 219312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070103143 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2070103143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.615105694 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 687530856 ps |
| CPU time | 36.15 seconds |
| Started | Sep 11 08:10:53 AM UTC 24 |
| Finished | Sep 11 08:11:31 AM UTC 24 |
| Peak memory | 262612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615105694 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.615105694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.2000046425 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 66867398 ps |
| CPU time | 10.65 seconds |
| Started | Sep 11 08:10:53 AM UTC 24 |
| Finished | Sep 11 08:11:05 AM UTC 24 |
| Peak memory | 262564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000046425 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2000046425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3197925714 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 33382634867 ps |
| CPU time | 205.23 seconds |
| Started | Sep 11 08:11:00 AM UTC 24 |
| Finished | Sep 11 08:14:28 AM UTC 24 |
| Peak memory | 295564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3197925714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 33.lc_ctrl_stress_all.3197925714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3611302701 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 11569375 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:10:52 AM UTC 24 |
| Finished | Sep 11 08:10:54 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611302701 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_volatile_unlock_smoke.3611302701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/33.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2091958578 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 18658606 ps |
| CPU time | 1.29 seconds |
| Started | Sep 11 08:11:10 AM UTC 24 |
| Finished | Sep 11 08:11:12 AM UTC 24 |
| Peak memory | 219164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2091958578 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2091958578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3306632392 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 279929043 ps |
| CPU time | 14.3 seconds |
| Started | Sep 11 08:11:06 AM UTC 24 |
| Finished | Sep 11 08:11:21 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306632392 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.3306632392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.663582945 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 234221286 ps |
| CPU time | 5.42 seconds |
| Started | Sep 11 08:11:07 AM UTC 24 |
| Finished | Sep 11 08:11:14 AM UTC 24 |
| Peak memory | 229196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663582945 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.663582945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.3012278854 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 363489917 ps |
| CPU time | 4.57 seconds |
| Started | Sep 11 08:11:06 AM UTC 24 |
| Finished | Sep 11 08:11:11 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3012278854 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.3012278854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.3679683640 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 1230082679 ps |
| CPU time | 10.39 seconds |
| Started | Sep 11 08:11:09 AM UTC 24 |
| Finished | Sep 11 08:11:20 AM UTC 24 |
| Peak memory | 232332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679683640 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3679683640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.3549060890 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 327150745 ps |
| CPU time | 15.33 seconds |
| Started | Sep 11 08:11:09 AM UTC 24 |
| Finished | Sep 11 08:11:25 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549060890 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_ token_digest.3549060890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.4233594705 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 396378046 ps |
| CPU time | 11.74 seconds |
| Started | Sep 11 08:11:09 AM UTC 24 |
| Finished | Sep 11 08:11:22 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233594705 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_tok en_mux.4233594705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.312394154 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 733206442 ps |
| CPU time | 13.98 seconds |
| Started | Sep 11 08:11:07 AM UTC 24 |
| Finished | Sep 11 08:11:22 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312394154 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.312394154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.2204713021 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 65557552 ps |
| CPU time | 3.53 seconds |
| Started | Sep 11 08:11:04 AM UTC 24 |
| Finished | Sep 11 08:11:08 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204713021 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2204713021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.1656387977 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 325235087 ps |
| CPU time | 39.34 seconds |
| Started | Sep 11 08:11:05 AM UTC 24 |
| Finished | Sep 11 08:11:46 AM UTC 24 |
| Peak memory | 262744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656387977 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1656387977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.3077207060 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 188184434 ps |
| CPU time | 4.41 seconds |
| Started | Sep 11 08:11:06 AM UTC 24 |
| Finished | Sep 11 08:11:11 AM UTC 24 |
| Peak memory | 234756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077207060 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3077207060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1313480399 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 4418086147 ps |
| CPU time | 165.73 seconds |
| Started | Sep 11 08:11:09 AM UTC 24 |
| Finished | Sep 11 08:13:57 AM UTC 24 |
| Peak memory | 293524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1313480399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 34.lc_ctrl_stress_all.1313480399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1248404205 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 38140450 ps |
| CPU time | 1.4 seconds |
| Started | Sep 11 08:11:05 AM UTC 24 |
| Finished | Sep 11 08:11:07 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248404205 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_volatile_unlock_smoke.1248404205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/34.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.1351273710 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 69757441 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 08:11:20 AM UTC 24 |
| Finished | Sep 11 08:11:22 AM UTC 24 |
| Peak memory | 217224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351273710 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1351273710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_errors.2119095513 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 320750555 ps |
| CPU time | 16.18 seconds |
| Started | Sep 11 08:11:14 AM UTC 24 |
| Finished | Sep 11 08:11:31 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119095513 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2119095513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1817964489 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 132021939 ps |
| CPU time | 2.55 seconds |
| Started | Sep 11 08:11:15 AM UTC 24 |
| Finished | Sep 11 08:11:19 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817964489 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_acce ss.1817964489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.1639280616 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 288451433 ps |
| CPU time | 3.73 seconds |
| Started | Sep 11 08:11:14 AM UTC 24 |
| Finished | Sep 11 08:11:19 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639280616 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1639280616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.2270643365 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 1530831205 ps |
| CPU time | 13.56 seconds |
| Started | Sep 11 08:11:16 AM UTC 24 |
| Finished | Sep 11 08:11:31 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270643365 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2270643365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.3942997600 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2505085958 ps |
| CPU time | 14.65 seconds |
| Started | Sep 11 08:11:18 AM UTC 24 |
| Finished | Sep 11 08:11:33 AM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942997600 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_ token_digest.3942997600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.361659852 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 849385577 ps |
| CPU time | 8.33 seconds |
| Started | Sep 11 08:11:17 AM UTC 24 |
| Finished | Sep 11 08:11:27 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361659852 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_toke n_mux.361659852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.2047219251 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 451028785 ps |
| CPU time | 13.7 seconds |
| Started | Sep 11 08:11:15 AM UTC 24 |
| Finished | Sep 11 08:11:30 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047219251 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2047219251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.3712611074 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 167006830 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 08:11:12 AM UTC 24 |
| Finished | Sep 11 08:11:17 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712611074 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3712611074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.3844515055 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 309050645 ps |
| CPU time | 34.81 seconds |
| Started | Sep 11 08:11:13 AM UTC 24 |
| Finished | Sep 11 08:11:49 AM UTC 24 |
| Peak memory | 262752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844515055 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3844515055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.1904964327 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 77446465 ps |
| CPU time | 9.74 seconds |
| Started | Sep 11 08:11:13 AM UTC 24 |
| Finished | Sep 11 08:11:23 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904964327 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1904964327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all.2013439177 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 5305858855 ps |
| CPU time | 43.1 seconds |
| Started | Sep 11 08:11:19 AM UTC 24 |
| Finished | Sep 11 08:12:03 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2013439177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 35.lc_ctrl_stress_all.2013439177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2325355324 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 24400739 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:11:12 AM UTC 24 |
| Finished | Sep 11 08:11:15 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325355324 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_volatile_unlock_smoke.2325355324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/35.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.796916392 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 55668802 ps |
| CPU time | 1.57 seconds |
| Started | Sep 11 08:11:29 AM UTC 24 |
| Finished | Sep 11 08:11:32 AM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796916392 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.796916392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_errors.3759686245 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 4730362869 ps |
| CPU time | 18.59 seconds |
| Started | Sep 11 08:11:23 AM UTC 24 |
| Finished | Sep 11 08:11:43 AM UTC 24 |
| Peak memory | 232504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3759686245 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3759686245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2795624509 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 1579617656 ps |
| CPU time | 15.52 seconds |
| Started | Sep 11 08:11:24 AM UTC 24 |
| Finished | Sep 11 08:11:41 AM UTC 24 |
| Peak memory | 229228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795624509 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_acce ss.2795624509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.2105164142 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 135024611 ps |
| CPU time | 3.14 seconds |
| Started | Sep 11 08:11:23 AM UTC 24 |
| Finished | Sep 11 08:11:27 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105164142 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2105164142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.1016912669 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 1539511892 ps |
| CPU time | 13.96 seconds |
| Started | Sep 11 08:11:24 AM UTC 24 |
| Finished | Sep 11 08:11:39 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016912669 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1016912669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.4080871662 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 449425509 ps |
| CPU time | 15.1 seconds |
| Started | Sep 11 08:11:27 AM UTC 24 |
| Finished | Sep 11 08:11:43 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080871662 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_ token_digest.4080871662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.1145393740 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 715089640 ps |
| CPU time | 12.59 seconds |
| Started | Sep 11 08:11:27 AM UTC 24 |
| Finished | Sep 11 08:11:40 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145393740 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_tok en_mux.1145393740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.2663971872 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 358860353 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 08:11:24 AM UTC 24 |
| Finished | Sep 11 08:11:35 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663971872 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2663971872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.1949483312 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 274577592 ps |
| CPU time | 7 seconds |
| Started | Sep 11 08:11:20 AM UTC 24 |
| Finished | Sep 11 08:11:28 AM UTC 24 |
| Peak memory | 229840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949483312 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1949483312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3037746646 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 419255636 ps |
| CPU time | 35.72 seconds |
| Started | Sep 11 08:11:21 AM UTC 24 |
| Finished | Sep 11 08:11:58 AM UTC 24 |
| Peak memory | 260960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037746646 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3037746646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.727538608 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 188076736 ps |
| CPU time | 8.12 seconds |
| Started | Sep 11 08:11:23 AM UTC 24 |
| Finished | Sep 11 08:11:32 AM UTC 24 |
| Peak memory | 238432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727538608 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.727538608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.2358138381 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 6961590274 ps |
| CPU time | 248.42 seconds |
| Started | Sep 11 08:11:28 AM UTC 24 |
| Finished | Sep 11 08:15:40 AM UTC 24 |
| Peak memory | 295652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2358138381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 36.lc_ctrl_stress_all.2358138381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1594620573 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 7170947414 ps |
| CPU time | 143.44 seconds |
| Started | Sep 11 08:11:28 AM UTC 24 |
| Finished | Sep 11 08:13:54 AM UTC 24 |
| Peak memory | 295700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594620573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1594620573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1022233353 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 29104017 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:11:21 AM UTC 24 |
| Finished | Sep 11 08:11:24 AM UTC 24 |
| Peak memory | 222896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022233353 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_volatile_unlock_smoke.1022233353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/36.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.3669219107 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 24635493 ps |
| CPU time | 1.28 seconds |
| Started | Sep 11 08:11:40 AM UTC 24 |
| Finished | Sep 11 08:11:42 AM UTC 24 |
| Peak memory | 218888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669219107 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3669219107 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_errors.851065343 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 574001915 ps |
| CPU time | 9.2 seconds |
| Started | Sep 11 08:11:33 AM UTC 24 |
| Finished | Sep 11 08:11:43 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851065343 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.851065343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.4283448795 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 1340630340 ps |
| CPU time | 18.71 seconds |
| Started | Sep 11 08:11:34 AM UTC 24 |
| Finished | Sep 11 08:11:54 AM UTC 24 |
| Peak memory | 229624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283448795 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_acce ss.4283448795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.2097862910 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 138756309 ps |
| CPU time | 3.5 seconds |
| Started | Sep 11 08:11:33 AM UTC 24 |
| Finished | Sep 11 08:11:37 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097862910 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2097862910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.3384485794 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 3636192792 ps |
| CPU time | 29.46 seconds |
| Started | Sep 11 08:11:35 AM UTC 24 |
| Finished | Sep 11 08:12:06 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384485794 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.3384485794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3754035558 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 1042936428 ps |
| CPU time | 15.44 seconds |
| Started | Sep 11 08:11:36 AM UTC 24 |
| Finished | Sep 11 08:11:52 AM UTC 24 |
| Peak memory | 238208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754035558 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_ token_digest.3754035558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.1348352202 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 272598680 ps |
| CPU time | 11.83 seconds |
| Started | Sep 11 08:11:35 AM UTC 24 |
| Finished | Sep 11 08:11:48 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348352202 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_tok en_mux.1348352202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.2733978706 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 266309872 ps |
| CPU time | 13.74 seconds |
| Started | Sep 11 08:11:33 AM UTC 24 |
| Finished | Sep 11 08:11:48 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733978706 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.2733978706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.2116649948 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 128950988 ps |
| CPU time | 3.64 seconds |
| Started | Sep 11 08:11:30 AM UTC 24 |
| Finished | Sep 11 08:11:35 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116649948 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2116649948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.755702699 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 618043612 ps |
| CPU time | 33.34 seconds |
| Started | Sep 11 08:11:32 AM UTC 24 |
| Finished | Sep 11 08:12:06 AM UTC 24 |
| Peak memory | 263064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755702699 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.755702699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1857389489 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 705518336 ps |
| CPU time | 15.33 seconds |
| Started | Sep 11 08:11:32 AM UTC 24 |
| Finished | Sep 11 08:11:48 AM UTC 24 |
| Peak memory | 260596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857389489 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1857389489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.760231510 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 20225233576 ps |
| CPU time | 146.89 seconds |
| Started | Sep 11 08:11:36 AM UTC 24 |
| Finished | Sep 11 08:14:05 AM UTC 24 |
| Peak memory | 285324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=760231510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 37.lc_ctrl_stress_all.760231510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.570829690 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 12104488432 ps |
| CPU time | 86.15 seconds |
| Started | Sep 11 08:11:39 AM UTC 24 |
| Finished | Sep 11 08:13:07 AM UTC 24 |
| Peak memory | 273308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570829690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.570829690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2770102854 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 55969984 ps |
| CPU time | 1.41 seconds |
| Started | Sep 11 08:11:32 AM UTC 24 |
| Finished | Sep 11 08:11:34 AM UTC 24 |
| Peak memory | 228844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770102854 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_volatile_unlock_smoke.2770102854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/37.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3201016421 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 19514555 ps |
| CPU time | 1.73 seconds |
| Started | Sep 11 08:11:50 AM UTC 24 |
| Finished | Sep 11 08:11:53 AM UTC 24 |
| Peak memory | 218864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201016421 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3201016421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_errors.3002598761 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 256658015 ps |
| CPU time | 9.79 seconds |
| Started | Sep 11 08:11:45 AM UTC 24 |
| Finished | Sep 11 08:11:56 AM UTC 24 |
| Peak memory | 237968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3002598761 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3002598761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.1828774974 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 833957544 ps |
| CPU time | 11.77 seconds |
| Started | Sep 11 08:11:45 AM UTC 24 |
| Finished | Sep 11 08:11:58 AM UTC 24 |
| Peak memory | 229236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828774974 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_acce ss.1828774974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.3509747103 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 49119734 ps |
| CPU time | 3.11 seconds |
| Started | Sep 11 08:11:45 AM UTC 24 |
| Finished | Sep 11 08:11:49 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509747103 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3509747103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.737443411 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 848769804 ps |
| CPU time | 18.24 seconds |
| Started | Sep 11 08:11:47 AM UTC 24 |
| Finished | Sep 11 08:12:06 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737443411 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.737443411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.3968268609 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 328816795 ps |
| CPU time | 16.93 seconds |
| Started | Sep 11 08:11:50 AM UTC 24 |
| Finished | Sep 11 08:12:08 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968268609 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_ token_digest.3968268609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.2344657966 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 377563712 ps |
| CPU time | 16.06 seconds |
| Started | Sep 11 08:11:48 AM UTC 24 |
| Finished | Sep 11 08:12:06 AM UTC 24 |
| Peak memory | 237948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344657966 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_tok en_mux.2344657966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.103225096 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 915547853 ps |
| CPU time | 13.59 seconds |
| Started | Sep 11 08:11:45 AM UTC 24 |
| Finished | Sep 11 08:11:59 AM UTC 24 |
| Peak memory | 232520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103225096 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.103225096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.1676182994 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 131584347 ps |
| CPU time | 2.1 seconds |
| Started | Sep 11 08:11:41 AM UTC 24 |
| Finished | Sep 11 08:11:44 AM UTC 24 |
| Peak memory | 225744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676182994 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1676182994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.280794297 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 1225238570 ps |
| CPU time | 41.05 seconds |
| Started | Sep 11 08:11:43 AM UTC 24 |
| Finished | Sep 11 08:12:26 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280794297 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.280794297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.2697437958 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 63342612 ps |
| CPU time | 13.69 seconds |
| Started | Sep 11 08:11:43 AM UTC 24 |
| Finished | Sep 11 08:11:58 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697437958 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2697437958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all.1998521398 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 5721128173 ps |
| CPU time | 45.81 seconds |
| Started | Sep 11 08:11:50 AM UTC 24 |
| Finished | Sep 11 08:12:37 AM UTC 24 |
| Peak memory | 237524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1998521398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 38.lc_ctrl_stress_all.1998521398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1446710670 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 13258729 ps |
| CPU time | 1.12 seconds |
| Started | Sep 11 08:11:42 AM UTC 24 |
| Finished | Sep 11 08:11:44 AM UTC 24 |
| Peak memory | 218484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446710670 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_volatile_unlock_smoke.1446710670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/38.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1119560025 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 23100506 ps |
| CPU time | 1.37 seconds |
| Started | Sep 11 08:12:04 AM UTC 24 |
| Finished | Sep 11 08:12:06 AM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119560025 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1119560025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_errors.3412311978 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 1447190011 ps |
| CPU time | 25.62 seconds |
| Started | Sep 11 08:11:57 AM UTC 24 |
| Finished | Sep 11 08:12:23 AM UTC 24 |
| Peak memory | 230332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412311978 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3412311978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.1344831881 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2318522140 ps |
| CPU time | 16.14 seconds |
| Started | Sep 11 08:11:59 AM UTC 24 |
| Finished | Sep 11 08:12:16 AM UTC 24 |
| Peak memory | 229940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344831881 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_acce ss.1344831881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.1328043482 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 243868770 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 08:11:55 AM UTC 24 |
| Finished | Sep 11 08:12:01 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328043482 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1328043482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.1756551939 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 1282518265 ps |
| CPU time | 19.75 seconds |
| Started | Sep 11 08:11:59 AM UTC 24 |
| Finished | Sep 11 08:12:20 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756551939 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1756551939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.3418437975 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 2183813087 ps |
| CPU time | 12.5 seconds |
| Started | Sep 11 08:12:00 AM UTC 24 |
| Finished | Sep 11 08:12:14 AM UTC 24 |
| Peak memory | 237948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418437975 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_ token_digest.3418437975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.1740539882 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 397564491 ps |
| CPU time | 19.64 seconds |
| Started | Sep 11 08:12:00 AM UTC 24 |
| Finished | Sep 11 08:12:21 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740539882 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_tok en_mux.1740539882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3126646887 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 30287253 ps |
| CPU time | 2.82 seconds |
| Started | Sep 11 08:11:50 AM UTC 24 |
| Finished | Sep 11 08:11:54 AM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126646887 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3126646887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.472985408 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 215626806 ps |
| CPU time | 25.66 seconds |
| Started | Sep 11 08:11:53 AM UTC 24 |
| Finished | Sep 11 08:12:20 AM UTC 24 |
| Peak memory | 262728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472985408 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.472985408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.1754077537 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 87637897 ps |
| CPU time | 12.13 seconds |
| Started | Sep 11 08:11:54 AM UTC 24 |
| Finished | Sep 11 08:12:07 AM UTC 24 |
| Peak memory | 262652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754077537 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1754077537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2584750909 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 5262357499 ps |
| CPU time | 157.88 seconds |
| Started | Sep 11 08:12:02 AM UTC 24 |
| Finished | Sep 11 08:14:43 AM UTC 24 |
| Peak memory | 273040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2584750909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 39.lc_ctrl_stress_all.2584750909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.3671371327 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2603027815 ps |
| CPU time | 70.85 seconds |
| Started | Sep 11 08:12:04 AM UTC 24 |
| Finished | Sep 11 08:13:16 AM UTC 24 |
| Peak memory | 289632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671371327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.3671371327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1392031821 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 35320779 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:11:53 AM UTC 24 |
| Finished | Sep 11 08:11:56 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392031821 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_volatile_unlock_smoke.1392031821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/39.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_alert_test.988000187 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 34333724 ps |
| CPU time | 2.28 seconds |
| Started | Sep 11 08:04:11 AM UTC 24 |
| Finished | Sep 11 08:04:14 AM UTC 24 |
| Peak memory | 219132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988000187 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.988000187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_claim_transition_if.2516628070 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 49214174 ps |
| CPU time | 1.19 seconds |
| Started | Sep 11 08:03:54 AM UTC 24 |
| Finished | Sep 11 08:03:56 AM UTC 24 |
| Peak memory | 219072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516628070 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2516628070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_errors.176792135 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 5003260362 ps |
| CPU time | 20.13 seconds |
| Started | Sep 11 08:03:54 AM UTC 24 |
| Finished | Sep 11 08:04:15 AM UTC 24 |
| Peak memory | 231972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176792135 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.176792135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_access.910983478 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 273499334 ps |
| CPU time | 1.94 seconds |
| Started | Sep 11 08:04:00 AM UTC 24 |
| Finished | Sep 11 08:04:03 AM UTC 24 |
| Peak memory | 229672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910983478 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.910983478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_errors.3292316371 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 3288413067 ps |
| CPU time | 39.41 seconds |
| Started | Sep 11 08:04:00 AM UTC 24 |
| Finished | Sep 11 08:04:40 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292316371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_ jtag_errors.3292316371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_priority.131393901 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 1834835342 ps |
| CPU time | 7.82 seconds |
| Started | Sep 11 08:04:01 AM UTC 24 |
| Finished | Sep 11 08:04:10 AM UTC 24 |
| Peak memory | 229976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131393901 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_prio rity.131393901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_prog_failure.2812312665 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 918249818 ps |
| CPU time | 5.8 seconds |
| Started | Sep 11 08:03:57 AM UTC 24 |
| Finished | Sep 11 08:04:04 AM UTC 24 |
| Peak memory | 232100 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812312665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct rl_jtag_prog_failure.2812312665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1905342057 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 895335189 ps |
| CPU time | 15.22 seconds |
| Started | Sep 11 08:04:02 AM UTC 24 |
| Finished | Sep 11 08:04:18 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905342057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.l c_ctrl_jtag_regwen_during_op.1905342057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_smoke.4018438119 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 920238182 ps |
| CPU time | 3.49 seconds |
| Started | Sep 11 08:03:55 AM UTC 24 |
| Finished | Sep 11 08:03:59 AM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018438119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag _smoke.4018438119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_failure.1005004425 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6865768701 ps |
| CPU time | 78.6 seconds |
| Started | Sep 11 08:03:56 AM UTC 24 |
| Finished | Sep 11 08:05:17 AM UTC 24 |
| Peak memory | 262872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005004425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_c trl_jtag_state_failure.1005004425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_jtag_state_post_trans.1308875347 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 972621198 ps |
| CPU time | 19.43 seconds |
| Started | Sep 11 08:03:56 AM UTC 24 |
| Finished | Sep 11 08:04:17 AM UTC 24 |
| Peak memory | 262668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308875347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.l c_ctrl_jtag_state_post_trans.1308875347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_prog_failure.841374181 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 99558639 ps |
| CPU time | 4.49 seconds |
| Started | Sep 11 08:03:54 AM UTC 24 |
| Finished | Sep 11 08:03:59 AM UTC 24 |
| Peak memory | 236524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841374181 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.841374181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_regwen_during_op.2705894734 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 377161070 ps |
| CPU time | 14.7 seconds |
| Started | Sep 11 08:03:54 AM UTC 24 |
| Finished | Sep 11 08:04:10 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705894734 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2705894734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_cm.3710376451 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 370765759 ps |
| CPU time | 37.76 seconds |
| Started | Sep 11 08:04:10 AM UTC 24 |
| Finished | Sep 11 08:04:49 AM UTC 24 |
| Peak memory | 296028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710376451 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3710376451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_mubi.789872784 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 1322317548 ps |
| CPU time | 12.11 seconds |
| Started | Sep 11 08:04:02 AM UTC 24 |
| Finished | Sep 11 08:04:15 AM UTC 24 |
| Peak memory | 238164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789872784 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.789872784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_digest.1136533099 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 615678477 ps |
| CPU time | 9.97 seconds |
| Started | Sep 11 08:04:03 AM UTC 24 |
| Finished | Sep 11 08:04:14 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136533099 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_t oken_digest.1136533099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_sec_token_mux.63449355 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 879205924 ps |
| CPU time | 14.09 seconds |
| Started | Sep 11 08:04:02 AM UTC 24 |
| Finished | Sep 11 08:04:17 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63449355 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.63449355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_security_escalation.3913995899 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1027379684 ps |
| CPU time | 13.88 seconds |
| Started | Sep 11 08:03:54 AM UTC 24 |
| Finished | Sep 11 08:04:09 AM UTC 24 |
| Peak memory | 231932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913995899 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3913995899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_smoke.2694415304 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 51900531 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 08:03:49 AM UTC 24 |
| Finished | Sep 11 08:03:51 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694415304 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2694415304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_failure.1802879872 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 748007649 ps |
| CPU time | 41.26 seconds |
| Started | Sep 11 08:03:52 AM UTC 24 |
| Finished | Sep 11 08:04:35 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802879872 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1802879872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_state_post_trans.1032976071 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 85591240 ps |
| CPU time | 5.59 seconds |
| Started | Sep 11 08:03:52 AM UTC 24 |
| Finished | Sep 11 08:03:59 AM UTC 24 |
| Peak memory | 234488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032976071 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1032976071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.3356756377 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 4385304308 ps |
| CPU time | 134.03 seconds |
| Started | Sep 11 08:04:05 AM UTC 24 |
| Finished | Sep 11 08:06:22 AM UTC 24 |
| Peak memory | 262940 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3356756377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 4.lc_ctrl_stress_all.3356756377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3959237692 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 91844010 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 08:03:50 AM UTC 24 |
| Finished | Sep 11 08:03:52 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959237692 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_volatile_unlock_smoke.3959237692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/4.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2660482251 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 358607404 ps |
| CPU time | 1.56 seconds |
| Started | Sep 11 08:12:12 AM UTC 24 |
| Finished | Sep 11 08:12:14 AM UTC 24 |
| Peak memory | 218700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660482251 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2660482251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_errors.933319510 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 312354498 ps |
| CPU time | 20.74 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:30 AM UTC 24 |
| Peak memory | 232496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933319510 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.933319510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.2111614086 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 4275194630 ps |
| CPU time | 10.43 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:20 AM UTC 24 |
| Peak memory | 230028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111614086 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_acce ss.2111614086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.1700446462 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 105794626 ps |
| CPU time | 2.51 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:12 AM UTC 24 |
| Peak memory | 234372 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700446462 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1700446462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.2472553538 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1761917202 ps |
| CPU time | 21.23 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:31 AM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472553538 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2472553538 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.301436173 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 980897153 ps |
| CPU time | 17.9 seconds |
| Started | Sep 11 08:12:10 AM UTC 24 |
| Finished | Sep 11 08:12:29 AM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301436173 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_t oken_digest.301436173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.2690165632 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 289218276 ps |
| CPU time | 9.34 seconds |
| Started | Sep 11 08:12:09 AM UTC 24 |
| Finished | Sep 11 08:12:20 AM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690165632 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_tok en_mux.2690165632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.3762851967 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 488634484 ps |
| CPU time | 17.57 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:27 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762851967 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3762851967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.822998563 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 182678616 ps |
| CPU time | 3.57 seconds |
| Started | Sep 11 08:12:06 AM UTC 24 |
| Finished | Sep 11 08:12:11 AM UTC 24 |
| Peak memory | 229644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822998563 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.822998563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.2104348748 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 623441931 ps |
| CPU time | 46.53 seconds |
| Started | Sep 11 08:12:06 AM UTC 24 |
| Finished | Sep 11 08:12:54 AM UTC 24 |
| Peak memory | 263064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104348748 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2104348748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.4003689786 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 76678653 ps |
| CPU time | 16.71 seconds |
| Started | Sep 11 08:12:08 AM UTC 24 |
| Finished | Sep 11 08:12:26 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003689786 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4003689786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1104106624 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 3717080546 ps |
| CPU time | 76.68 seconds |
| Started | Sep 11 08:12:11 AM UTC 24 |
| Finished | Sep 11 08:13:29 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1104106624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 40.lc_ctrl_stress_all.1104106624 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3349022631 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 10031681 ps |
| CPU time | 1.08 seconds |
| Started | Sep 11 08:12:06 AM UTC 24 |
| Finished | Sep 11 08:12:08 AM UTC 24 |
| Peak memory | 218324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349022631 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_volatile_unlock_smoke.3349022631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/40.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.3732272846 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 35582899 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:12:27 AM UTC 24 |
| Finished | Sep 11 08:12:29 AM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732272846 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3732272846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_errors.3066501262 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 997640303 ps |
| CPU time | 13.04 seconds |
| Started | Sep 11 08:12:21 AM UTC 24 |
| Finished | Sep 11 08:12:35 AM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066501262 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3066501262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.2878719375 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 1474912806 ps |
| CPU time | 7.47 seconds |
| Started | Sep 11 08:12:21 AM UTC 24 |
| Finished | Sep 11 08:12:29 AM UTC 24 |
| Peak memory | 229436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878719375 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_acce ss.2878719375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1353645690 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 60719010 ps |
| CPU time | 3.12 seconds |
| Started | Sep 11 08:12:19 AM UTC 24 |
| Finished | Sep 11 08:12:24 AM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353645690 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1353645690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.3335095900 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 1744403260 ps |
| CPU time | 27.72 seconds |
| Started | Sep 11 08:12:21 AM UTC 24 |
| Finished | Sep 11 08:12:50 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335095900 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3335095900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3850133718 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 344564660 ps |
| CPU time | 12.87 seconds |
| Started | Sep 11 08:12:23 AM UTC 24 |
| Finished | Sep 11 08:12:37 AM UTC 24 |
| Peak memory | 237884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850133718 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_ token_digest.3850133718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.2826938511 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 1115084699 ps |
| CPU time | 13.72 seconds |
| Started | Sep 11 08:12:22 AM UTC 24 |
| Finished | Sep 11 08:12:37 AM UTC 24 |
| Peak memory | 237900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826938511 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_tok en_mux.2826938511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.2837845590 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1012226649 ps |
| CPU time | 9.81 seconds |
| Started | Sep 11 08:12:21 AM UTC 24 |
| Finished | Sep 11 08:12:32 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837845590 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.2837845590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.1286529233 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 84062604 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 08:12:14 AM UTC 24 |
| Finished | Sep 11 08:12:19 AM UTC 24 |
| Peak memory | 235984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286529233 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1286529233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.3437379207 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 367882055 ps |
| CPU time | 37.42 seconds |
| Started | Sep 11 08:12:17 AM UTC 24 |
| Finished | Sep 11 08:12:56 AM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437379207 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3437379207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.351951262 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 243896603 ps |
| CPU time | 12.58 seconds |
| Started | Sep 11 08:12:18 AM UTC 24 |
| Finished | Sep 11 08:12:32 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351951262 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.351951262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2916822490 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 12038793377 ps |
| CPU time | 120.31 seconds |
| Started | Sep 11 08:12:25 AM UTC 24 |
| Finished | Sep 11 08:14:27 AM UTC 24 |
| Peak memory | 295840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2916822490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 41.lc_ctrl_stress_all.2916822490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.265236313 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 1497909888 ps |
| CPU time | 29.63 seconds |
| Started | Sep 11 08:12:25 AM UTC 24 |
| Finished | Sep 11 08:12:55 AM UTC 24 |
| Peak memory | 238288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265236313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.265236313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2879453788 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 43085283 ps |
| CPU time | 1.49 seconds |
| Started | Sep 11 08:12:15 AM UTC 24 |
| Finished | Sep 11 08:12:18 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879453788 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_volatile_unlock_smoke.2879453788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/41.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.1887407225 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 27086293 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:12:36 AM UTC 24 |
| Finished | Sep 11 08:12:38 AM UTC 24 |
| Peak memory | 217712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887407225 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1887407225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_errors.2622789831 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 812962451 ps |
| CPU time | 19.61 seconds |
| Started | Sep 11 08:12:31 AM UTC 24 |
| Finished | Sep 11 08:12:52 AM UTC 24 |
| Peak memory | 237888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622789831 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2622789831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.863468551 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1029048000 ps |
| CPU time | 5.59 seconds |
| Started | Sep 11 08:12:32 AM UTC 24 |
| Finished | Sep 11 08:12:39 AM UTC 24 |
| Peak memory | 230088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863468551 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.863468551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.2326301277 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 39198034 ps |
| CPU time | 2.54 seconds |
| Started | Sep 11 08:12:31 AM UTC 24 |
| Finished | Sep 11 08:12:34 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326301277 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2326301277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.1450303036 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 198506249 ps |
| CPU time | 13.23 seconds |
| Started | Sep 11 08:12:32 AM UTC 24 |
| Finished | Sep 11 08:12:47 AM UTC 24 |
| Peak memory | 232252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450303036 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1450303036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.1654136292 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 1165705335 ps |
| CPU time | 17.02 seconds |
| Started | Sep 11 08:12:33 AM UTC 24 |
| Finished | Sep 11 08:12:52 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654136292 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_ token_digest.1654136292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.1330323196 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 671504660 ps |
| CPU time | 13.44 seconds |
| Started | Sep 11 08:12:33 AM UTC 24 |
| Finished | Sep 11 08:12:48 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330323196 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_tok en_mux.1330323196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.1955011166 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 885494614 ps |
| CPU time | 10.29 seconds |
| Started | Sep 11 08:12:31 AM UTC 24 |
| Finished | Sep 11 08:12:42 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955011166 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1955011166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.4188830573 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 380003926 ps |
| CPU time | 3.92 seconds |
| Started | Sep 11 08:12:27 AM UTC 24 |
| Finished | Sep 11 08:12:32 AM UTC 24 |
| Peak memory | 230108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188830573 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.4188830573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.539820584 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 605923343 ps |
| CPU time | 23.55 seconds |
| Started | Sep 11 08:12:28 AM UTC 24 |
| Finished | Sep 11 08:12:53 AM UTC 24 |
| Peak memory | 260680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539820584 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.539820584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.3844231384 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 204459397 ps |
| CPU time | 13.97 seconds |
| Started | Sep 11 08:12:30 AM UTC 24 |
| Finished | Sep 11 08:12:45 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844231384 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3844231384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all.198298935 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 1576361143 ps |
| CPU time | 49.62 seconds |
| Started | Sep 11 08:12:33 AM UTC 24 |
| Finished | Sep 11 08:13:25 AM UTC 24 |
| Peak memory | 236644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=198298935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 42.lc_ctrl_stress_all.198298935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.162961553 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5167202086 ps |
| CPU time | 194.83 seconds |
| Started | Sep 11 08:12:36 AM UTC 24 |
| Finished | Sep 11 08:15:54 AM UTC 24 |
| Peak memory | 291608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162961553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.162961553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.540348944 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 176126890 ps |
| CPU time | 1.27 seconds |
| Started | Sep 11 08:12:28 AM UTC 24 |
| Finished | Sep 11 08:12:31 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540348944 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 2.lc_ctrl_volatile_unlock_smoke.540348944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/42.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.413277943 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 34458702 ps |
| CPU time | 1.35 seconds |
| Started | Sep 11 08:12:49 AM UTC 24 |
| Finished | Sep 11 08:12:51 AM UTC 24 |
| Peak memory | 218928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413277943 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.413277943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_errors.1280821271 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 1289988097 ps |
| CPU time | 14.45 seconds |
| Started | Sep 11 08:12:40 AM UTC 24 |
| Finished | Sep 11 08:12:55 AM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280821271 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1280821271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.946854329 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 640229543 ps |
| CPU time | 15.13 seconds |
| Started | Sep 11 08:12:43 AM UTC 24 |
| Finished | Sep 11 08:12:59 AM UTC 24 |
| Peak memory | 229244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946854329 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.946854329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.1918957613 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 95128984 ps |
| CPU time | 5.5 seconds |
| Started | Sep 11 08:12:40 AM UTC 24 |
| Finished | Sep 11 08:12:46 AM UTC 24 |
| Peak memory | 236268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918957613 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1918957613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.3549664369 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 781748471 ps |
| CPU time | 11.43 seconds |
| Started | Sep 11 08:12:45 AM UTC 24 |
| Finished | Sep 11 08:12:57 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549664369 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.3549664369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.3752024838 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 2454856503 ps |
| CPU time | 16.45 seconds |
| Started | Sep 11 08:12:46 AM UTC 24 |
| Finished | Sep 11 08:13:04 AM UTC 24 |
| Peak memory | 237944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752024838 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_ token_digest.3752024838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.1703330132 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 1233620064 ps |
| CPU time | 8.04 seconds |
| Started | Sep 11 08:12:46 AM UTC 24 |
| Finished | Sep 11 08:12:55 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703330132 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_tok en_mux.1703330132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.2547987401 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 643436202 ps |
| CPU time | 14.4 seconds |
| Started | Sep 11 08:12:42 AM UTC 24 |
| Finished | Sep 11 08:12:57 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547987401 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2547987401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.820456593 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 539676793 ps |
| CPU time | 5.83 seconds |
| Started | Sep 11 08:12:37 AM UTC 24 |
| Finished | Sep 11 08:12:44 AM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820456593 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.820456593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.1739284773 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 467580741 ps |
| CPU time | 27.82 seconds |
| Started | Sep 11 08:12:38 AM UTC 24 |
| Finished | Sep 11 08:13:07 AM UTC 24 |
| Peak memory | 262740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739284773 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1739284773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.3857500257 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 242114997 ps |
| CPU time | 9.79 seconds |
| Started | Sep 11 08:12:38 AM UTC 24 |
| Finished | Sep 11 08:12:49 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857500257 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3857500257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1923364005 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 18072155201 ps |
| CPU time | 149.08 seconds |
| Started | Sep 11 08:12:47 AM UTC 24 |
| Finished | Sep 11 08:15:19 AM UTC 24 |
| Peak memory | 281240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1923364005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 43.lc_ctrl_stress_all.1923364005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3753515831 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 43149393 ps |
| CPU time | 1.18 seconds |
| Started | Sep 11 08:12:38 AM UTC 24 |
| Finished | Sep 11 08:12:40 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3753515831 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_volatile_unlock_smoke.3753515831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/43.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.3200853824 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 16526696 ps |
| CPU time | 1.25 seconds |
| Started | Sep 11 08:12:56 AM UTC 24 |
| Finished | Sep 11 08:12:59 AM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200853824 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3200853824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_errors.3712508612 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 573824059 ps |
| CPU time | 25.41 seconds |
| Started | Sep 11 08:12:52 AM UTC 24 |
| Finished | Sep 11 08:13:19 AM UTC 24 |
| Peak memory | 237972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712508612 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3712508612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.885415158 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 1777192552 ps |
| CPU time | 9.59 seconds |
| Started | Sep 11 08:12:55 AM UTC 24 |
| Finished | Sep 11 08:13:05 AM UTC 24 |
| Peak memory | 229584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885415158 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.885415158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2039466 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 195938443 ps |
| CPU time | 4.35 seconds |
| Started | Sep 11 08:12:52 AM UTC 24 |
| Finished | Sep 11 08:12:58 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039466 -assert nopostproc +UVM_TESTNAME=lc_ctr l_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2039466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.3446459487 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 324996863 ps |
| CPU time | 13.94 seconds |
| Started | Sep 11 08:12:55 AM UTC 24 |
| Finished | Sep 11 08:13:10 AM UTC 24 |
| Peak memory | 232440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446459487 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3446459487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.2701831635 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 283466961 ps |
| CPU time | 10.13 seconds |
| Started | Sep 11 08:12:56 AM UTC 24 |
| Finished | Sep 11 08:13:07 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701831635 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_ token_digest.2701831635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_mux.19334420 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 499447468 ps |
| CPU time | 13.49 seconds |
| Started | Sep 11 08:12:56 AM UTC 24 |
| Finished | Sep 11 08:13:11 AM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19334420 -assert nopos tproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token _mux.19334420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.2225446457 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 468218754 ps |
| CPU time | 15.67 seconds |
| Started | Sep 11 08:12:53 AM UTC 24 |
| Finished | Sep 11 08:13:10 AM UTC 24 |
| Peak memory | 238148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225446457 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2225446457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.961158523 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 42368383 ps |
| CPU time | 4.39 seconds |
| Started | Sep 11 08:12:50 AM UTC 24 |
| Finished | Sep 11 08:12:55 AM UTC 24 |
| Peak memory | 225820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961158523 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.961158523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.2198091604 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 559224624 ps |
| CPU time | 36.29 seconds |
| Started | Sep 11 08:12:51 AM UTC 24 |
| Finished | Sep 11 08:13:29 AM UTC 24 |
| Peak memory | 260700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198091604 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2198091604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.4187278040 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 179917142 ps |
| CPU time | 12.65 seconds |
| Started | Sep 11 08:12:52 AM UTC 24 |
| Finished | Sep 11 08:13:06 AM UTC 24 |
| Peak memory | 262776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187278040 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.4187278040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3403799996 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 6595339863 ps |
| CPU time | 124.25 seconds |
| Started | Sep 11 08:12:56 AM UTC 24 |
| Finished | Sep 11 08:15:03 AM UTC 24 |
| Peak memory | 258704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3403799996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 44.lc_ctrl_stress_all.3403799996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.578404676 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 2839269611 ps |
| CPU time | 155.38 seconds |
| Started | Sep 11 08:12:56 AM UTC 24 |
| Finished | Sep 11 08:15:34 AM UTC 24 |
| Peak memory | 281436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578404676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_ SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_u nlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.578404676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4143836589 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 14214115 ps |
| CPU time | 1.61 seconds |
| Started | Sep 11 08:12:50 AM UTC 24 |
| Finished | Sep 11 08:12:52 AM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4143836589 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_volatile_unlock_smoke.4143836589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/44.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2270044122 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 18397193 ps |
| CPU time | 1.38 seconds |
| Started | Sep 11 08:13:07 AM UTC 24 |
| Finished | Sep 11 08:13:09 AM UTC 24 |
| Peak memory | 218924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270044122 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2270044122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_errors.3341222993 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 733767763 ps |
| CPU time | 18.69 seconds |
| Started | Sep 11 08:13:00 AM UTC 24 |
| Finished | Sep 11 08:13:20 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341222993 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3341222993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.1817546665 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 249805995 ps |
| CPU time | 4.82 seconds |
| Started | Sep 11 08:13:02 AM UTC 24 |
| Finished | Sep 11 08:13:08 AM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817546665 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_acce ss.1817546665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.2447644989 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 132521877 ps |
| CPU time | 5.04 seconds |
| Started | Sep 11 08:13:00 AM UTC 24 |
| Finished | Sep 11 08:13:06 AM UTC 24 |
| Peak memory | 236604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447644989 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2447644989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.3695469916 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 331331957 ps |
| CPU time | 14.51 seconds |
| Started | Sep 11 08:13:04 AM UTC 24 |
| Finished | Sep 11 08:13:20 AM UTC 24 |
| Peak memory | 232180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695469916 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3695469916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1579152652 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1341765657 ps |
| CPU time | 16.06 seconds |
| Started | Sep 11 08:13:06 AM UTC 24 |
| Finished | Sep 11 08:13:23 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579152652 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_ token_digest.1579152652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3175526338 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1236544040 ps |
| CPU time | 14.35 seconds |
| Started | Sep 11 08:13:06 AM UTC 24 |
| Finished | Sep 11 08:13:21 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3175526338 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_tok en_mux.3175526338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.237698732 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1707929058 ps |
| CPU time | 9.23 seconds |
| Started | Sep 11 08:13:01 AM UTC 24 |
| Finished | Sep 11 08:13:11 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237698732 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.237698732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.2838097698 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 91746594 ps |
| CPU time | 2.69 seconds |
| Started | Sep 11 08:12:58 AM UTC 24 |
| Finished | Sep 11 08:13:01 AM UTC 24 |
| Peak memory | 229836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838097698 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2838097698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1124972471 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 2833132218 ps |
| CPU time | 38 seconds |
| Started | Sep 11 08:12:59 AM UTC 24 |
| Finished | Sep 11 08:13:38 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124972471 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1124972471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.2939564866 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 228415478 ps |
| CPU time | 6.13 seconds |
| Started | Sep 11 08:12:59 AM UTC 24 |
| Finished | Sep 11 08:13:06 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939564866 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2939564866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3742598452 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 4053456851 ps |
| CPU time | 113.85 seconds |
| Started | Sep 11 08:13:07 AM UTC 24 |
| Finished | Sep 11 08:15:03 AM UTC 24 |
| Peak memory | 295904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3742598452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 45.lc_ctrl_stress_all.3742598452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.892991923 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 78522321 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 08:12:58 AM UTC 24 |
| Finished | Sep 11 08:13:00 AM UTC 24 |
| Peak memory | 222904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892991923 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 5.lc_ctrl_volatile_unlock_smoke.892991923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/45.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.4162596312 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 17395191 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:13:17 AM UTC 24 |
| Finished | Sep 11 08:13:21 AM UTC 24 |
| Peak memory | 217776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162596312 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.4162596312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2872799205 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 3762477499 ps |
| CPU time | 35.04 seconds |
| Started | Sep 11 08:13:11 AM UTC 24 |
| Finished | Sep 11 08:13:47 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872799205 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2872799205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.1784364780 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 90834400 ps |
| CPU time | 1.97 seconds |
| Started | Sep 11 08:13:12 AM UTC 24 |
| Finished | Sep 11 08:13:15 AM UTC 24 |
| Peak memory | 228844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784364780 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_acce ss.1784364780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.3132671027 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 193407751 ps |
| CPU time | 3.66 seconds |
| Started | Sep 11 08:13:10 AM UTC 24 |
| Finished | Sep 11 08:13:14 AM UTC 24 |
| Peak memory | 236540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3132671027 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3132671027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.2121214670 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 332580986 ps |
| CPU time | 12.45 seconds |
| Started | Sep 11 08:13:12 AM UTC 24 |
| Finished | Sep 11 08:13:26 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121214670 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2121214670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1096330123 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1484152242 ps |
| CPU time | 17.51 seconds |
| Started | Sep 11 08:13:15 AM UTC 24 |
| Finished | Sep 11 08:13:33 AM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096330123 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_ token_digest.1096330123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_mux.998376579 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 257354085 ps |
| CPU time | 11.34 seconds |
| Started | Sep 11 08:13:12 AM UTC 24 |
| Finished | Sep 11 08:13:25 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998376579 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_toke n_mux.998376579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_security_escalation.986142708 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 431849876 ps |
| CPU time | 10.42 seconds |
| Started | Sep 11 08:13:11 AM UTC 24 |
| Finished | Sep 11 08:13:22 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986142708 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.986142708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.994245800 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 64050321 ps |
| CPU time | 4.29 seconds |
| Started | Sep 11 08:13:08 AM UTC 24 |
| Finished | Sep 11 08:13:14 AM UTC 24 |
| Peak memory | 225848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994245800 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.994245800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2803234384 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 314487421 ps |
| CPU time | 28.78 seconds |
| Started | Sep 11 08:13:09 AM UTC 24 |
| Finished | Sep 11 08:13:39 AM UTC 24 |
| Peak memory | 263156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803234384 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2803234384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.2867642202 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 80032260 ps |
| CPU time | 10.55 seconds |
| Started | Sep 11 08:13:09 AM UTC 24 |
| Finished | Sep 11 08:13:20 AM UTC 24 |
| Peak memory | 263004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867642202 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2867642202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3061928704 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 34477938754 ps |
| CPU time | 210.08 seconds |
| Started | Sep 11 08:13:16 AM UTC 24 |
| Finished | Sep 11 08:16:49 AM UTC 24 |
| Peak memory | 262848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=3061928704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 46.lc_ctrl_stress_all.3061928704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3920629907 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 2250733526 ps |
| CPU time | 82.63 seconds |
| Started | Sep 11 08:13:16 AM UTC 24 |
| Finished | Sep 11 08:14:40 AM UTC 24 |
| Peak memory | 281368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920629907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.3920629907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.230742772 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 12971044 ps |
| CPU time | 1.48 seconds |
| Started | Sep 11 08:13:09 AM UTC 24 |
| Finished | Sep 11 08:13:11 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230742772 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4 6.lc_ctrl_volatile_unlock_smoke.230742772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/46.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.4242925249 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 22826024 ps |
| CPU time | 1.32 seconds |
| Started | Sep 11 08:13:28 AM UTC 24 |
| Finished | Sep 11 08:13:30 AM UTC 24 |
| Peak memory | 217772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242925249 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.4242925249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.834119258 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 1616596785 ps |
| CPU time | 18.62 seconds |
| Started | Sep 11 08:13:23 AM UTC 24 |
| Finished | Sep 11 08:13:43 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=834119258 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.834119258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3922243756 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 2806065783 ps |
| CPU time | 9.75 seconds |
| Started | Sep 11 08:13:24 AM UTC 24 |
| Finished | Sep 11 08:13:35 AM UTC 24 |
| Peak memory | 229872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922243756 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_acce ss.3922243756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.4100694553 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 59325397 ps |
| CPU time | 3.28 seconds |
| Started | Sep 11 08:13:21 AM UTC 24 |
| Finished | Sep 11 08:13:26 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100694553 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.4100694553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1445224111 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 469450272 ps |
| CPU time | 22.67 seconds |
| Started | Sep 11 08:13:25 AM UTC 24 |
| Finished | Sep 11 08:13:50 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445224111 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1445224111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2835107904 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 625699501 ps |
| CPU time | 17.94 seconds |
| Started | Sep 11 08:13:25 AM UTC 24 |
| Finished | Sep 11 08:13:45 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835107904 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_ token_digest.2835107904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2437164607 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1038543600 ps |
| CPU time | 9.19 seconds |
| Started | Sep 11 08:13:25 AM UTC 24 |
| Finished | Sep 11 08:13:36 AM UTC 24 |
| Peak memory | 237844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437164607 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_tok en_mux.2437164607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2246912750 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 329986854 ps |
| CPU time | 12.64 seconds |
| Started | Sep 11 08:13:24 AM UTC 24 |
| Finished | Sep 11 08:13:38 AM UTC 24 |
| Peak memory | 237880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246912750 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.2246912750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1937866256 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 68957327 ps |
| CPU time | 3.45 seconds |
| Started | Sep 11 08:13:20 AM UTC 24 |
| Finished | Sep 11 08:13:25 AM UTC 24 |
| Peak memory | 225740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937866256 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1937866256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3561269576 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1706873067 ps |
| CPU time | 38.38 seconds |
| Started | Sep 11 08:13:21 AM UTC 24 |
| Finished | Sep 11 08:14:01 AM UTC 24 |
| Peak memory | 263072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561269576 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3561269576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.882857537 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 253076944 ps |
| CPU time | 10.57 seconds |
| Started | Sep 11 08:13:21 AM UTC 24 |
| Finished | Sep 11 08:13:33 AM UTC 24 |
| Peak memory | 262568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882857537 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.882857537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_stress_all.997944831 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 3137485340 ps |
| CPU time | 40.52 seconds |
| Started | Sep 11 08:13:26 AM UTC 24 |
| Finished | Sep 11 08:14:09 AM UTC 24 |
| Peak memory | 262788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=997944831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 47.lc_ctrl_stress_all.997944831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1187106652 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 40001861 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:13:21 AM UTC 24 |
| Finished | Sep 11 08:13:24 AM UTC 24 |
| Peak memory | 222900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187106652 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_volatile_unlock_smoke.1187106652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/47.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.489647824 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 57029070 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:13:40 AM UTC 24 |
| Finished | Sep 11 08:13:42 AM UTC 24 |
| Peak memory | 219168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489647824 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.489647824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2017832563 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 260674012 ps |
| CPU time | 16.11 seconds |
| Started | Sep 11 08:13:34 AM UTC 24 |
| Finished | Sep 11 08:13:51 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017832563 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2017832563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2991582688 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 7512226988 ps |
| CPU time | 12.77 seconds |
| Started | Sep 11 08:13:35 AM UTC 24 |
| Finished | Sep 11 08:13:49 AM UTC 24 |
| Peak memory | 229948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991582688 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_acce ss.2991582688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.4233767525 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 270153245 ps |
| CPU time | 4.17 seconds |
| Started | Sep 11 08:13:34 AM UTC 24 |
| Finished | Sep 11 08:13:39 AM UTC 24 |
| Peak memory | 232180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233767525 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.4233767525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2081339126 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 288298075 ps |
| CPU time | 12.89 seconds |
| Started | Sep 11 08:13:36 AM UTC 24 |
| Finished | Sep 11 08:13:50 AM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081339126 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2081339126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4260306300 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 473291423 ps |
| CPU time | 11.21 seconds |
| Started | Sep 11 08:13:37 AM UTC 24 |
| Finished | Sep 11 08:13:50 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260306300 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_ token_digest.4260306300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.272241846 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 525745804 ps |
| CPU time | 23.5 seconds |
| Started | Sep 11 08:13:37 AM UTC 24 |
| Finished | Sep 11 08:14:02 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272241846 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_toke n_mux.272241846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1470412348 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 974061024 ps |
| CPU time | 15.56 seconds |
| Started | Sep 11 08:13:34 AM UTC 24 |
| Finished | Sep 11 08:13:51 AM UTC 24 |
| Peak memory | 237652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470412348 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1470412348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.1335106988 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 125076009 ps |
| CPU time | 3.76 seconds |
| Started | Sep 11 08:13:29 AM UTC 24 |
| Finished | Sep 11 08:13:35 AM UTC 24 |
| Peak memory | 235992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335106988 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.1335106988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.902787652 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 794253383 ps |
| CPU time | 33.88 seconds |
| Started | Sep 11 08:13:31 AM UTC 24 |
| Finished | Sep 11 08:14:06 AM UTC 24 |
| Peak memory | 262808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902787652 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.902787652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2950944266 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 187228379 ps |
| CPU time | 3.78 seconds |
| Started | Sep 11 08:13:32 AM UTC 24 |
| Finished | Sep 11 08:13:37 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950944266 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2950944266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.782917028 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 4801671264 ps |
| CPU time | 52.12 seconds |
| Started | Sep 11 08:13:39 AM UTC 24 |
| Finished | Sep 11 08:14:32 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=782917028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 48.lc_ctrl_stress_all.782917028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1651568941 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 15701328 ps |
| CPU time | 1.52 seconds |
| Started | Sep 11 08:13:29 AM UTC 24 |
| Finished | Sep 11 08:13:32 AM UTC 24 |
| Peak memory | 228844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1651568941 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_volatile_unlock_smoke.1651568941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/48.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3409205995 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 60169787 ps |
| CPU time | 1.63 seconds |
| Started | Sep 11 08:13:53 AM UTC 24 |
| Finished | Sep 11 08:13:56 AM UTC 24 |
| Peak memory | 218808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3409205995 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3409205995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1887613834 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1085016100 ps |
| CPU time | 9.56 seconds |
| Started | Sep 11 08:13:46 AM UTC 24 |
| Finished | Sep 11 08:13:57 AM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887613834 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1887613834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.742819310 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 1128829691 ps |
| CPU time | 9.16 seconds |
| Started | Sep 11 08:13:50 AM UTC 24 |
| Finished | Sep 11 08:14:01 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742819310 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.742819310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1352695472 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 859004588 ps |
| CPU time | 4.78 seconds |
| Started | Sep 11 08:13:46 AM UTC 24 |
| Finished | Sep 11 08:13:52 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352695472 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1352695472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1660464675 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 734723301 ps |
| CPU time | 16.85 seconds |
| Started | Sep 11 08:13:50 AM UTC 24 |
| Finished | Sep 11 08:14:09 AM UTC 24 |
| Peak memory | 232176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660464675 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1660464675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.815445073 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1112312934 ps |
| CPU time | 14.95 seconds |
| Started | Sep 11 08:13:51 AM UTC 24 |
| Finished | Sep 11 08:14:07 AM UTC 24 |
| Peak memory | 237892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815445073 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_t oken_digest.815445073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.4264966854 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 720973683 ps |
| CPU time | 9.14 seconds |
| Started | Sep 11 08:13:51 AM UTC 24 |
| Finished | Sep 11 08:14:01 AM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264966854 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_tok en_mux.4264966854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1485459205 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 320343849 ps |
| CPU time | 13.28 seconds |
| Started | Sep 11 08:13:49 AM UTC 24 |
| Finished | Sep 11 08:14:03 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485459205 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1485459205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1657393875 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 77975889 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 08:13:40 AM UTC 24 |
| Finished | Sep 11 08:13:46 AM UTC 24 |
| Peak memory | 225776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657393875 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1657393875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2539376631 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 852758713 ps |
| CPU time | 33.2 seconds |
| Started | Sep 11 08:13:44 AM UTC 24 |
| Finished | Sep 11 08:14:19 AM UTC 24 |
| Peak memory | 263156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539376631 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.2539376631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2882414893 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 54382678 ps |
| CPU time | 10.78 seconds |
| Started | Sep 11 08:13:46 AM UTC 24 |
| Finished | Sep 11 08:13:58 AM UTC 24 |
| Peak memory | 256860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882414893 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2882414893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.4107969879 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 62710502429 ps |
| CPU time | 297.92 seconds |
| Started | Sep 11 08:13:52 AM UTC 24 |
| Finished | Sep 11 08:18:54 AM UTC 24 |
| Peak memory | 262800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=4107969879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 49.lc_ctrl_stress_all.4107969879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3915763060 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 2362021219 ps |
| CPU time | 115.62 seconds |
| Started | Sep 11 08:13:52 AM UTC 24 |
| Finished | Sep 11 08:15:50 AM UTC 24 |
| Peak memory | 263008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_ rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915763060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST _SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_ unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.3915763060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2556378878 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 24214623 ps |
| CPU time | 1.46 seconds |
| Started | Sep 11 08:13:43 AM UTC 24 |
| Finished | Sep 11 08:13:46 AM UTC 24 |
| Peak memory | 222720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556378878 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_volatile_unlock_smoke.2556378878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/49.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_alert_test.3898084015 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 30726512 ps |
| CPU time | 1.34 seconds |
| Started | Sep 11 08:04:35 AM UTC 24 |
| Finished | Sep 11 08:04:37 AM UTC 24 |
| Peak memory | 217684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898084015 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3898084015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_claim_transition_if.2002742494 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 30388804 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 08:04:19 AM UTC 24 |
| Finished | Sep 11 08:04:22 AM UTC 24 |
| Peak memory | 219012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002742494 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2002742494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_errors.2422688823 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 214195540 ps |
| CPU time | 10.15 seconds |
| Started | Sep 11 08:04:16 AM UTC 24 |
| Finished | Sep 11 08:04:28 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422688823 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2422688823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_access.4292741387 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 356631673 ps |
| CPU time | 6.77 seconds |
| Started | Sep 11 08:04:24 AM UTC 24 |
| Finished | Sep 11 08:04:32 AM UTC 24 |
| Peak memory | 229564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292741387 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.4292741387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_errors.2147802944 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2499584072 ps |
| CPU time | 46.61 seconds |
| Started | Sep 11 08:04:24 AM UTC 24 |
| Finished | Sep 11 08:05:12 AM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147802944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_ jtag_errors.2147802944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_priority.3119821356 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 5791707624 ps |
| CPU time | 26.43 seconds |
| Started | Sep 11 08:04:24 AM UTC 24 |
| Finished | Sep 11 08:04:52 AM UTC 24 |
| Peak memory | 230036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119821356 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_pri ority.3119821356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_prog_failure.3486254255 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 590299622 ps |
| CPU time | 9.75 seconds |
| Started | Sep 11 08:04:22 AM UTC 24 |
| Finished | Sep 11 08:04:34 AM UTC 24 |
| Peak memory | 232380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486254255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct rl_jtag_prog_failure.3486254255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3373011172 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 910081741 ps |
| CPU time | 17.84 seconds |
| Started | Sep 11 08:04:25 AM UTC 24 |
| Finished | Sep 11 08:04:44 AM UTC 24 |
| Peak memory | 230200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373011172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_jtag_regwen_during_op.3373011172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_smoke.18498542 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 250504476 ps |
| CPU time | 7.83 seconds |
| Started | Sep 11 08:04:19 AM UTC 24 |
| Finished | Sep 11 08:04:28 AM UTC 24 |
| Peak memory | 230052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18498542 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_s moke.18498542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_failure.4282209932 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1187399054 ps |
| CPU time | 63.61 seconds |
| Started | Sep 11 08:04:19 AM UTC 24 |
| Finished | Sep 11 08:05:25 AM UTC 24 |
| Peak memory | 262936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282209932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_c trl_jtag_state_failure.4282209932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_jtag_state_post_trans.1109623361 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 791245669 ps |
| CPU time | 37.67 seconds |
| Started | Sep 11 08:04:21 AM UTC 24 |
| Finished | Sep 11 08:05:01 AM UTC 24 |
| Peak memory | 262640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109623361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.l c_ctrl_jtag_state_post_trans.1109623361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_prog_failure.2844025638 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 350630246 ps |
| CPU time | 4.88 seconds |
| Started | Sep 11 08:04:16 AM UTC 24 |
| Finished | Sep 11 08:04:22 AM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844025638 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2844025638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_regwen_during_op.3288477082 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 498902458 ps |
| CPU time | 10.87 seconds |
| Started | Sep 11 08:04:18 AM UTC 24 |
| Finished | Sep 11 08:04:30 AM UTC 24 |
| Peak memory | 229924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288477082 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.3288477082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_mubi.1719015051 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 320005166 ps |
| CPU time | 12.21 seconds |
| Started | Sep 11 08:04:28 AM UTC 24 |
| Finished | Sep 11 08:04:42 AM UTC 24 |
| Peak memory | 238152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719015051 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.1719015051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_digest.3936993215 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 1425280632 ps |
| CPU time | 19.11 seconds |
| Started | Sep 11 08:04:31 AM UTC 24 |
| Finished | Sep 11 08:04:52 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936993215 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_t oken_digest.3936993215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_sec_token_mux.3041143975 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 2011907129 ps |
| CPU time | 18.9 seconds |
| Started | Sep 11 08:04:29 AM UTC 24 |
| Finished | Sep 11 08:04:49 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041143975 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_toke n_mux.3041143975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_security_escalation.2208963833 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 381341351 ps |
| CPU time | 14.99 seconds |
| Started | Sep 11 08:04:18 AM UTC 24 |
| Finished | Sep 11 08:04:35 AM UTC 24 |
| Peak memory | 232480 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208963833 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2208963833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_smoke.634887920 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 97205437 ps |
| CPU time | 3.23 seconds |
| Started | Sep 11 08:04:11 AM UTC 24 |
| Finished | Sep 11 08:04:15 AM UTC 24 |
| Peak memory | 225748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=634887920 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.634887920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_failure.3629293090 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 314874084 ps |
| CPU time | 27.18 seconds |
| Started | Sep 11 08:04:15 AM UTC 24 |
| Finished | Sep 11 08:04:43 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3629293090 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3629293090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_state_post_trans.2744169599 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 77797213 ps |
| CPU time | 12.6 seconds |
| Started | Sep 11 08:04:16 AM UTC 24 |
| Finished | Sep 11 08:04:30 AM UTC 24 |
| Peak memory | 260704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744169599 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2744169599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.1381440733 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 13763278183 ps |
| CPU time | 164.95 seconds |
| Started | Sep 11 08:04:31 AM UTC 24 |
| Finished | Sep 11 08:07:19 AM UTC 24 |
| Peak memory | 263068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1381440733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 5.lc_ctrl_stress_all.1381440733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2556592154 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 13322785 ps |
| CPU time | 1.2 seconds |
| Started | Sep 11 08:04:15 AM UTC 24 |
| Finished | Sep 11 08:04:17 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556592154 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_volatile_unlock_smoke.2556592154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/5.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_alert_test.1946602957 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 47202934 ps |
| CPU time | 1.59 seconds |
| Started | Sep 11 08:04:57 AM UTC 24 |
| Finished | Sep 11 08:04:59 AM UTC 24 |
| Peak memory | 218688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946602957 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1946602957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_claim_transition_if.3896847699 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 18082056 ps |
| CPU time | 1.13 seconds |
| Started | Sep 11 08:04:43 AM UTC 24 |
| Finished | Sep 11 08:04:45 AM UTC 24 |
| Peak memory | 218952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896847699 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3896847699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_claim_transition_if/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_errors.1926821925 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 788915193 ps |
| CPU time | 27.28 seconds |
| Started | Sep 11 08:04:40 AM UTC 24 |
| Finished | Sep 11 08:05:08 AM UTC 24 |
| Peak memory | 232444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1926821925 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1926821925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_access.1662533882 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 183338649 ps |
| CPU time | 3.62 seconds |
| Started | Sep 11 08:04:47 AM UTC 24 |
| Finished | Sep 11 08:04:51 AM UTC 24 |
| Peak memory | 229172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662533882 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1662533882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_errors.982102736 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3363253133 ps |
| CPU time | 61.8 seconds |
| Started | Sep 11 08:04:45 AM UTC 24 |
| Finished | Sep 11 08:05:49 AM UTC 24 |
| Peak memory | 238208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=982102736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j tag_errors.982102736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_priority.3702378768 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 717265235 ps |
| CPU time | 4.54 seconds |
| Started | Sep 11 08:04:50 AM UTC 24 |
| Finished | Sep 11 08:04:55 AM UTC 24 |
| Peak memory | 229968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702378768 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_pri ority.3702378768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_prog_failure.2906452039 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 371401920 ps |
| CPU time | 12.5 seconds |
| Started | Sep 11 08:04:44 AM UTC 24 |
| Finished | Sep 11 08:04:58 AM UTC 24 |
| Peak memory | 236196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906452039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_jtag_prog_failure.2906452039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2913851002 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4904058969 ps |
| CPU time | 25.63 seconds |
| Started | Sep 11 08:04:51 AM UTC 24 |
| Finished | Sep 11 08:05:18 AM UTC 24 |
| Peak memory | 229844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913851002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_jtag_regwen_during_op.2913851002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_smoke.2991782794 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 575551625 ps |
| CPU time | 9.88 seconds |
| Started | Sep 11 08:04:44 AM UTC 24 |
| Finished | Sep 11 08:04:55 AM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991782794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag _smoke.2991782794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_failure.875831677 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 24423692792 ps |
| CPU time | 67.67 seconds |
| Started | Sep 11 08:04:44 AM UTC 24 |
| Finished | Sep 11 08:05:54 AM UTC 24 |
| Peak memory | 283288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875831677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct rl_jtag_state_failure.875831677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_jtag_state_post_trans.4062156602 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 802165490 ps |
| CPU time | 19.43 seconds |
| Started | Sep 11 08:04:44 AM UTC 24 |
| Finished | Sep 11 08:05:05 AM UTC 24 |
| Peak memory | 262580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062156602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.l c_ctrl_jtag_state_post_trans.4062156602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_prog_failure.2172919691 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 225373613 ps |
| CPU time | 3.67 seconds |
| Started | Sep 11 08:04:39 AM UTC 24 |
| Finished | Sep 11 08:04:44 AM UTC 24 |
| Peak memory | 232276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172919691 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2172919691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_regwen_during_op.3075145960 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 488892247 ps |
| CPU time | 9.3 seconds |
| Started | Sep 11 08:04:41 AM UTC 24 |
| Finished | Sep 11 08:04:51 AM UTC 24 |
| Peak memory | 230116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075145960 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3075145960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_mubi.2878413597 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1193128131 ps |
| CPU time | 14.41 seconds |
| Started | Sep 11 08:04:52 AM UTC 24 |
| Finished | Sep 11 08:05:07 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878413597 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2878413597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_digest.3498269164 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2609868659 ps |
| CPU time | 21.85 seconds |
| Started | Sep 11 08:04:53 AM UTC 24 |
| Finished | Sep 11 08:05:16 AM UTC 24 |
| Peak memory | 237948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3498269164 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_t oken_digest.3498269164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_sec_token_mux.1580773921 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 5571026175 ps |
| CPU time | 8.81 seconds |
| Started | Sep 11 08:04:52 AM UTC 24 |
| Finished | Sep 11 08:05:02 AM UTC 24 |
| Peak memory | 232484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580773921 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_toke n_mux.1580773921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_security_escalation.196191037 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 839494433 ps |
| CPU time | 11.46 seconds |
| Started | Sep 11 08:04:41 AM UTC 24 |
| Finished | Sep 11 08:04:53 AM UTC 24 |
| Peak memory | 232232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=196191037 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.196191037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_smoke.1222503284 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 220901684 ps |
| CPU time | 7.21 seconds |
| Started | Sep 11 08:04:35 AM UTC 24 |
| Finished | Sep 11 08:04:43 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222503284 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1222503284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_failure.3364718867 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 366815233 ps |
| CPU time | 37.91 seconds |
| Started | Sep 11 08:04:36 AM UTC 24 |
| Finished | Sep 11 08:05:16 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3364718867 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3364718867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_state_post_trans.3532434161 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 75755533 ps |
| CPU time | 4.48 seconds |
| Started | Sep 11 08:04:38 AM UTC 24 |
| Finished | Sep 11 08:04:43 AM UTC 24 |
| Peak memory | 238160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532434161 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3532434161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1874348015 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 14076536425 ps |
| CPU time | 54.24 seconds |
| Started | Sep 11 08:04:53 AM UTC 24 |
| Finished | Sep 11 08:05:49 AM UTC 24 |
| Peak memory | 262796 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=1874348015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 6.lc_ctrl_stress_all.1874348015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1028147822 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 33755494 ps |
| CPU time | 1.36 seconds |
| Started | Sep 11 08:04:36 AM UTC 24 |
| Finished | Sep 11 08:04:39 AM UTC 24 |
| Peak memory | 222724 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028147822 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_volatile_unlock_smoke.1028147822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/6.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_alert_test.391912424 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 20167848 ps |
| CPU time | 1.62 seconds |
| Started | Sep 11 08:05:19 AM UTC 24 |
| Finished | Sep 11 08:05:22 AM UTC 24 |
| Peak memory | 218692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391912424 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.391912424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_errors.566403266 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2715349428 ps |
| CPU time | 25.21 seconds |
| Started | Sep 11 08:05:00 AM UTC 24 |
| Finished | Sep 11 08:05:27 AM UTC 24 |
| Peak memory | 238220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566403266 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.566403266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_access.1024526887 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 613904996 ps |
| CPU time | 20.59 seconds |
| Started | Sep 11 08:05:13 AM UTC 24 |
| Finished | Sep 11 08:05:35 AM UTC 24 |
| Peak memory | 229488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024526887 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1024526887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_errors.2350807691 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 8303574111 ps |
| CPU time | 39.57 seconds |
| Started | Sep 11 08:05:10 AM UTC 24 |
| Finished | Sep 11 08:05:51 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2350807691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_ jtag_errors.2350807691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_priority.2818227896 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 1654754979 ps |
| CPU time | 16.38 seconds |
| Started | Sep 11 08:05:14 AM UTC 24 |
| Finished | Sep 11 08:05:32 AM UTC 24 |
| Peak memory | 230044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818227896 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_pri ority.2818227896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_prog_failure.3460758979 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 311445776 ps |
| CPU time | 7.18 seconds |
| Started | Sep 11 08:05:10 AM UTC 24 |
| Finished | Sep 11 08:05:18 AM UTC 24 |
| Peak memory | 236368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460758979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct rl_jtag_prog_failure.3460758979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3991418434 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 1948747726 ps |
| CPU time | 37.62 seconds |
| Started | Sep 11 08:05:16 AM UTC 24 |
| Finished | Sep 11 08:05:56 AM UTC 24 |
| Peak memory | 229856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991418434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l c_ctrl_jtag_regwen_during_op.3991418434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_smoke.2868827419 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 1503999919 ps |
| CPU time | 9 seconds |
| Started | Sep 11 08:05:06 AM UTC 24 |
| Finished | Sep 11 08:05:17 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868827419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag _smoke.2868827419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.2306821939 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 6371456675 ps |
| CPU time | 75.89 seconds |
| Started | Sep 11 08:05:09 AM UTC 24 |
| Finished | Sep 11 08:06:26 AM UTC 24 |
| Peak memory | 295576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306821939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_c trl_jtag_state_failure.2306821939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_post_trans.3507517939 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2849617509 ps |
| CPU time | 21.07 seconds |
| Started | Sep 11 08:05:09 AM UTC 24 |
| Finished | Sep 11 08:05:31 AM UTC 24 |
| Peak memory | 262748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507517939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.l c_ctrl_jtag_state_post_trans.3507517939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_prog_failure.3249483373 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 482288867 ps |
| CPU time | 4.66 seconds |
| Started | Sep 11 08:05:00 AM UTC 24 |
| Finished | Sep 11 08:05:06 AM UTC 24 |
| Peak memory | 236268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249483373 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3249483373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_regwen_during_op.3961953700 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 470099468 ps |
| CPU time | 22.57 seconds |
| Started | Sep 11 08:05:03 AM UTC 24 |
| Finished | Sep 11 08:05:27 AM UTC 24 |
| Peak memory | 225832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961953700 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3961953700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_mubi.4037253930 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 671932605 ps |
| CPU time | 14.09 seconds |
| Started | Sep 11 08:05:18 AM UTC 24 |
| Finished | Sep 11 08:05:33 AM UTC 24 |
| Peak memory | 237948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037253930 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.4037253930 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_digest.1564540493 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2922863662 ps |
| CPU time | 13.33 seconds |
| Started | Sep 11 08:05:18 AM UTC 24 |
| Finished | Sep 11 08:05:33 AM UTC 24 |
| Peak memory | 232228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564540493 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_t oken_digest.1564540493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_sec_token_mux.2308311364 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 754145814 ps |
| CPU time | 8.66 seconds |
| Started | Sep 11 08:05:18 AM UTC 24 |
| Finished | Sep 11 08:05:28 AM UTC 24 |
| Peak memory | 232420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308311364 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_toke n_mux.2308311364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_security_escalation.3787166948 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 1397333668 ps |
| CPU time | 12.93 seconds |
| Started | Sep 11 08:05:01 AM UTC 24 |
| Finished | Sep 11 08:05:15 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787166948 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3787166948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_smoke.3134213224 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 480972326 ps |
| CPU time | 11.1 seconds |
| Started | Sep 11 08:04:57 AM UTC 24 |
| Finished | Sep 11 08:05:09 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134213224 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3134213224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_failure.3345076758 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 377743421 ps |
| CPU time | 44.32 seconds |
| Started | Sep 11 08:04:59 AM UTC 24 |
| Finished | Sep 11 08:05:44 AM UTC 24 |
| Peak memory | 262732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345076758 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3345076758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_state_post_trans.1523446042 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 57677439 ps |
| CPU time | 12.25 seconds |
| Started | Sep 11 08:05:00 AM UTC 24 |
| Finished | Sep 11 08:05:13 AM UTC 24 |
| Peak memory | 262736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523446042 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1523446042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all.360585907 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 14832006176 ps |
| CPU time | 136.07 seconds |
| Started | Sep 11 08:05:18 AM UTC 24 |
| Finished | Sep 11 08:07:37 AM UTC 24 |
| Peak memory | 262876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=360585907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 7.lc_ctrl_stress_all.360585907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/7.lc_ctrl_volatile_unlock_smoke.980325593 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 11580881 ps |
| CPU time | 1.5 seconds |
| Started | Sep 11 08:04:57 AM UTC 24 |
| Finished | Sep 11 08:04:59 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980325593 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7 .lc_ctrl_volatile_unlock_smoke.980325593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/7.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_alert_test.1318527881 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 31483327 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:05:45 AM UTC 24 |
| Finished | Sep 11 08:05:48 AM UTC 24 |
| Peak memory | 218804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318527881 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1318527881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_errors.640946771 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 225488706 ps |
| CPU time | 13 seconds |
| Started | Sep 11 08:05:27 AM UTC 24 |
| Finished | Sep 11 08:05:41 AM UTC 24 |
| Peak memory | 230196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640946771 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.640946771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_access.1455162987 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 1505432621 ps |
| CPU time | 13.26 seconds |
| Started | Sep 11 08:05:34 AM UTC 24 |
| Finished | Sep 11 08:05:49 AM UTC 24 |
| Peak memory | 229916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455162987 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1455162987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.3250709628 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 3160273003 ps |
| CPU time | 116.61 seconds |
| Started | Sep 11 08:05:34 AM UTC 24 |
| Finished | Sep 11 08:07:33 AM UTC 24 |
| Peak memory | 232424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250709628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_ jtag_errors.3250709628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_priority.3537839738 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 530843700 ps |
| CPU time | 11.17 seconds |
| Started | Sep 11 08:05:36 AM UTC 24 |
| Finished | Sep 11 08:05:48 AM UTC 24 |
| Peak memory | 229900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537839738 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_pri ority.3537839738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_prog_failure.2948954438 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 2365101952 ps |
| CPU time | 16.67 seconds |
| Started | Sep 11 08:05:34 AM UTC 24 |
| Finished | Sep 11 08:05:52 AM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948954438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct rl_jtag_prog_failure.2948954438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2400690219 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 8102457423 ps |
| CPU time | 31.95 seconds |
| Started | Sep 11 08:05:38 AM UTC 24 |
| Finished | Sep 11 08:06:12 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400690219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_jtag_regwen_during_op.2400690219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_smoke.774473841 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 200069411 ps |
| CPU time | 4.49 seconds |
| Started | Sep 11 08:05:32 AM UTC 24 |
| Finished | Sep 11 08:05:37 AM UTC 24 |
| Peak memory | 229692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774473841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_ smoke.774473841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.1492968508 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 14342220899 ps |
| CPU time | 82.23 seconds |
| Started | Sep 11 08:05:32 AM UTC 24 |
| Finished | Sep 11 08:06:56 AM UTC 24 |
| Peak memory | 289356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492968508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_c trl_jtag_state_failure.1492968508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_post_trans.3026972577 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 395829478 ps |
| CPU time | 17.09 seconds |
| Started | Sep 11 08:05:33 AM UTC 24 |
| Finished | Sep 11 08:05:51 AM UTC 24 |
| Peak memory | 232184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026972577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.l c_ctrl_jtag_state_post_trans.3026972577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_prog_failure.2126420901 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 87142000 ps |
| CPU time | 6.18 seconds |
| Started | Sep 11 08:05:26 AM UTC 24 |
| Finished | Sep 11 08:05:33 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126420901 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2126420901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_regwen_during_op.1939124528 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 303079621 ps |
| CPU time | 18.1 seconds |
| Started | Sep 11 08:05:28 AM UTC 24 |
| Finished | Sep 11 08:05:48 AM UTC 24 |
| Peak memory | 225116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939124528 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1939124528 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_mubi.105332381 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 265756393 ps |
| CPU time | 13.85 seconds |
| Started | Sep 11 08:05:40 AM UTC 24 |
| Finished | Sep 11 08:05:55 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105332381 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.105332381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_digest.4118288418 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 653168001 ps |
| CPU time | 8.71 seconds |
| Started | Sep 11 08:05:41 AM UTC 24 |
| Finished | Sep 11 08:05:51 AM UTC 24 |
| Peak memory | 232164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118288418 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_t oken_digest.4118288418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_sec_token_mux.3043647472 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 1167993527 ps |
| CPU time | 6.98 seconds |
| Started | Sep 11 08:05:40 AM UTC 24 |
| Finished | Sep 11 08:05:48 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3043647472 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces /repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_toke n_mux.3043647472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_security_escalation.1409936370 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 315664726 ps |
| CPU time | 11.45 seconds |
| Started | Sep 11 08:05:28 AM UTC 24 |
| Finished | Sep 11 08:05:41 AM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409936370 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1409936370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_smoke.1939738427 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 52464125 ps |
| CPU time | 3.6 seconds |
| Started | Sep 11 08:05:20 AM UTC 24 |
| Finished | Sep 11 08:05:24 AM UTC 24 |
| Peak memory | 229848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939738427 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1939738427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_failure.1743819437 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 1036089678 ps |
| CPU time | 30.25 seconds |
| Started | Sep 11 08:05:25 AM UTC 24 |
| Finished | Sep 11 08:05:56 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743819437 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1743819437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_state_post_trans.3520143799 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 61798368 ps |
| CPU time | 13.34 seconds |
| Started | Sep 11 08:05:26 AM UTC 24 |
| Finished | Sep 11 08:05:40 AM UTC 24 |
| Peak memory | 262816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520143799 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3520143799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.2582039044 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 4208678554 ps |
| CPU time | 123.88 seconds |
| Started | Sep 11 08:05:42 AM UTC 24 |
| Finished | Sep 11 08:07:48 AM UTC 24 |
| Peak memory | 295560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=2582039044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null - cm_name 8.lc_ctrl_stress_all.2582039044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/8.lc_ctrl_volatile_unlock_smoke.979429914 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 146888566 ps |
| CPU time | 1.42 seconds |
| Started | Sep 11 08:05:23 AM UTC 24 |
| Finished | Sep 11 08:05:25 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979429914 -a ssert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8 .lc_ctrl_volatile_unlock_smoke.979429914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/8.lc_ctrl_volatile_unlock_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_alert_test.2318260768 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 58301711 ps |
| CPU time | 1.53 seconds |
| Started | Sep 11 08:06:06 AM UTC 24 |
| Finished | Sep 11 08:06:09 AM UTC 24 |
| Peak memory | 218608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318260768 -assert no postproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2318260768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_errors.3532448736 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 321086277 ps |
| CPU time | 18.69 seconds |
| Started | Sep 11 08:05:50 AM UTC 24 |
| Finished | Sep 11 08:06:10 AM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532448736 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3532448736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_access.3112096776 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2312323694 ps |
| CPU time | 9.41 seconds |
| Started | Sep 11 08:05:55 AM UTC 24 |
| Finished | Sep 11 08:06:06 AM UTC 24 |
| Peak memory | 229932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112096776 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3112096776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.476979579 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 8298536126 ps |
| CPU time | 41.09 seconds |
| Started | Sep 11 08:05:53 AM UTC 24 |
| Finished | Sep 11 08:06:36 AM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476979579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j tag_errors.476979579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_priority.736332447 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 479034665 ps |
| CPU time | 9.51 seconds |
| Started | Sep 11 08:05:55 AM UTC 24 |
| Finished | Sep 11 08:06:06 AM UTC 24 |
| Peak memory | 230160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736332447 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_prio rity.736332447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_priority/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_prog_failure.4119614323 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 3575214224 ps |
| CPU time | 12.96 seconds |
| Started | Sep 11 08:05:53 AM UTC 24 |
| Finished | Sep 11 08:06:07 AM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119614323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct rl_jtag_prog_failure.4119614323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2607676606 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 3696896679 ps |
| CPU time | 26.31 seconds |
| Started | Sep 11 08:05:55 AM UTC 24 |
| Finished | Sep 11 08:06:23 AM UTC 24 |
| Peak memory | 229920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607676606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.l c_ctrl_jtag_regwen_during_op.2607676606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_smoke.3538711331 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1401619382 ps |
| CPU time | 12.18 seconds |
| Started | Sep 11 08:05:52 AM UTC 24 |
| Finished | Sep 11 08:06:05 AM UTC 24 |
| Peak memory | 229772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538711331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp aces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag _smoke.3538711331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.1686954684 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4783151570 ps |
| CPU time | 60.2 seconds |
| Started | Sep 11 08:05:52 AM UTC 24 |
| Finished | Sep 11 08:06:54 AM UTC 24 |
| Peak memory | 262764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686954684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_c trl_jtag_state_failure.1686954684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_post_trans.881024443 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 338312737 ps |
| CPU time | 14.64 seconds |
| Started | Sep 11 08:05:52 AM UTC 24 |
| Finished | Sep 11 08:06:08 AM UTC 24 |
| Peak memory | 258820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881024443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc _ctrl_jtag_state_post_trans.881024443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_jtag_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_prog_failure.2042459859 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 46208010 ps |
| CPU time | 2.56 seconds |
| Started | Sep 11 08:05:50 AM UTC 24 |
| Finished | Sep 11 08:05:54 AM UTC 24 |
| Peak memory | 231856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042459859 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2042459859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_prog_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_regwen_during_op.4058398405 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1198513623 ps |
| CPU time | 17.07 seconds |
| Started | Sep 11 08:05:50 AM UTC 24 |
| Finished | Sep 11 08:06:08 AM UTC 24 |
| Peak memory | 229852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058398405 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.4058398405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_regwen_during_op/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_mubi.1201533645 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 2742057793 ps |
| CPU time | 16.91 seconds |
| Started | Sep 11 08:05:56 AM UTC 24 |
| Finished | Sep 11 08:06:14 AM UTC 24 |
| Peak memory | 232296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201533645 -assert nop ostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo /scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1201533645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_digest.439480016 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 429604428 ps |
| CPU time | 18.2 seconds |
| Started | Sep 11 08:05:58 AM UTC 24 |
| Finished | Sep 11 08:06:17 AM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439480016 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac es/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_to ken_digest.439480016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_digest/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_sec_token_mux.180630925 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 235398632 ps |
| CPU time | 7.84 seconds |
| Started | Sep 11 08:05:56 AM UTC 24 |
| Finished | Sep 11 08:06:05 AM UTC 24 |
| Peak memory | 232256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180630925 -assert nopo stproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token _mux.180630925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_sec_token_mux/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_security_escalation.1149626149 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 1711451612 ps |
| CPU time | 18.54 seconds |
| Started | Sep 11 08:05:50 AM UTC 24 |
| Finished | Sep 11 08:06:10 AM UTC 24 |
| Peak memory | 232152 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1149626149 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1149626149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_security_escalation/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_smoke.4095682455 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 141455508 ps |
| CPU time | 2.91 seconds |
| Started | Sep 11 08:05:47 AM UTC 24 |
| Finished | Sep 11 08:05:52 AM UTC 24 |
| Peak memory | 225752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095682455 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.4095682455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_failure.2720649812 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 701023707 ps |
| CPU time | 28.26 seconds |
| Started | Sep 11 08:05:49 AM UTC 24 |
| Finished | Sep 11 08:06:18 AM UTC 24 |
| Peak memory | 262812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720649812 -assert nopostproc +UVM_TESTNAME=lc_ ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2720649812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_failure/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_state_post_trans.849507482 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 138478104 ps |
| CPU time | 15.19 seconds |
| Started | Sep 11 08:05:49 AM UTC 24 |
| Finished | Sep 11 08:06:05 AM UTC 24 |
| Peak memory | 261024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849507482 -assert nopostproc +UVM_TESTNAME=lc_c trl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.849507482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_state_post_trans/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.383576879 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 13197128568 ps |
| CPU time | 138.92 seconds |
| Started | Sep 11 08:05:59 AM UTC 24 |
| Finished | Sep 11 08:08:20 AM UTC 24 |
| Peak memory | 261016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=1000 0000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando m_seed=383576879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -c m_name 9.lc_ctrl_stress_all.383576879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3647777932 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 25142231 ps |
| CPU time | 1.23 seconds |
| Started | Sep 11 08:05:49 AM UTC 24 |
| Finished | Sep 11 08:05:51 AM UTC 24 |
| Peak memory | 220676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647777932 - assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_volatile_unlock_smoke.3647777932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/9.lc_ctrl_volatile_unlock_smoke/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |