| T820 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.2121214670 |
|
|
Sep 11 08:13:12 AM UTC 24 |
Sep 11 08:13:26 AM UTC 24 |
332580986 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.3584606977 |
|
|
Sep 11 08:09:00 AM UTC 24 |
Sep 11 08:13:28 AM UTC 24 |
34093165485 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.2198091604 |
|
|
Sep 11 08:12:51 AM UTC 24 |
Sep 11 08:13:29 AM UTC 24 |
559224624 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/40.lc_ctrl_stress_all.1104106624 |
|
|
Sep 11 08:12:11 AM UTC 24 |
Sep 11 08:13:29 AM UTC 24 |
3717080546 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.4242925249 |
|
|
Sep 11 08:13:28 AM UTC 24 |
Sep 11 08:13:30 AM UTC 24 |
22826024 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1651568941 |
|
|
Sep 11 08:13:29 AM UTC 24 |
Sep 11 08:13:32 AM UTC 24 |
15701328 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.882857537 |
|
|
Sep 11 08:13:21 AM UTC 24 |
Sep 11 08:13:33 AM UTC 24 |
253076944 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_sec_token_digest.1096330123 |
|
|
Sep 11 08:13:15 AM UTC 24 |
Sep 11 08:13:33 AM UTC 24 |
1484152242 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.1335106988 |
|
|
Sep 11 08:13:29 AM UTC 24 |
Sep 11 08:13:35 AM UTC 24 |
125076009 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_jtag_access.3922243756 |
|
|
Sep 11 08:13:24 AM UTC 24 |
Sep 11 08:13:35 AM UTC 24 |
2806065783 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_mux.2437164607 |
|
|
Sep 11 08:13:25 AM UTC 24 |
Sep 11 08:13:36 AM UTC 24 |
1038543600 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_post_trans.2950944266 |
|
|
Sep 11 08:13:32 AM UTC 24 |
Sep 11 08:13:37 AM UTC 24 |
187228379 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_security_escalation.2246912750 |
|
|
Sep 11 08:13:24 AM UTC 24 |
Sep 11 08:13:38 AM UTC 24 |
329986854 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_state_failure.1124972471 |
|
|
Sep 11 08:12:59 AM UTC 24 |
Sep 11 08:13:38 AM UTC 24 |
2833132218 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_state_failure.2803234384 |
|
|
Sep 11 08:13:09 AM UTC 24 |
Sep 11 08:13:39 AM UTC 24 |
314487421 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_prog_failure.4233767525 |
|
|
Sep 11 08:13:34 AM UTC 24 |
Sep 11 08:13:39 AM UTC 24 |
270153245 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_alert_test.489647824 |
|
|
Sep 11 08:13:40 AM UTC 24 |
Sep 11 08:13:42 AM UTC 24 |
57029070 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_errors.834119258 |
|
|
Sep 11 08:13:23 AM UTC 24 |
Sep 11 08:13:43 AM UTC 24 |
1616596785 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_token_digest.2835107904 |
|
|
Sep 11 08:13:25 AM UTC 24 |
Sep 11 08:13:45 AM UTC 24 |
625699501 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_smoke.1657393875 |
|
|
Sep 11 08:13:40 AM UTC 24 |
Sep 11 08:13:46 AM UTC 24 |
77975889 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2556378878 |
|
|
Sep 11 08:13:43 AM UTC 24 |
Sep 11 08:13:46 AM UTC 24 |
24214623 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_errors.2872799205 |
|
|
Sep 11 08:13:11 AM UTC 24 |
Sep 11 08:13:47 AM UTC 24 |
3762477499 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_jtag_access.2991582688 |
|
|
Sep 11 08:13:35 AM UTC 24 |
Sep 11 08:13:49 AM UTC 24 |
7512226988 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3197720214 |
|
|
Sep 11 08:09:47 AM UTC 24 |
Sep 11 08:13:49 AM UTC 24 |
48738039713 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_digest.4260306300 |
|
|
Sep 11 08:13:37 AM UTC 24 |
Sep 11 08:13:50 AM UTC 24 |
473291423 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_sec_mubi.1445224111 |
|
|
Sep 11 08:13:25 AM UTC 24 |
Sep 11 08:13:50 AM UTC 24 |
469450272 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_mubi.2081339126 |
|
|
Sep 11 08:13:36 AM UTC 24 |
Sep 11 08:13:50 AM UTC 24 |
288298075 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_security_escalation.1470412348 |
|
|
Sep 11 08:13:34 AM UTC 24 |
Sep 11 08:13:51 AM UTC 24 |
974061024 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_errors.2017832563 |
|
|
Sep 11 08:13:34 AM UTC 24 |
Sep 11 08:13:51 AM UTC 24 |
260674012 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_prog_failure.1352695472 |
|
|
Sep 11 08:13:46 AM UTC 24 |
Sep 11 08:13:52 AM UTC 24 |
859004588 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.2708144714 |
|
|
Sep 11 08:09:28 AM UTC 24 |
Sep 11 08:13:53 AM UTC 24 |
12060438801 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1594620573 |
|
|
Sep 11 08:11:28 AM UTC 24 |
Sep 11 08:13:54 AM UTC 24 |
7170947414 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_alert_test.3409205995 |
|
|
Sep 11 08:13:53 AM UTC 24 |
Sep 11 08:13:56 AM UTC 24 |
60169787 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_errors.1887613834 |
|
|
Sep 11 08:13:46 AM UTC 24 |
Sep 11 08:13:57 AM UTC 24 |
1085016100 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1313480399 |
|
|
Sep 11 08:11:09 AM UTC 24 |
Sep 11 08:13:57 AM UTC 24 |
4418086147 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_post_trans.2882414893 |
|
|
Sep 11 08:13:46 AM UTC 24 |
Sep 11 08:13:58 AM UTC 24 |
54382678 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_jtag_access.742819310 |
|
|
Sep 11 08:13:50 AM UTC 24 |
Sep 11 08:14:01 AM UTC 24 |
1128829691 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_mux.4264966854 |
|
|
Sep 11 08:13:51 AM UTC 24 |
Sep 11 08:14:01 AM UTC 24 |
720973683 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/47.lc_ctrl_state_failure.3561269576 |
|
|
Sep 11 08:13:21 AM UTC 24 |
Sep 11 08:14:01 AM UTC 24 |
1706873067 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_sec_token_mux.272241846 |
|
|
Sep 11 08:13:37 AM UTC 24 |
Sep 11 08:14:02 AM UTC 24 |
525745804 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_security_escalation.1485459205 |
|
|
Sep 11 08:13:49 AM UTC 24 |
Sep 11 08:14:03 AM UTC 24 |
320343849 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all.760231510 |
|
|
Sep 11 08:11:36 AM UTC 24 |
Sep 11 08:14:05 AM UTC 24 |
20225233576 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_state_failure.902787652 |
|
|
Sep 11 08:13:31 AM UTC 24 |
Sep 11 08:14:06 AM UTC 24 |
794253383 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_token_digest.815445073 |
|
|
Sep 11 08:13:51 AM UTC 24 |
Sep 11 08:14:07 AM UTC 24 |
1112312934 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_sec_mubi.1660464675 |
|
|
Sep 11 08:13:50 AM UTC 24 |
Sep 11 08:14:09 AM UTC 24 |
734723301 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_state_failure.2539376631 |
|
|
Sep 11 08:13:44 AM UTC 24 |
Sep 11 08:14:19 AM UTC 24 |
852758713 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/41.lc_ctrl_stress_all.2916822490 |
|
|
Sep 11 08:12:25 AM UTC 24 |
Sep 11 08:14:27 AM UTC 24 |
12038793377 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/33.lc_ctrl_stress_all.3197925714 |
|
|
Sep 11 08:11:00 AM UTC 24 |
Sep 11 08:14:28 AM UTC 24 |
33382634867 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/48.lc_ctrl_stress_all.782917028 |
|
|
Sep 11 08:13:39 AM UTC 24 |
Sep 11 08:14:32 AM UTC 24 |
4801671264 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all.996084568 |
|
|
Sep 11 08:10:50 AM UTC 24 |
Sep 11 08:14:35 AM UTC 24 |
46159908477 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.3920629907 |
|
|
Sep 11 08:13:16 AM UTC 24 |
Sep 11 08:14:40 AM UTC 24 |
2250733526 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/39.lc_ctrl_stress_all.2584750909 |
|
|
Sep 11 08:12:02 AM UTC 24 |
Sep 11 08:14:43 AM UTC 24 |
5262357499 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/26.lc_ctrl_stress_all.4262675534 |
|
|
Sep 11 08:09:57 AM UTC 24 |
Sep 11 08:15:01 AM UTC 24 |
17328474845 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all.3403799996 |
|
|
Sep 11 08:12:56 AM UTC 24 |
Sep 11 08:15:03 AM UTC 24 |
6595339863 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/45.lc_ctrl_stress_all.3742598452 |
|
|
Sep 11 08:13:07 AM UTC 24 |
Sep 11 08:15:03 AM UTC 24 |
4053456851 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/43.lc_ctrl_stress_all.1923364005 |
|
|
Sep 11 08:12:47 AM UTC 24 |
Sep 11 08:15:19 AM UTC 24 |
18072155201 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/30.lc_ctrl_stress_all.2139709432 |
|
|
Sep 11 08:10:33 AM UTC 24 |
Sep 11 08:15:25 AM UTC 24 |
11121506934 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.578404676 |
|
|
Sep 11 08:12:56 AM UTC 24 |
Sep 11 08:15:34 AM UTC 24 |
2839269611 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.2358138381 |
|
|
Sep 11 08:11:28 AM UTC 24 |
Sep 11 08:15:40 AM UTC 24 |
6961590274 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.3915763060 |
|
|
Sep 11 08:13:52 AM UTC 24 |
Sep 11 08:15:50 AM UTC 24 |
2362021219 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.162961553 |
|
|
Sep 11 08:12:36 AM UTC 24 |
Sep 11 08:15:54 AM UTC 24 |
5167202086 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/46.lc_ctrl_stress_all.3061928704 |
|
|
Sep 11 08:13:16 AM UTC 24 |
Sep 11 08:16:49 AM UTC 24 |
34477938754 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/49.lc_ctrl_stress_all.4107969879 |
|
|
Sep 11 08:13:52 AM UTC 24 |
Sep 11 08:18:54 AM UTC 24 |
62710502429 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.893995863 |
|
|
Sep 11 08:09:41 AM UTC 24 |
Sep 11 08:19:48 AM UTC 24 |
40192247571 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.4249991004 |
|
|
Sep 11 08:10:41 AM UTC 24 |
Sep 11 08:20:17 AM UTC 24 |
91294274400 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/default/29.lc_ctrl_stress_all.2838150834 |
|
|
Sep 11 08:10:25 AM UTC 24 |
Sep 11 08:20:29 AM UTC 24 |
19614156779 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.888841397 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:33 AM UTC 24 |
124403850 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.936648377 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:33 AM UTC 24 |
68223432 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_rw.4214533620 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:34 AM UTC 24 |
39852651 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3995898474 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:34 AM UTC 24 |
72051583 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1913212843 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:34 AM UTC 24 |
46832119 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3558588389 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
25605008 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1474306584 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
102585624 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3848996854 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
238587878 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1438596089 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
201880623 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3598179503 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
243363876 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2716922492 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
301672096 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2344131617 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:35 AM UTC 24 |
110444780 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.71530055 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
585414502 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3330029204 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
795069798 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.478481359 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
1310506367 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2766704489 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
51897912 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1617564041 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
95620907 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1693708004 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
29543105 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3451765603 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
26378461 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2350053595 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:36 AM UTC 24 |
69829182 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1121662091 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:37 AM UTC 24 |
162285716 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.258995548 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:37 AM UTC 24 |
228788815 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1116756591 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:37 AM UTC 24 |
98281127 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2692617812 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:37 AM UTC 24 |
247683064 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1418178476 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
665950501 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_tl_errors.629372049 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
32731680 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.4098491575 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
17726688 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.129994984 |
|
|
Sep 11 10:30:36 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
29119507 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3538755127 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
341069890 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2860506391 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:38 AM UTC 24 |
35928916 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3433234053 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:39 AM UTC 24 |
117894658 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1456972686 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:39 AM UTC 24 |
99592021 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3571546604 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:39 AM UTC 24 |
143305591 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.921088010 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:39 AM UTC 24 |
267138552 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1005386054 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
82380399 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1619563230 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
480250829 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.646340615 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
139271586 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3211234095 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
39274905 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.103490309 |
|
|
Sep 11 10:30:34 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
339143095 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2728871135 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
69796923 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.333899081 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:40 AM UTC 24 |
149667103 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3344335114 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
52149712 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.962717602 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
14634363 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3933177569 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
24851784 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1943031523 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
21346837 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2620537728 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
227124839 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3817734676 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:41 AM UTC 24 |
341160649 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3231154298 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
193007619 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2398674422 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
65268853 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.802140474 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
28041069 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2021288359 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
140190168 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2548421360 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
17479711 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1104797964 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
64311943 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1168018610 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
22742731 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1978291982 |
|
|
Sep 11 10:30:37 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
191164546 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2734802541 |
|
|
Sep 11 10:30:36 AM UTC 24 |
Sep 11 10:30:42 AM UTC 24 |
173284601 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1645233599 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:43 AM UTC 24 |
133249579 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1187373832 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
58102086 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3787194348 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
49916495 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2128903163 |
|
|
Sep 11 10:30:32 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
848032538 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1061669289 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
17019762 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3158544660 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
29848568 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.880595921 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
876868013 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2831801752 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
47363707 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.449850409 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:44 AM UTC 24 |
27034840 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.377754959 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
52766982 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4279762883 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
86666768 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2096719782 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
781803791 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1514413248 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
94695668 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3415939126 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
104601285 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.252726339 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:45 AM UTC 24 |
644529202 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1776983741 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
168753077 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3954293952 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
139358852 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3745309972 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
18531889 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2741501558 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
172229542 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2909144973 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
63931015 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3732784075 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:46 AM UTC 24 |
39140604 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2094837862 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:47 AM UTC 24 |
19564254 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2985036039 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:47 AM UTC 24 |
488490973 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3355861265 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:47 AM UTC 24 |
153900087 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.907075288 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:47 AM UTC 24 |
97720032 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4210768512 |
|
|
Sep 11 10:30:35 AM UTC 24 |
Sep 11 10:30:48 AM UTC 24 |
1969859560 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3325543263 |
|
|
Sep 11 10:30:45 AM UTC 24 |
Sep 11 10:30:48 AM UTC 24 |
21534094 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3738209219 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:48 AM UTC 24 |
75587605 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3028331347 |
|
|
Sep 11 10:30:45 AM UTC 24 |
Sep 11 10:30:48 AM UTC 24 |
40320409 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1077430524 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:49 AM UTC 24 |
61359072 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1699410978 |
|
|
Sep 11 10:30:46 AM UTC 24 |
Sep 11 10:30:49 AM UTC 24 |
49652364 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.915477507 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:49 AM UTC 24 |
14999934 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2568641020 |
|
|
Sep 11 10:30:46 AM UTC 24 |
Sep 11 10:30:49 AM UTC 24 |
178314439 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3243097586 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:49 AM UTC 24 |
85800982 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.600970591 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:50 AM UTC 24 |
233736833 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1237318451 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:50 AM UTC 24 |
87751434 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1276115660 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:31:00 AM UTC 24 |
113868002 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1558506202 |
|
|
Sep 11 10:30:45 AM UTC 24 |
Sep 11 10:30:50 AM UTC 24 |
857181941 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2417710542 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
18095229 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1720603327 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
29220423 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1624575933 |
|
|
Sep 11 10:30:49 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
35020562 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1381024696 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
62612678 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2666198641 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
197156348 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2172103260 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:51 AM UTC 24 |
28351827 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3775696784 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:52 AM UTC 24 |
39870457 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2932491220 |
|
|
Sep 11 10:30:44 AM UTC 24 |
Sep 11 10:30:52 AM UTC 24 |
558445507 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2900080556 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
80900137 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.840660185 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
273195260 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_errors.243865824 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:31:00 AM UTC 24 |
69608576 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4201302912 |
|
|
Sep 11 10:30:30 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
3707121397 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1698628310 |
|
|
Sep 11 10:30:49 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
467470894 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2551794775 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
5942909608 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3165297655 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:53 AM UTC 24 |
15877866 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.960771308 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
183643219 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2332857636 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
1291544611 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.258002472 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
103873511 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1794956010 |
|
|
Sep 11 10:30:45 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
1254220047 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1273624961 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
1076132174 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.1626497769 |
|
|
Sep 11 10:30:41 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
2240450424 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3254114694 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
136153893 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.780875045 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
81127171 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3500204893 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:54 AM UTC 24 |
110143019 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2791326042 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
303088941 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1742775366 |
|
|
Sep 11 10:30:38 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
7566320644 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1579083878 |
|
|
Sep 11 10:30:50 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
642999496 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.220686994 |
|
|
Sep 11 10:30:53 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
35995986 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3071877337 |
|
|
Sep 11 10:30:49 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
352468314 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2349559664 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
67232770 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440543369 |
|
|
Sep 11 10:30:48 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
2160401432 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.408932247 |
|
|
Sep 11 10:30:53 AM UTC 24 |
Sep 11 10:30:55 AM UTC 24 |
37179634 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3978964498 |
|
|
Sep 11 10:30:43 AM UTC 24 |
Sep 11 10:30:56 AM UTC 24 |
951802919 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4269765604 |
|
|
Sep 11 10:30:53 AM UTC 24 |
Sep 11 10:30:56 AM UTC 24 |
30632437 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.855630687 |
|
|
Sep 11 10:30:54 AM UTC 24 |
Sep 11 10:30:56 AM UTC 24 |
44445403 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3051129518 |
|
|
Sep 11 10:30:54 AM UTC 24 |
Sep 11 10:30:56 AM UTC 24 |
33388301 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1119188446 |
|
|
Sep 11 10:30:53 AM UTC 24 |
Sep 11 10:30:56 AM UTC 24 |
297352729 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3453945150 |
|
|
Sep 11 10:30:55 AM UTC 24 |
Sep 11 10:30:57 AM UTC 24 |
24881736 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.354398744 |
|
|
Sep 11 10:30:54 AM UTC 24 |
Sep 11 10:30:57 AM UTC 24 |
30216506 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.687182233 |
|
|
Sep 11 10:30:55 AM UTC 24 |
Sep 11 10:30:57 AM UTC 24 |
125699192 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1266425155 |
|
|
Sep 11 10:30:53 AM UTC 24 |
Sep 11 10:30:57 AM UTC 24 |
141882291 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.650661869 |
|
|
Sep 11 10:30:55 AM UTC 24 |
Sep 11 10:30:58 AM UTC 24 |
22361387 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1073502611 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:30:58 AM UTC 24 |
12021065 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1062510879 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:30:58 AM UTC 24 |
23902855 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2132784033 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
31941487 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1828956347 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
32871966 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_errors.933114489 |
|
|
Sep 11 10:30:54 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
73243927 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_rw.411162486 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
12046740 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.301424822 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
17125294 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1077506277 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
68810230 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3907807942 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
444482388 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.984125849 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
149663708 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2380841179 |
|
|
Sep 11 10:30:40 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
1244818468 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3105983861 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
66640406 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3717857527 |
|
|
Sep 11 10:30:55 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
209446261 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.4273338714 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:30:59 AM UTC 24 |
122662094 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2730483420 |
|
|
Sep 11 10:30:55 AM UTC 24 |
Sep 11 10:31:01 AM UTC 24 |
552794064 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.92372320 |
|
|
Sep 11 10:30:57 AM UTC 24 |
Sep 11 10:31:00 AM UTC 24 |
97727683 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2634767114 |
|
|
Sep 11 10:30:56 AM UTC 24 |
Sep 11 10:31:01 AM UTC 24 |
127799476 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1320375241 |
|
|
Sep 11 10:30:51 AM UTC 24 |
Sep 11 10:31:03 AM UTC 24 |
4404106046 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3990822890 |
|
|
Sep 11 10:30:47 AM UTC 24 |
Sep 11 10:31:05 AM UTC 24 |
1663559185 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2110923022 |
|
|
Sep 11 10:31:23 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
18536243 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_rw.929643394 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
81821219 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2526668811 |
|
|
Sep 11 10:31:23 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
23533993 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2881725775 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
30181648 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2564123442 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
42420244 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_rw.247841832 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
14168003 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.69719530 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:26 AM UTC 24 |
24391732 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.135967429 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
24569783 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2529675229 |
|
|
Sep 11 10:31:23 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
48210861 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2984194345 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
60130683 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4074515598 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
31227234 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2859945694 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
24285786 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1938720429 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
44093339 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.4051478796 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
32085691 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1185476519 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
54854182 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1858417389 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
29563168 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1416218036 |
|
|
Sep 11 10:31:23 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
55704603 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2507777756 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
84082181 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1071432413 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
23228012 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2572136231 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
133537344 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_errors.635712734 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:27 AM UTC 24 |
193578559 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1058197748 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:28 AM UTC 24 |
117674496 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2515655289 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:28 AM UTC 24 |
131168400 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1772683023 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:28 AM UTC 24 |
394237588 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2292480341 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:28 AM UTC 24 |
63118310 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2861928869 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:29 AM UTC 24 |
197768526 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.189387276 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:29 AM UTC 24 |
65294652 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2770783754 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:29 AM UTC 24 |
111474347 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_disabled-sim-vcs/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1209984565 |
|
|
Sep 11 10:31:24 AM UTC 24 |
Sep 11 10:31:29 AM UTC 24 |
1836545954 ps |