LC_CTRL/VOLATILE_UNLOCK_ENABLED Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	lc_ctrl_smoke	6.290s	1.021ms	50	50	100.00
V1	csr_hw_reset	lc_ctrl_csr_hw_reset	1.140s	14.779us	5	5	100.00
V1	csr_rw	lc_ctrl_csr_rw	1.060s	15.882us	20	20	100.00
V1	csr_bit_bash	lc_ctrl_csr_bit_bash	3.180s	91.838us	5	5	100.00
V1	csr_aliasing	lc_ctrl_csr_aliasing	1.720s	164.276us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	lc_ctrl_csr_mem_rw_with_rand_reset	1.840s	23.430us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	lc_ctrl_csr_rw	1.060s	15.882us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	164.276us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	state_post_trans	lc_ctrl_state_post_trans	10.050s	172.796us	50	50	100.00
V2	regwen_during_op	lc_ctrl_regwen_during_op	24.460s	1.437ms	10	10	100.00
V2	rand_wr_claim_transition_if	lc_ctrl_claim_transition_if	0.980s	59.462us	10	10	100.00
V2	lc_prog_failure	lc_ctrl_prog_failure	4.630s	187.965us	50	50	100.00
V2	lc_state_failure	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
V2	lc_errors	lc_ctrl_errors	23.800s	543.058us	50	50	100.00
V2	security_escalation	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_prog_failure	4.630s	187.965us	50	50	100.00
		lc_ctrl_errors	23.800s	543.058us	50	50	100.00
		lc_ctrl_security_escalation	15.380s	825.283us	50	50	100.00
		lc_ctrl_jtag_state_failure	2.177m	8.884ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.810s	842.732us	20	20	100.00
		lc_ctrl_jtag_errors	1.254m	2.982ms	20	20	100.00
V2	jtag_access	lc_ctrl_jtag_smoke	20.980s	3.631ms	20	20	100.00
		lc_ctrl_jtag_state_post_trans	23.900s	3.647ms	20	20	100.00
		lc_ctrl_jtag_prog_failure	21.810s	842.732us	20	20	100.00
		lc_ctrl_jtag_errors	1.254m	2.982ms	20	20	100.00
		lc_ctrl_jtag_access	18.240s	778.206us	50	50	100.00
		lc_ctrl_jtag_regwen_during_op	37.110s	1.292ms	10	10	100.00
		lc_ctrl_jtag_csr_hw_reset	5.700s	237.163us	10	10	100.00
		lc_ctrl_jtag_csr_rw	3.440s	1.766ms	10	10	100.00
		lc_ctrl_jtag_csr_bit_bash	36.020s	1.605ms	10	10	100.00
		lc_ctrl_jtag_csr_aliasing	23.160s	4.433ms	10	10	100.00
		lc_ctrl_jtag_same_csr_outstanding	1.770s	54.663us	10	10	100.00
		lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.590s	684.506us	10	10	100.00
		lc_ctrl_jtag_alert_test	2.140s	63.671us	10	10	100.00
V2	jtag_priority	lc_ctrl_jtag_priority	15.050s	2.337ms	10	10	100.00
V2	lc_ctrl_volatile_unlock	lc_ctrl_volatile_unlock_smoke	1.150s	93.526us	50	50	100.00
V2	stress_all	lc_ctrl_stress_all	10.286m	19.018ms	50	50	100.00
V2	alert_test	lc_ctrl_alert_test	1.530s	56.183us	50	50	100.00
V2	tl_d_oob_addr_access	lc_ctrl_tl_errors	4.340s	109.949us	20	20	100.00
V2	tl_d_illegal_access	lc_ctrl_tl_errors	4.340s	109.949us	20	20	100.00
V2	tl_d_outstanding_access	lc_ctrl_csr_hw_reset	1.140s	14.779us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	15.882us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	164.276us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.780s	54.995us	20	20	100.00
V2	tl_d_partial_access	lc_ctrl_csr_hw_reset	1.140s	14.779us	5	5	100.00
		lc_ctrl_csr_rw	1.060s	15.882us	20	20	100.00
		lc_ctrl_csr_aliasing	1.720s	164.276us	5	5	100.00
		lc_ctrl_same_csr_outstanding	1.780s	54.995us	20	20	100.00
V2		TOTAL			700	700	100.00
V2S	tl_intg_err	lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
		lc_ctrl_tl_intg_err	7.480s	608.697us	20	20	100.00
V2S	sec_cm_bus_integrity	lc_ctrl_tl_intg_err	7.480s	608.697us	20	20	100.00
V2S	sec_cm_transition_config_regwen	lc_ctrl_regwen_during_op	24.460s	1.437ms	10	10	100.00
V2S	sec_cm_manuf_state_sparse	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_transition_ctr_sparse	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_manuf_state_bkgn_chk	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_transition_ctr_bkgn_chk	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_state_config_sparse	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_main_fsm_sparse	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_kmac_fsm_sparse	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_main_fsm_local_esc	lc_ctrl_state_failure	38.110s	1.445ms	50	50	100.00
		lc_ctrl_sec_cm	35.570s	217.764us	5	5	100.00
V2S	sec_cm_main_fsm_global_esc	lc_ctrl_security_escalation	15.380s	825.283us	50	50	100.00
V2S	sec_cm_main_ctrl_flow_consistency	lc_ctrl_state_post_trans	10.050s	172.796us	50	50	100.00
		lc_ctrl_jtag_state_post_trans	23.900s	3.647ms	20	20	100.00
V2S	sec_cm_intersig_mubi	lc_ctrl_sec_mubi	19.810s	896.896us	50	50	100.00
V2S	sec_cm_token_valid_ctrl_mubi	lc_ctrl_sec_mubi	19.810s	896.896us	50	50	100.00
V2S	sec_cm_token_digest	lc_ctrl_sec_token_digest	20.360s	1.623ms	50	50	100.00
V2S	sec_cm_token_mux_ctrl_redun	lc_ctrl_sec_token_mux	15.230s	3.839ms	50	50	100.00
V2S	sec_cm_token_valid_mux_redun	lc_ctrl_sec_token_mux	15.230s	3.839ms	50	50	100.00
V2S		TOTAL			175	175	100.00
V3	stress_all_with_rand_reset	lc_ctrl_stress_all_with_rand_reset	1.947h	192.572ms	24	50	48.00
V3		TOTAL			24	50	48.00
		TOTAL			1004	1030	97.48

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	27	27	27	100.00
V2S	5	5	5	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.22	97.89	95.77	93.31	100.00	98.55	98.76	96.29

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 22 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 22 failures.

    • 0.lc_ctrl_stress_all_with_rand_reset.53902671072383852989656438108529561088839593176663975116217684413483661808349
      Line 5790, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/0.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28730579035 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28730579035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.lc_ctrl_stress_all_with_rand_reset.51584637436590260845342419625279411993668393111722793809127426091528193204294
      Line 21129, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/1.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29899227727 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29899227727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 20 more failures.

• UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:* has 3 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 3 failures.

    • 12.lc_ctrl_stress_all_with_rand_reset.67727822577365094415698055323403503396083127076884800410505131069831051872066
      Line 27119, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/12.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 14137510861 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 14137510861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 18.lc_ctrl_stress_all_with_rand_reset.33952452774929594377502131143105092275249478836372396797194030760098226859594
      Line 15551, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/18.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8578158789 ps: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
        UVM_INFO @ 8578158789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR (cip_base_vseq.sv:554) [lc_ctrl_common_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_state_error fired unexpectedly! has 1 failures:
  • Test lc_ctrl_stress_all_with_rand_reset has 1 failures.

    • 19.lc_ctrl_stress_all_with_rand_reset.20358483259720429886634225592706341621274055989911201694428656181093625944817
      Line 31540, in log /container/opentitan-public/scratch/os_regression/lc_ctrl_volatile_unlock_enabled-sim-vcs/19.lc_ctrl_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 136005535226 ps: (cip_base_vseq.sv:554) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_state_error fired unexpectedly!
        UVM_INFO @ 136005535226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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