Unified Coverage Report :: Module :: prim_clock_inv

Module : prim_clock_inv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_abstract_clock_inv_0/prim_clock_inv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv	0.00			0.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00			0.00				i_dmi_jtag_tap

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_generic.u_impl_generic	0.00			0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_clock_inv

	Total	Covered	Percent
Totals	3	0	0.00
Total Bits	6	0	0.00
Total Bits 0->1	3	0	0.00
Total Bits 1->0	3	0	0.00

Ports	3	0	0.00
Port Bits	6	0	0.00
Port Bits 0->1	3	0	0.00
Port Bits 1->0	3	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
scanmode_i	No	No		No		INPUT
clk_no	No	No		No		OUTPUT