Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

Go up
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 70.00 70.00
gen_alert_tx[1].u_prim_alert_sender 70.00 70.00
gen_alert_tx[2].u_prim_alert_sender 100.00 100.00
lc_ctrl_csr_assert 100.00 100.00
tlul_assert_device 33.33 0.00 0.00 100.00
u_dmi_jtag 0.00 0.00
i_dmi_cdc 0.00 0.00
i_cdc_req 0.00 0.00
u_prim_sync_reqack 0.00 0.00
gen_rz_hs_protocol.ack_sync 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_cdc_rand_delay 0.00 0.00
u_sync_1 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_sync_2 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_rz_hs_protocol.req_sync 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_cdc_rand_delay 0.00 0.00
u_sync_1 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_sync_2 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
i_cdc_resp 0.00 0.00
u_prim_sync_reqack 0.00 0.00
gen_rz_hs_protocol.ack_sync 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_cdc_rand_delay 0.00 0.00
u_sync_1 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_sync_2 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_rz_hs_protocol.req_sync 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_cdc_rand_delay 0.00 0.00
u_sync_1 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_sync_2 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_combined_rstn_sync 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_cdc_rand_delay 0.00 0.00
u_sync_1 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_sync_2 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_rst_mux 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
i_dmi_jtag_tap 0.00 0.00
i_tck_inv 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_scan.i_dft_tck_mux 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_lc_ctrl_fsm 0.00 0.00 0.00 0.00 0.00
subtree...
u_lc_ctrl_kmac_if 0.00 0.00 0.00 0.00 0.00
u_prim_flop_2sync 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_1 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_prim_sync_reqack_data_in 0.00 0.00 0.00 0.00
u_prim_sync_reqack 0.00 0.00 0.00 0.00
gen_nrz_hs_protocol.ack_sync 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_1 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
gen_nrz_hs_protocol.req_sync 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_1 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_state_regs 0.00 0.00 0.00
u_state_flop 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_prim_clock_mux2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_prim_esc_receiver0 0.00 0.00
u_prim_count 0.00 0.00
u_prim_esc_receiver1 0.00 0.00
u_prim_count 0.00 0.00
u_prim_flop_2sync_init 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_1 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_sync_2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_prim_lc_sync 0.00 0.00
gen_buffs[0].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[0].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[0].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[1].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[2].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_buffs[1].gen_bits[3].u_prim_buf 0.00 0.00
u_secure_anchor_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_mubi4_dec 0.00 0.00
gen_bits[0].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[1].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[2].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
gen_bits[3].u_prim_buf 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00
u_prim_rst_n_mux2 0.00 0.00 0.00
gen_generic.u_impl_generic 0.00 0.00 0.00
u_reg 93.73 85.34 90.42 92.89 100.00 100.00
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_chk 100.00 100.00
u_tlul_data_integ_dec 100.00 100.00 100.00
u_data_chk 100.00 100.00
u_claim_transition_if 100.00 100.00
u_claim_transition_if_regwen 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00
u_device_id_0 66.67 66.67
u_device_id_1 66.67 66.67
u_device_id_2 66.67 66.67
u_device_id_3 66.67 66.67
u_device_id_4 66.67 66.67
u_device_id_5 66.67 66.67
u_device_id_6 66.67 66.67
u_device_id_7 66.67 66.67
u_hw_revision0_product_id 0.00 0.00
u_hw_revision0_silicon_creator_id 0.00 0.00
u_hw_revision1_reserved 0.00 0.00
u_hw_revision1_revision_id 0.00 0.00
u_lc_id_state 66.67 66.67
u_lc_state 66.67 66.67
u_lc_transition_cnt 66.67 66.67
u_manuf_state_0 66.67 66.67
u_manuf_state_1 66.67 66.67
u_manuf_state_2 66.67 66.67
u_manuf_state_3 66.67 66.67
u_manuf_state_4 66.67 66.67
u_manuf_state_5 66.67 66.67
u_manuf_state_6 66.67 66.67
u_manuf_state_7 66.67 66.67
u_otp_vendor_test_ctrl 80.00 80.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 50.00 100.00 0.00
u_prim_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_onehot_check 0.00 0.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_err 100.00 100.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00
u_rsp_intg_gen 100.00 100.00 100.00
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
u_data_gen 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00
u_status_bus_integ_error 66.67 66.67
u_status_ext_clock_switched 66.67 66.67
u_status_flash_rma_error 66.67 66.67
u_status_initialized 66.67 66.67
u_status_otp_error 66.67 66.67
u_status_otp_partition_error 66.67 66.67
u_status_ready 66.67 66.67
u_status_state_error 66.67 66.67
u_status_token_error 66.67 66.67
u_status_transition_count_error 66.67 66.67
u_status_transition_error 66.67 66.67
u_status_transition_successful 66.67 66.67
u_transition_cmd 50.00 50.00
u_transition_ctrl_ext_clock_en 60.00 60.00
u_transition_ctrl_volatile_raw_unlock 60.00 60.00
u_transition_regwen 100.00 100.00
u_transition_target 80.00 80.00
u_transition_token_0 80.00 80.00
u_transition_token_1 80.00 80.00
u_transition_token_2 80.00 80.00
u_transition_token_3 80.00 80.00
u_reg_tap 88.60 97.15 84.26 63.19 98.39 100.00
u_alert_test_fatal_bus_integ_error 100.00 100.00
u_alert_test_fatal_prog_error 100.00 100.00
u_alert_test_fatal_state_error 100.00 100.00
u_chk 90.18 100.00 70.54 100.00
u_chk 34.48 34.48
u_tlul_data_integ_dec 100.00 100.00 100.00
u_data_chk 100.00 100.00
u_claim_transition_if 100.00 100.00
u_claim_transition_if_regwen 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00
u_device_id_0 100.00 100.00
u_device_id_1 100.00 100.00
u_device_id_2 100.00 100.00
u_device_id_3 100.00 100.00
u_device_id_4 100.00 100.00
u_device_id_5 100.00 100.00
u_device_id_6 100.00 100.00
u_device_id_7 100.00 100.00
u_hw_revision0_product_id 33.33 33.33
u_hw_revision0_silicon_creator_id 33.33 33.33
u_hw_revision1_reserved 33.33 33.33
u_hw_revision1_revision_id 33.33 33.33
u_lc_id_state 100.00 100.00
u_lc_state 100.00 100.00
u_lc_transition_cnt 100.00 100.00
u_manuf_state_0 100.00 100.00
u_manuf_state_1 100.00 100.00
u_manuf_state_2 100.00 100.00
u_manuf_state_3 100.00 100.00
u_manuf_state_4 100.00 100.00
u_manuf_state_5 100.00 100.00
u_manuf_state_6 100.00 100.00
u_manuf_state_7 100.00 100.00
u_otp_vendor_test_ctrl 100.00 100.00
u_otp_vendor_test_status 100.00 100.00
u_prim_reg_we_check 50.00 100.00 0.00
u_prim_buf 100.00 100.00
gen_generic.u_impl_generic 100.00 100.00
u_prim_onehot_check 0.00 0.00
u_reg_if 97.14 92.19 96.36 100.00 100.00
u_err 97.50 90.00 100.00 100.00 100.00
u_rsp_intg_gen 83.33 66.67 100.00
u_rsp_intg_gen 100.00 100.00 100.00
gen_data_intg.u_tlul_data_integ_enc 100.00 100.00
u_data_gen 100.00 100.00
gen_rsp_intg.u_rsp_gen 100.00 100.00
u_status_bus_integ_error 100.00 100.00
u_status_ext_clock_switched 100.00 100.00
u_status_flash_rma_error 100.00 100.00
u_status_initialized 100.00 100.00
u_status_otp_error 100.00 100.00
u_status_otp_partition_error 100.00 100.00
u_status_ready 100.00 100.00
u_status_state_error 100.00 100.00
u_status_token_error 100.00 100.00
u_status_transition_count_error 100.00 100.00
u_status_transition_error 100.00 100.00
u_status_transition_successful 100.00 100.00
u_transition_cmd 100.00 100.00
u_transition_ctrl_ext_clock_en 100.00 100.00
u_transition_ctrl_volatile_raw_unlock 100.00 100.00
u_transition_regwen 100.00 100.00
u_transition_target 100.00 100.00
u_transition_token_0 100.00 100.00
u_transition_token_1 100.00 100.00
u_transition_token_2 100.00 100.00
u_transition_token_3 100.00 100.00
u_tap_tlul_host 3.77 0.00 0.00 15.09 0.00
u_cmd_intg_gen 0.00 0.00
gen_data_intg.u_data_gen 0.00 0.00
u_cmd_gen 0.00 0.00
u_rsp_chk 5.03 0.00 0.00 15.09
u_chk 15.09 15.09
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%