Unified Coverage Report :: Module :: prim_onehot_check

Module : prim_onehot_check

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_onehot_check_0/rtl/prim_onehot_check.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check	0.00			0.00
tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check	0.00			0.00

---

Module Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_reg_we_check

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_onehot_check

	Total	Covered	Percent
Totals	5	0	0.00
Total Bits	30	0	0.00
Total Bits 0->1	15	0	0.00
Total Bits 1->0	15	0	0.00

Ports	5	0	0.00
Port Bits	30	0	0.00
Port Bits 0->1	15	0	0.00
Port Bits 1->0	15	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
oh_i[0]	No	No		No		INPUT
oh_i[1]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[3:2]	No	No		No		INPUT
oh_i[4]	Unreachable	Unreachable		Unreachable		INPUT
oh_i[12:5]	No	No		No		INPUT
oh_i[34:13]	Unreachable	Unreachable		Unreachable		INPUT
addr_i[5:0]	Unreachable	Unreachable		Unreachable		INPUT
en_i	No	No		No		INPUT
err_o	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_reg.u_prim_reg_we_check.u_prim_onehot_check

Toggle Coverage for Instance : tb.dut.u_reg_tap.u_prim_reg_we_check.u_prim_onehot_check