Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2212600	17754	0	0
claim_transition_if_regwen_rd_A	2212600	1349	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2212600	17754	0	0
T4	6208	67	0	0
T5	1748	142	0	0
T6	9199	907	0	0
T7	854	0	0	0
T8	130405	0	0	0
T9	0	8	0	0
T10	5474	0	0	0
T11	14786	0	0	0
T12	0	74	0	0
T16	0	3	0	0
T18	10090	0	0	0
T19	0	4	0	0
T20	21360	0	0	0
T28	0	856	0	0
T29	50653	0	0	0
T30	0	785	0	0
T31	0	142	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2212600	1349	0	0
T3	2862	10	0	0
T4	6208	0	0	0
T5	1748	0	0	0
T6	9199	0	0	0
T7	854	0	0	0
T8	130405	0	0	0
T10	5474	0	0	0
T11	14786	0	0	0
T18	10090	0	0	0
T19	0	68	0	0
T21	0	2	0	0
T23	0	30	0	0
T27	0	58	0	0
T29	50653	0	0	0
T32	0	19	0	0
T34	0	68	0	0
T40	0	8	0	0
T43	0	1	0	0
T70	0	22	0	0