Unified Coverage Report :: Module :: lc_ctrl_state_transition

Module : lc_ctrl_state_transition

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
TOTAL		67	0	0.00
ALWAYS	52	67	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
53	0	1
54	0	1
55	0	1
63	0	1
66	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
73	0	1
84	0	1
85	0	1
86	0	1
87	0	1
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
96	0	1
97	0	1
98	0	1
99	0	1
100	0	1
101	0	1
102	0	1
103	0	1
104	0	1
105	0	1
106	0	1
107	0	1
108	0	1
109	0	1
118	0	1
119	0	1
120	0	1
121	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
125	0	1
133	0	1
140	0	1
147	0	1
148	0	1
149	0	1
150	0	1
151	0	1
152	0	1
153	0	1
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
163	0	1
164	0	1
165	0	1
166	0	1
167	0	1
168	0	1
172	0	1
175	0	1
180	0	1
201	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : lc_ctrl_state_transition

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Not Covered
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
Branches		59	0	0.00
IF	63	3	0	0.00
IF	73	29	0	0.00
IF	125	27	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt)))
-2-:	66	if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	73	if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	84	case (lc_cnt_i)
-3-:	118	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:

-1-	-2-	-3-	Status	Tests
1	LcCnt0	-	Not Covered
1	LcCnt1	-	Not Covered
1	LcCnt2	-	Not Covered
1	LcCnt3	-	Not Covered
1	LcCnt4	-	Not Covered
1	LcCnt5	-	Not Covered
1	LcCnt6	-	Not Covered
1	LcCnt7	-	Not Covered
1	LcCnt8	-	Not Covered
1	LcCnt9	-	Not Covered
1	LcCnt10	-	Not Covered
1	LcCnt11	-	Not Covered
1	LcCnt12	-	Not Covered
1	LcCnt13	-	Not Covered
1	LcCnt14	-	Not Covered
1	LcCnt15	-	Not Covered
1	LcCnt16	-	Not Covered
1	LcCnt17	-	Not Covered
1	LcCnt18	-	Not Covered
1	LcCnt19	-	Not Covered
1	LcCnt20	-	Not Covered
1	LcCnt21	-	Not Covered
1	LcCnt22	-	Not Covered
1	LcCnt23	-	Not Covered
1	LcCnt24	-	Not Covered
1	default	-	Not Covered
1	-	1	Not Covered
1	-	0	Not Covered
0	-	-	Not Covered

	LineNo.	Expression
-1-:	125	if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	133	if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap)))
-3-:	140	if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)))
-4-:	147	case (trans_target_i)
-5-:	180	case (dec_lc_state_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	-	Not Covered
1	1	1	default	-	Not Covered
1	1	0	-	-	Not Covered
1	0	-	-	-	Not Covered
1	-	-	-	CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	Not Covered
1	-	-	-	default	Not Covered
0	-	-	-	-	Not Covered

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
TOTAL		66	0	0.00
ALWAYS	52	66	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	0	1
53	0	1
54	0	1
55	0	1
63	0	1
66	0	1
68	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
73	0	1
84	0	1
85	0	1
86	0	1
87	0	1
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
96	0	1
97	0	1
98	0	1
99	0	1
100	0	1
101	0	1
102	0	1
103	0	1
104	0	1
105	0	1
106	0	1
107	0	1
108	0	1
109	0	1
			Exclude Annotation: VC_COV_UNR
118	0	1
119	0	1
120	0	1
121	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
125	0	1
133	0	1
140	0	1
147	0	1
148		excluded
			Exclude Annotation: VC_COV_UNR
149	0	1
150	0	1
151	0	1
152	0	1
153	0	1
154	0	1
155	0	1
156	0	1
157	0	1
158	0	1
159	0	1
160	0	1
161	0	1
162	0	1
163	0	1
164	0	1
165	0	1
166	0	1
167	0	1
168	0	1
172	0	1
175	0	1
180	0	1
201	0	1
			Exclude Annotation: VC_COV_UNR
			==> MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Total	Covered	Percent
Conditions	24	0	0.00
Logical	24	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       63
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i && (fsm_state_i == IdleSt))
             -----------1----------    ----------2----------    -----3-----    -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
-	0	1	1	Not Covered
-	1	0	1	Not Covered
-	1	1	0	Not Covered
-	1	1	1	Not Covered

 LINE       63
 SUB-EXPRESSION (fsm_state_i == IdleSt)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       66
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || 
      2  (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}))

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Not Covered
0	1	Not Covered
1	0	Excluded		VC_COV_UNR

 LINE       66
 SUB-EXPRESSION (dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       66
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       118
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}})
            ------------------------------------1-----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       133
 EXPRESSION 
 Number  Term
      1  (dec_lc_state_i[0] <= DecLcStScrap) && 
      2  (trans_target_i[0] <= DecLcStScrap) && 
      3  (dec_lc_state_i[1] <= DecLcStScrap) && 
      4  (trans_target_i[1] <= DecLcStScrap))

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Excluded		VC_COV_UNR
1	0	1	1	Not Covered
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Not Covered
1	1	1	1	Not Covered

 LINE       140
 EXPRESSION 
 Number  Term
      1  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || 
      2  (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       140
 SUB-EXPRESSION (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)
                ---------------------------------------------1---------------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_transition

	Line No.	Total	Covered	Percent
Branches		56	0	0.00
IF	63	3	0	0.00
IF	73	28	0	0.00
IF	125	25	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_state_transition.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	63	if ((((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i) && (fsm_state_i == IdleSt)))
-2-:	66	if (((dec_lc_state_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}) || (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})))

Branches:

-1-	-2-	Status	Tests
1	1	Not Covered
1	0	Not Covered
0	-	Not Covered

	LineNo.	Expression
-1-:	73	if ((fsm_state_i inside {CntIncrSt, CntProgSt, TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	84	case (lc_cnt_i)
-3-:	118	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}))

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	LcCnt0	-	Not Covered
1	LcCnt1	-	Not Covered
1	LcCnt2	-	Not Covered
1	LcCnt3	-	Not Covered
1	LcCnt4	-	Not Covered
1	LcCnt5	-	Not Covered
1	LcCnt6	-	Not Covered
1	LcCnt7	-	Not Covered
1	LcCnt8	-	Not Covered
1	LcCnt9	-	Not Covered
1	LcCnt10	-	Not Covered
1	LcCnt11	-	Not Covered
1	LcCnt12	-	Not Covered
1	LcCnt13	-	Not Covered
1	LcCnt14	-	Not Covered
1	LcCnt15	-	Not Covered
1	LcCnt16	-	Not Covered
1	LcCnt17	-	Not Covered
1	LcCnt18	-	Not Covered
1	LcCnt19	-	Not Covered
1	LcCnt20	-	Not Covered
1	LcCnt21	-	Not Covered
1	LcCnt22	-	Not Covered
1	LcCnt23	-	Not Covered
1	LcCnt24	-	Not Covered
1	default	-	Excluded		VC_COV_UNR
1	-	1	Not Covered
1	-	0	Not Covered
0	-	-	Not Covered

	LineNo.	Expression
-1-:	125	if ((fsm_state_i inside {TransCheckSt, TokenCheck0St, TokenCheck1St, TransProgSt}))
-2-:	133	if (((((dec_lc_state_i[0] <= DecLcStScrap) && (trans_target_i[0] <= DecLcStScrap)) && (dec_lc_state_i[1] <= DecLcStScrap)) && (trans_target_i[1] <= DecLcStScrap)))
-3-:	140	if (((lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[0]][trans_target_i[0]] != InvalidTokenIdx) || (lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_i[1]][trans_target_i[1]] != InvalidTokenIdx)))
-4-:	147	case (trans_target_i)
-5-:	180	case (dec_lc_state_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests	Exclude Annotation
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}}	-	Excluded		VC_COV_UNR
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}	-	Not Covered
1	1	1	{lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	-	Not Covered
1	1	1	default	-	Not Covered
1	1	0	-	-	Not Covered
1	0	-	-	-	Not Covered
1	-	-	-	CASEITEM-1: {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRaw}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked0}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked1}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked2}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked3}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked4}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked5}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestLocked6}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked7}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStDev}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStProdEnd}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}} {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStScrap}}	Not Covered
1	-	-	-	default	Excluded		VC_COV_UNR
0	-	-	-	-	Not Covered