Unified Coverage Report :: Module :: lc_ctrl_fsm

Module : lc_ctrl_fsm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm	0.00	0.00	0.00		0.00	0.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00		0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_syncs[0].u_prim_lc_sync_flash_rma_ack	0.00	0.00				0.00
gen_syncs[1].u_prim_lc_sync_flash_rma_ack	0.00	0.00				0.00
u_cnt_regs	0.00	0.00				0.00
u_fsm_state_regs	0.00	0.00				0.00
u_lc_ctrl_fsm_cov_if	0.00	0.00	0.00			0.00
u_lc_ctrl_signal_decode	0.00	0.00				0.00
u_lc_ctrl_state_decode	0.00	0.00	0.00			0.00
u_lc_ctrl_state_transition	0.00	0.00	0.00			0.00
u_prim_lc_sender_check_byp_en	0.00	0.00				0.00
u_prim_lc_sender_clk_byp_req	0.00	0.00				0.00
u_prim_lc_sender_flash_rma_req	0.00	0.00				0.00
u_prim_lc_sync_clk_byp_ack	0.00	0.00				0.00
u_prim_lc_sync_flash_rma_ack_buf	0.00	0.00
u_prim_lc_sync_rma_token_valid	0.00	0.00
u_prim_lc_sync_test_token_valid	0.00	0.00
u_state_regs	0.00	0.00				0.00

Line Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		179	0	0.00
CONT_ASSIGN	126	1	0	0.00
ALWAYS	146	3	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	179	1	0	0.00
ALWAYS	204	114	0	0.00
ALWAYS	584	3	0	0.00
ALWAYS	585	3	0	0.00
ALWAYS	586	3	0	0.00
ALWAYS	589	3	0	0.00
ALWAYS	608	5	0	0.00
CONT_ASSIGN	619	1	0	0.00
CONT_ASSIGN	666	1	0	0.00
CONT_ASSIGN	667	1	0	0.00
CONT_ASSIGN	668	1	0	0.00
ALWAYS	677	15	0	0.00
ALWAYS	712	14	0	0.00
CONT_ASSIGN	732	1	0	0.00
CONT_ASSIGN	736	1	0	0.00
CONT_ASSIGN	740	1	0	0.00
CONT_ASSIGN	742	1	0	0.00
CONT_ASSIGN	749	1	0	0.00
ALWAYS	882	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	0	1
146	0	1
147	0	1
148	0	1
171	0	1
178	0	1
179	0	1
204	0	1
205	0	1
206	0	1
209	0	1
210	0	1
213	0	1
216	0	1
217	0	1
218	0	1
219	0	1
220	0	1
223	0	1
224	0	1
231	0	1
232	0	1
238	0	1
239	0	1
240	0	1
242	0	1
247	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
254	0	1
255	0	1
			==> MISSING_ELSE
263	0	1
273	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
284	0	1
285	0	1
293	0	1
295	0	1
299	0	1
301	0	1
305	0	1
309	0	1
312	0	1
314	0	1
316	0	1
317	0	1
321	0	1
326	0	1
327	0	1
			==> MISSING_ELSE
333	0	1
350	0	1
351	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
364	0	1
365	0	1
382	0	1
383	0	1
384	0	1
385	0	1
			==> MISSING_ELSE
388	0	1
391	0	1
398	0	1
399	0	1
401	0	1
407	0	1
411	0	1
412	0	1
413	0	1
			==> MISSING_ELSE
418	0	1
419	0	1
420	0	1
421	0	1
423	0	1
			==> MISSING_ELSE
431	0	1
432	0	1
434	0	1
445	0	1
446	0	1
452	0	1
455	0	1
457	0	1
458	0	1
			==> MISSING_ELSE
466	0	1
467	0	1
468	0	1
469	0	1
			==> MISSING_ELSE
472	0	1
482	0	1
483	0	1
487	0	1
493	0	1
496	0	1
499	0	1
501	0	1
504	0	1
505	0	1
509	0	1
510	0	1
520	0	1
524	0	1
525	0	1
526	0	1
529	0	1
533	0	1
534	0	1
535	0	1
536	0	1
537	0	1
538	0	1
			==> MISSING_ELSE
544	0	1
549	0	1
554	0	1
555	0	1
567	0	1
568	0	1
574	0	1
575	0	1
576	0	1
			==> MISSING_ELSE
584	0	3
585	0	3
586	0	3
589	0	1
590	0	1
592	0	1
608	0	1
609	0	1
610	0	1
612	0	1
615	0	1
619	0	1
666	0	1
667	0	1
668	0	1
677	0	1
679	0	1
681	0	1
684	0	1
685	0	1
			==> MISSING_ELSE
687	0	1
688	0	1
			==> MISSING_ELSE
691	0	1
692	0	1
			==> MISSING_ELSE
694	0	1
695	0	1
			==> MISSING_ELSE
698	0	1
699	0	1
			==> MISSING_ELSE
701	0	1
702	0	1
			==> MISSING_ELSE
712	0	1
713	0	1
714	0	1
715	0	1
716	0	1
717	0	1
718	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
732	0	1
736	0	1
740	0	1
742	0	1
749	0	1
882	0	3

---

Cond Coverage for Module : lc_ctrl_fsm

	Total	Covered	Percent
Conditions	92	0	0.00
Logical	92	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       293
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Not Covered
-	1	0	Not Covered
-	1	1	Not Covered

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       612
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Not Covered

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Not Covered

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Module : lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	0	0.00	(Not included in score)
Transitions	47	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Not Covered
CntIncrSt	385	Not Covered
CntProgSt	401	Not Covered
EscalateSt	568	Not Covered
FlashRmaSt	455	Not Covered
IdleSt	252	Not Covered
InvalidSt	575	Not Covered
PostTransSt	317	Not Covered
ResetSt	246	Not Covered
ScrapSt	285	Not Covered
TokenCheck0St	469	Not Covered
TokenCheck1St	501	Not Covered
TokenHashSt	434	Not Covered
TransCheckSt	423	Not Covered
TransProgSt	499	Not Covered

transitions	Line No.	Covered	Tests
ClkMuxSt->CntIncrSt	385	Not Covered
ClkMuxSt->EscalateSt	568	Not Covered
ClkMuxSt->InvalidSt	575	Not Covered
CntIncrSt->CntProgSt	401	Not Covered
CntIncrSt->EscalateSt	568	Not Covered
CntIncrSt->InvalidSt	575	Not Covered
CntIncrSt->PostTransSt	399	Not Covered
CntProgSt->EscalateSt	568	Not Covered
CntProgSt->InvalidSt	575	Not Covered
CntProgSt->PostTransSt	412	Not Covered
CntProgSt->TransCheckSt	423	Not Covered
EscalateSt->InvalidSt	575	Not Covered
FlashRmaSt->EscalateSt	568	Not Covered
FlashRmaSt->InvalidSt	575	Not Covered
FlashRmaSt->TokenCheck0St	469	Not Covered
IdleSt->ClkMuxSt	327	Not Covered
IdleSt->EscalateSt	568	Not Covered
IdleSt->InvalidSt	575	Not Covered
IdleSt->PostTransSt	317	Not Covered
IdleSt->ScrapSt	285	Not Covered
InvalidSt->EscalateSt	568	Not Covered
PostTransSt->EscalateSt	568	Not Covered
PostTransSt->InvalidSt	575	Not Covered
ResetSt->EscalateSt	568	Not Covered
ResetSt->IdleSt	252	Not Covered
ResetSt->InvalidSt	575	Not Covered
ScrapSt->EscalateSt	568	Not Covered
ScrapSt->InvalidSt	575	Not Covered
TokenCheck0St->EscalateSt	568	Not Covered
TokenCheck0St->InvalidSt	575	Not Covered
TokenCheck0St->PostTransSt	483	Not Covered
TokenCheck0St->TokenCheck1St	501	Not Covered
TokenCheck1St->EscalateSt	568	Not Covered
TokenCheck1St->InvalidSt	575	Not Covered
TokenCheck1St->PostTransSt	483	Not Covered
TokenCheck1St->TransProgSt	499	Not Covered
TokenHashSt->EscalateSt	568	Not Covered
TokenHashSt->FlashRmaSt	455	Not Covered
TokenHashSt->InvalidSt	575	Not Covered
TokenHashSt->PostTransSt	457	Not Covered
TransCheckSt->EscalateSt	568	Not Covered
TransCheckSt->InvalidSt	575	Not Covered
TransCheckSt->PostTransSt	432	Not Covered
TransCheckSt->TokenHashSt	434	Not Covered
TransProgSt->EscalateSt	568	Not Covered
TransProgSt->InvalidSt	575	Not Covered
TransProgSt->PostTransSt	525	Not Covered

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	0	0.00	(Not included in score)
Transitions	1	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	295	Not Covered
LcStRma	333	Not Covered
LcStScrap	284	Not Covered
LcStTestLocked0	333	Not Covered
LcStTestLocked1	333	Not Covered
LcStTestLocked2	333	Not Covered
LcStTestLocked3	333	Not Covered
LcStTestLocked4	333	Not Covered
LcStTestLocked5	333	Not Covered
LcStTestLocked6	333	Not Covered
LcStTestUnlocked0	301	Not Covered
LcStTestUnlocked1	333	Not Covered
LcStTestUnlocked2	333	Not Covered
LcStTestUnlocked3	333	Not Covered
LcStTestUnlocked4	333	Not Covered
LcStTestUnlocked5	333	Not Covered
LcStTestUnlocked6	333	Not Covered
LcStTestUnlocked7	333	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Not Covered

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	0	0.00	(Not included in score)
Transitions	1	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Not Covered
LcCnt1	305	Not Covered
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Not Covered
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Not Covered
LcCnt4	106	Not Covered
LcCnt5	107	Not Covered
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Not Covered

---

Branch Coverage for Module : lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		75	0	0.00
TERNARY	732	1	0	0.00
TERNARY	736	1	0	0.00
CASE	242	46	0	0.00
IF	567	3	0	0.00
IF	584	2	0	0.00
IF	585	2	0	0.00
IF	586	2	0	0.00
IF	589	2	0	0.00
IF	684	2	0	0.00
IF	687	2	0	0.00
IF	691	2	0	0.00
IF	694	2	0	0.00
IF	698	2	0	0.00
IF	701	2	0	0.00
IF	882	2	0	0.00
IF	608	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	732	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	736	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	242	case (fsm_state_q)
-2-:	251	if ((init_req_i && lc_state_valid_q))
-3-:	273	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	284	if ((lc_state_q == LcStScrap))
-5-:	293	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	295	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	299	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	305	((lc_cnt_q == LcCnt0)) ? 
-9-:	326	if (trans_cmd_i)
-10-:	333	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	350	if (use_ext_clock_i)
-12-:	365	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	382	if (use_ext_clock_i)
-14-:	384	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	398	if (trans_cnt_oflw_error_o)
-16-:	411	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	418	if (otp_prog_ack_i)
-18-:	419	if (otp_prog_err_i)
-19-:	431	if (trans_invalid_error_o)
-20-:	446	if (token_hash_ack_i)
-21-:	452	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	466	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	468	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[0]))
-24-:	482	if (trans_invalid_error_o)
-25-:	487	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))))
-26-:	493	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	496	if ((fsm_state_q == TokenCheck1St))
-28-:	524	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	529	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))))
-30-:	535	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Not Covered
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	567	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	574	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	584	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	585	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	586	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	589	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	684	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	687	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	691	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	694	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	698	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	701	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	882	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	608	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
TOTAL		177	0	0.00
CONT_ASSIGN	126	1	0	0.00
ALWAYS	146	3	0	0.00
CONT_ASSIGN	171	1	0	0.00
CONT_ASSIGN	178	1	0	0.00
CONT_ASSIGN	179	1	0	0.00
ALWAYS	204	112	0	0.00
ALWAYS	584	3	0	0.00
ALWAYS	585	3	0	0.00
ALWAYS	586	3	0	0.00
ALWAYS	589	3	0	0.00
ALWAYS	608	5	0	0.00
CONT_ASSIGN	619	1	0	0.00
CONT_ASSIGN	666	1	0	0.00
CONT_ASSIGN	667	1	0	0.00
CONT_ASSIGN	668	1	0	0.00
ALWAYS	677	15	0	0.00
ALWAYS	712	14	0	0.00
CONT_ASSIGN	732	1	0	0.00
CONT_ASSIGN	736	1	0	0.00
CONT_ASSIGN	740	1	0	0.00
CONT_ASSIGN	742	1	0	0.00
CONT_ASSIGN	749	1	0	0.00
ALWAYS	882	3	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
126	0	1
146	0	1
147	0	1
148	0	1
171	0	1
178	0	1
179	0	1
204	0	1
205	0	1
206	0	1
209	0	1
210	0	1
213	0	1
216	0	1
217	0	1
218	0	1
219	0	1
220	0	1
223	0	1
224	0	1
231	0	1
232	0	1
238	0	1
239	0	1
240	0	1
242	0	1
247	0	1
248	0	1
249	0	1
250	0	1
251	0	1
252	0	1
254	0	1
255	0	1
			==> MISSING_ELSE
263	0	1
273	0	1
277	0	1
278	0	1
			==> MISSING_ELSE
284	0	1
285	0	1
293	0	1
295	0	1
299	0	1
301	0	1
305	0	1
309	0	1
312	0	1
314	0	1
316		excluded
			Exclude Annotation: VC_COV_UNR
317		excluded
			Exclude Annotation: VC_COV_UNR
321	0	1
326	0	1
327	0	1
			==> MISSING_ELSE
333	0	1
350	0	1
351	0	1
			==> MISSING_ELSE
			==> MISSING_ELSE
364	0	1
365	0	1
382	0	1
383	0	1
384	0	1
385	0	1
			==> MISSING_ELSE
388	0	1
391	0	1
398	0	1
399	0	1
401	0	1
407	0	1
411	0	1
412	0	1
413	0	1
			==> MISSING_ELSE
418	0	1
419	0	1
420	0	1
421	0	1
423	0	1
			==> MISSING_ELSE
431	0	1
432	0	1
434	0	1
445	0	1
446	0	1
452	0	1
455	0	1
457	0	1
458	0	1
			==> MISSING_ELSE
466	0	1
467	0	1
468	0	1
469	0	1
			==> MISSING_ELSE
472	0	1
482	0	1
483	0	1
487	0	1
493	0	1
496	0	1
499	0	1
501	0	1
504	0	1
505	0	1
509	0	1
510	0	1
520	0	1
524	0	1
525	0	1
526	0	1
529	0	1
533	0	1
534	0	1
535	0	1
536	0	1
537	0	1
538	0	1
			==> MISSING_ELSE
544	0	1
549	0	1
554	0	1
555	0	1
567	0	1
568	0	1
574	0	1
575	0	1
576	0	1
			==> MISSING_ELSE
584	0	3
585	0	3
586	0	3
589	0	1
590	0	1
592	0	1
608	0	1
609	0	1
610	0	1
612	0	1
615	0	1
619	0	1
666	0	1
667	0	1
668	0	1
677	0	1
679	0	1
681	0	1
684	0	1
685	0	1
			==> MISSING_ELSE
687	0	1
688	0	1
			==> MISSING_ELSE
691	0	1
692	0	1
			==> MISSING_ELSE
694	0	1
695	0	1
			==> MISSING_ELSE
698	0	1
699	0	1
			==> MISSING_ELSE
701	0	1
702	0	1
			==> MISSING_ELSE
712	0	1
713	0	1
714	0	1
715	0	1
716	0	1
717	0	1
718	0	1
720	0	1
721	0	1
722	0	1
723	0	1
724	0	1
725	0	1
726	0	1
732	0	1
736	0	1
740	0	1
742	0	1
749	0	1
882	0	3

---

Cond Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Total	Covered	Percent
Conditions	86	0	0.00
Logical	86	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       251
 EXPRESSION (init_req_i && lc_state_valid_q)
             -----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       284
 EXPRESSION (lc_state_q == LcStScrap)
            ------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       293
 EXPRESSION (SecVolatileRawUnlockEn && volatile_raw_unlock_i && trans_cmd_i)
             -----------1----------    ----------2----------    -----3-----

-1-	-2-	-3-	Status	Tests
-	0	1	Not Covered
-	1	0	Not Covered
-	1	1	Not Covered

 LINE       295
 EXPRESSION ((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}}) && ((!trans_invalid_error_o)))
             -----------1-----------    ----------------------------------------2---------------------------------------    -------------3------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Not Covered

 LINE       295
 SUB-EXPRESSION (lc_state_q == LcStRaw)
                -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       295
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})
                ----------------------------------------1---------------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       299
 EXPRESSION (unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed)
            ----------------------------------1---------------------------------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Not Covered

 LINE       305
 EXPRESSION ((lc_cnt_q == LcCnt0) ? LcCnt1 : lc_cnt_q)
             ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Not Covered
1	Excluded		VC_COV_UNR

 LINE       305
 SUB-EXPRESSION (lc_cnt_q == LcCnt0)
                ----------1---------

-1-	Status	Tests	Exclude Annotation
0	Not Covered
1	Excluded		VC_COV_UNR

 LINE       411
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[1])
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       452
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       452
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       466
 EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
            -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       493
 EXPRESSION ((hashed_token_i == hashed_token_mux) && ((!token_hash_err_i)) && ((&hashed_token_valid_mux)))
             ------------------1-----------------    ----------2----------    -------------3-------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       493
 SUB-EXPRESSION (hashed_token_i == hashed_token_mux)
                ------------------1-----------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       496
 EXPRESSION (fsm_state_q == TokenCheck1St)
            ---------------1--------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       524
 EXPRESSION (lc_clk_byp_req_o != lc_clk_byp_ack[2])
            -------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 EXPRESSION 
 Number  Term
      1  ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || 
      2  ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))))

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION ((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off)))
                 -----------------------------------1----------------------------------    --------------------------------2--------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       529
 SUB-EXPRESSION (trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))
                 -------------1-------------    ----------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != Off)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != Off)
                ----------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))
                 -----------------------------------1----------------------------------    -------------------------------2-------------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       529
 SUB-EXPRESSION (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}})
                -----------------------------------1----------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On))
                 -------------1------------    ---------------2---------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_req_o != On)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       529
 SUB-EXPRESSION (lc_flash_rma_ack_buf[2] != On)
                ---------------1---------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       567
 EXPRESSION (esc_scrap_state0_i || esc_scrap_state1_i)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       574
 EXPRESSION ((((|state_invalid_error)) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt))
             -----------------------1-----------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       574
 SUB-EXPRESSION (((|state_invalid_error)) | token_if_fsm_err_i)
                 ------------1-----------   ---------2--------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       574
 SUB-EXPRESSION (fsm_state_q != EscalateSt)
                -------------1-------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       612
 SUB-EXPRESSION (set_strap_en_override || gen_strap_delay_regs.strap_en_override_q[0])
                 ----------1----------    ---------------------2---------------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       732
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[0]][trans_target_i[0]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       732
 SUB-EXPRESSION ((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Not Covered

 LINE       736
 EXPRESSION 
 Number  Term
      1  ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates)) ? lc_ctrl_pkg::TransTokenIdxMatrix[dec_lc_state_o[1]][trans_target_i[1]] : InvalidTokenIdx)

-1-	Status	Tests
0	Unreachable
1	Not Covered

 LINE       736
 SUB-EXPRESSION ((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))
                 -----------------------------1----------------------------    -----------------------------2----------------------------

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Unreachable
1	1	Not Covered

 LINE       749
 EXPRESSION (trans_invalid_error || (token_idx0 != token_idx1))
             ---------1---------    -------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       749
 SUB-EXPRESSION (token_idx0 != token_idx1)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

FSM Coverage for Instance : tb.dut.u_lc_ctrl_fsm

Summary for FSM :: fsm_state_q

	Total	Covered	Percent
States	15	0	0.00	(Not included in score)
Transitions	35	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: fsm_state_q

---

states	Line No.	Covered	Tests
ClkMuxSt	327	Not Covered
CntIncrSt	385	Not Covered
CntProgSt	401	Not Covered
EscalateSt	568	Not Covered
FlashRmaSt	455	Not Covered
IdleSt	252	Not Covered
InvalidSt	575	Not Covered
PostTransSt	317	Not Covered
ResetSt	246	Not Covered
ScrapSt	285	Not Covered
TokenCheck0St	469	Not Covered
TokenCheck1St	501	Not Covered
TokenHashSt	434	Not Covered
TransCheckSt	423	Not Covered
TransProgSt	499	Not Covered

transitions	Line No.	Covered	Tests	Exclude Annotation
ClkMuxSt->CntIncrSt	385	Not Covered
ClkMuxSt->EscalateSt	568	Not Covered
ClkMuxSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->CntProgSt	401	Not Covered
CntIncrSt->EscalateSt	568	Not Covered
CntIncrSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntIncrSt->PostTransSt	399	Not Covered
CntProgSt->EscalateSt	568	Not Covered
CntProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
CntProgSt->PostTransSt	412	Not Covered
CntProgSt->TransCheckSt	423	Not Covered
EscalateSt->InvalidSt	575	Excluded		VC_COV_UNR
FlashRmaSt->EscalateSt	568	Not Covered
FlashRmaSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
FlashRmaSt->TokenCheck0St	469	Not Covered
IdleSt->ClkMuxSt	327	Not Covered
IdleSt->EscalateSt	568	Not Covered
IdleSt->InvalidSt	575	Not Covered
IdleSt->PostTransSt	317	Not Covered
IdleSt->ScrapSt	285	Not Covered
InvalidSt->EscalateSt	568	Not Covered
PostTransSt->EscalateSt	568	Not Covered
PostTransSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ResetSt->EscalateSt	568	Not Covered
ResetSt->IdleSt	252	Not Covered
ResetSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
ScrapSt->EscalateSt	568	Not Covered
ScrapSt->InvalidSt	575	Not Covered
TokenCheck0St->EscalateSt	568	Not Covered
TokenCheck0St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck0St->PostTransSt	483	Not Covered
TokenCheck0St->TokenCheck1St	501	Not Covered
TokenCheck1St->EscalateSt	568	Not Covered
TokenCheck1St->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenCheck1St->PostTransSt	483	Not Covered
TokenCheck1St->TransProgSt	499	Not Covered
TokenHashSt->EscalateSt	568	Not Covered
TokenHashSt->FlashRmaSt	455	Not Covered
TokenHashSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TokenHashSt->PostTransSt	457	Not Covered
TransCheckSt->EscalateSt	568	Not Covered
TransCheckSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransCheckSt->PostTransSt	432	Not Covered
TransCheckSt->TokenHashSt	434	Not Covered
TransProgSt->EscalateSt	568	Not Covered
TransProgSt->InvalidSt	575	Excluded		[LOW_RISK] The transition from any state to error_terminal state is fully verified in FPV.
TransProgSt->PostTransSt	525	Not Covered

Summary for FSM :: lc_state_q

	Total	Covered	Percent
States	21	0	0.00	(Not included in score)
Transitions	1	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_state_q

---

states	Line No.	Covered	Tests
LcStDev	92	Not Covered
LcStProd	93	Not Covered
LcStProdEnd	94	Not Covered
LcStRaw	295	Not Covered
LcStRma	333	Not Covered
LcStScrap	284	Not Covered
LcStTestLocked0	333	Not Covered
LcStTestLocked1	333	Not Covered
LcStTestLocked2	333	Not Covered
LcStTestLocked3	333	Not Covered
LcStTestLocked4	333	Not Covered
LcStTestLocked5	333	Not Covered
LcStTestLocked6	333	Not Covered
LcStTestUnlocked0	301	Not Covered
LcStTestUnlocked1	333	Not Covered
LcStTestUnlocked2	333	Not Covered
LcStTestUnlocked3	333	Not Covered
LcStTestUnlocked4	333	Not Covered
LcStTestUnlocked5	333	Not Covered
LcStTestUnlocked6	333	Not Covered
LcStTestUnlocked7	333	Not Covered

transitions	Line No.	Covered	Tests
LcStRaw->LcStTestUnlocked0	301	Not Covered

Summary for FSM :: lc_cnt_q

	Total	Covered	Percent
States	25	0	0.00	(Not included in score)
Transitions	1	0	0.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: lc_cnt_q

---

states	Line No.	Covered	Tests
LcCnt0	305	Not Covered
LcCnt1	305	Not Covered
LcCnt10	112	Not Covered
LcCnt11	113	Not Covered
LcCnt12	114	Not Covered
LcCnt13	115	Not Covered
LcCnt14	116	Not Covered
LcCnt15	117	Not Covered
LcCnt16	118	Not Covered
LcCnt17	119	Not Covered
LcCnt18	120	Not Covered
LcCnt19	121	Not Covered
LcCnt2	104	Not Covered
LcCnt20	122	Not Covered
LcCnt21	123	Not Covered
LcCnt22	124	Not Covered
LcCnt23	125	Not Covered
LcCnt24	126	Not Covered
LcCnt3	105	Not Covered
LcCnt4	106	Not Covered
LcCnt5	107	Not Covered
LcCnt6	108	Not Covered
LcCnt7	109	Not Covered
LcCnt8	110	Not Covered
LcCnt9	111	Not Covered

transitions	Line No.	Covered	Tests
LcCnt0->LcCnt1	305	Not Covered

---

Branch Coverage for Instance : tb.dut.u_lc_ctrl_fsm

	Line No.	Total	Covered	Percent
Branches		73	0	0.00
TERNARY	732	1	0	0.00
TERNARY	736	1	0	0.00
CASE	242	44	0	0.00
IF	567	3	0	0.00
IF	584	2	0	0.00
IF	585	2	0	0.00
IF	586	2	0	0.00
IF	589	2	0	0.00
IF	684	2	0	0.00
IF	687	2	0	0.00
IF	691	2	0	0.00
IF	694	2	0	0.00
IF	698	2	0	0.00
IF	701	2	0	0.00
IF	882	2	0	0.00
IF	608	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv' or '../src/lowrisc_ip_lc_ctrl_0.1/rtl/lc_ctrl_fsm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	732	(((int'(dec_lc_state_o[0]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[0]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	736	(((int'(dec_lc_state_o[1]) < lc_ctrl_state_pkg::NumLcStates) && (int'(trans_target_i[1]) < lc_ctrl_state_pkg::NumLcStates))) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Unreachable

	LineNo.	Expression
-1-:	242	case (fsm_state_q)
-2-:	251	if ((init_req_i && lc_state_valid_q))
-3-:	273	if (((!((SecVolatileRawUnlockEn && (lc_state_q == LcStTestUnlocked0)) && (lc_cnt_q != LcCnt0))) || prim_mubi_pkg::mubi8_test_false_loose(volatile_raw_unlock_success_q)))
-4-:	284	if ((lc_state_q == LcStScrap))
-5-:	293	if (((SecVolatileRawUnlockEn && volatile_raw_unlock_i) && trans_cmd_i))
-6-:	295	if ((((lc_state_q == LcStRaw) && (trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStTestUnlocked0}})) && (!trans_invalid_error_o)))
-7-:	299	if ((unhashed_token_i == lc_ctrl_state_pkg::RndCnstRawUnlockTokenHashed))
-8-:	305	((lc_cnt_q == LcCnt0)) ? 
-9-:	326	if (trans_cmd_i)
-10-:	333	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-11-:	350	if (use_ext_clock_i)
-12-:	365	if ((lc_state_q inside {LcStRaw, LcStTestLocked0, LcStTestLocked1, LcStTestLocked2, LcStTestLocked3, LcStTestLocked4, LcStTestLocked5, LcStTestLocked6, LcStTestUnlocked0, LcStTestUnlocked1, LcStTestUnlocked2, LcStTestUnlocked3, LcStTestUnlocked4, LcStTestUnlocked5, LcStTestUnlocked6, LcStTestUnlocked7, LcStRma}))
-13-:	382	if (use_ext_clock_i)
-14-:	384	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_clk_byp_ack[0]))
-15-:	398	if (trans_cnt_oflw_error_o)
-16-:	411	if ((lc_clk_byp_req_o != lc_clk_byp_ack[1]))
-17-:	418	if (otp_prog_ack_i)
-18-:	419	if (otp_prog_err_i)
-19-:	431	if (trans_invalid_error_o)
-20-:	446	if (token_hash_ack_i)
-21-:	452	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-22-:	466	if ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}))
-23-:	468	if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[0]))
-24-:	482	if (trans_invalid_error_o)
-25-:	487	if (((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_false_strict(lc_flash_rma_ack_buf[1])) || (((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_req_o)) && lc_ctrl_pkg::lc_tx_test_true_strict(lc_flash_rma_ack_buf[1]))))
-26-:	493	if ((((hashed_token_i == hashed_token_mux) && (!token_hash_err_i)) && (&hashed_token_valid_mux)))
-27-:	496	if ((fsm_state_q == TokenCheck1St))
-28-:	524	if ((lc_clk_byp_req_o != lc_clk_byp_ack[2]))
-29-:	529	if ((((trans_target_i != {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != Off) || (lc_flash_rma_ack_buf[2] != Off))) || ((trans_target_i == {lc_ctrl_state_pkg::DecLcStateNumRep {DecLcStRma}}) && ((lc_flash_rma_req_o != On) || (lc_flash_rma_ack_buf[2] != On)))))
-30-:	535	if (otp_prog_ack_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	-18-	-19-	-20-	-21-	-22-	-23-	-24-	-25-	-26-	-27-	-28-	-29-	-30-	Status	Tests	Exclude Annotation
ResetSt	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ResetSt	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	0	1	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Excluded		VC_COV_UNR
IdleSt	-	-	0	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	0	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	0	0	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
IdleSt	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
ClkMuxSt	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntIncrSt	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
CntProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TransCheckSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	-	-	Not Covered
TokenHashSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	-	-	-	-	-	Not Covered
FlashRmaSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	1	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	1	0	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	0	-	-	-	-	Not Covered
TokenCheck0St TokenCheck1St	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	-	-	-	-	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	-	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	1	-	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	1	Not Covered
TransProgSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	0	0	Not Covered
ScrapSt PostTransSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
EscalateSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
InvalidSt	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	567	if ((esc_scrap_state0_i || esc_scrap_state1_i))
-2-:	574	if ((((|state_invalid_error) | token_if_fsm_err_i) && (fsm_state_q != EscalateSt)))

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	584	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	585	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	586	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	589	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	684	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	687	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[1]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	691	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[2]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	694	if (lc_ctrl_pkg::lc_tx_test_true_strict(test_tokens_valid[3]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	698	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[0]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	701	if (lc_ctrl_pkg::lc_tx_test_true_strict(rma_token_valid[1]))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	882	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	608	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered