Unified Coverage Report :: Module :: prim_esc_receiver

Module : prim_esc_receiver

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_esc_0/rtl/prim_esc_receiver.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_esc_receiver0	0.00			0.00
tb.dut.u_prim_esc_receiver1	0.00			0.00

---

Module Instance : tb.dut.u_prim_esc_receiver0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	0.00			0.00

---

Module Instance : tb.dut.u_prim_esc_receiver1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
15.56	0.00	0.00	62.24		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	0.00			0.00

Toggle Coverage for Module : prim_esc_receiver

	Total	Covered	Percent
Totals	7	0	0.00
Total Bits	14	0	0.00
Total Bits 0->1	7	0	0.00
Total Bits 1->0	7	0	0.00

Ports	7	0	0.00
Port Bits	14	0	0.00
Port Bits 0->1	7	0	0.00
Port Bits 1->0	7	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
esc_req_o	No	No		No		OUTPUT
esc_rx_o.resp_n	No	No		No		OUTPUT
esc_rx_o.resp_p	No	No		No		OUTPUT
esc_tx_i.esc_n	No	No		No		INPUT
esc_tx_i.esc_p	No	No		No		INPUT

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver0

Toggle Coverage for Instance : tb.dut.u_prim_esc_receiver1